Final Year Project Presentation

Transistor Modelling Using Verilog A

17 March 2025
Team Members Project Guide

Alfred A J Manju I kollannur

Edwin Thomas C R Asst. Professor
Mohammed Jaseel N J
Powel Prince
Introduction
This project focuses on designing and simulating a CMOS inverter using Verilog-A, a hardware
description language tailored for analog and mixed-signal circuit modeling. The CMOS inverter, a
fundamental building block in digital logic, is widely used in various applications, including signal
processing and memory design. The project aims to provide an in-depth understanding of CMOS
inverter functionality, explore its performance characteristics, and demonstrate its behavior through
simulation.
Objectives
• To model the CMOS inverter in Verilog-A, incorporating transistor-level characteristics.
• To simulate the inverter's transient and DC response, analyzing key parameters like
propagation delay, power dissipation, and noise margins.
• To validate the design for potential applications in digital or mixed-signal circuits, such as SRAM
cells or other digital subsystems.
Literature Review
Sl no Title of the Methodology Year
paper
1 Verilog-A An Organic Electrochemical Transistor model written in
modeling of Verilog-A, a high level analog hardware description
Organic language,is presented. Using a polynomial approximation of
Electrochemical the transistor DC characteristics, various phenomena in the
Transistors. operation of the device could be modeled.The error 2021
between experimental and simulated data was estimated
very low for all cases of the simulated results. The model
was imported in HSPICE and several test circuits were
simulated.
2 A Verilog-A based semi In this paper, a Verilog-A based semiclassical model of
classical model for dual gate graphene field effect transistors with gapless
dual gated graphene large-area graphene channels has been
field-effect transistor. presented.Here we have adopted a quasi analytical
modeling approach based on the Boltzmann transport
equation.The explicit expression of drain to source
current has been derived. The small signal parameters
2023
like drain conductance and transconductance have
been derived.Our model shows good agreement with
experimental data in literature. A Verilog-A code has
been developed for this model and we have designed a
single ended frequency doubler in the Cadence Design
environment using this Verilog-A model.
Methodology
• Analyze areas for improvement in the current inverter design.
• Refer ieee and other research papers to gain knowledge about current trends.
• Set Linux environment and Xyce open source tools for Verilog A and spice simulation.
• Implement the design in ADS commercial software.
• Check whether design have met the objectives.
Diode Chara
Circuit Diagram Spice code

v1 1 0 5v
R1 1 2 1k
D1 2 0 name
.MODEl name D
.DC v1 0 1 0.05
.print DC v1 I(D1)
.end
Output Graph
Diode Clipper
Circuit Diagram Spice Code

V1 in 0 DC 0V AC 1V SIN(0 1 1k)
R1 in node1 1k
D1 node1 0 D1_MODEL
model D1_MODEL D(IS=1E-14)
.print tran V(in) V(node1)
.print tran I(V1)
.tran 0.01ms 5ms
.end
Output Graph
RLC Circuit
Circuit Diagram Spice Code

V1 in 0 DC 0V AC 1V SIN(0 1 1k)
R1 in n1 1k
L1 n1 n2 1mH
C1 n2 0 1uF
.tran 0.01ms 5ms
.print tran V(in) V(n1) V(n2)
.print tran I(R1) I(L1) I(C1)
.end
Output Graph
RC Lowpass Filter
Circuit Diagram Spice Code

V1 n1 0 DC 0V AC 1V SIN(0 1 1k)
R1 n2 n1 1k
C1 n2 0 1uf
.AC DEC 100 10 350
.PRINT AC V(n2)
.END
Output Graph
NMOS Modelling
Parameter Our Value Ideal Value
Vt (Threshold voltage) 0.2 V 0.2 V - 0.7 V

Γ (Body-effect coefficient) 0.01 V^0.5 0.3 - 0.5 V^0.5

Λ (Channel length modulation parameter) 0.02 1/V 0.01 - 0.1

ls (Saturation current) 0.0823e-5 A 10^-6 - 10^-12 A

Φ (Surface potential) 0.9 V 0.6 - 1.0 V

C_ox (Oxide capacitance per unit area) 0.2e-6 F/m^2 10^-3 - 10^-7 F/m^2

K (Process transconductance parameter) 1.218e-4 A/V^2 10^-5 - 10^-12 A/V^2

Vbs (Bulk source voltage) 0 V 0 V (Typical)

Netlist
Circuit Diagram Spice Code

M1 3 2 1 1 N1
M2 3 2 0 0 N2
vdd 1 0 1.5
vin 2 0 0 pulse(0 5 0 1ms 1ms 5ms 10ms)
.model N1 PMOS
.model N2 NMOS (level=78)
*.DC vin 0 1.5 0.1
.tran 10 100ms
*.PRINT DC v(2) v(3)
.print tran v(2) v(3)
.end
Result

CMOS Voltage Transfer Characteristic(VTC)

CMOS Transient Analysis
ADS Software Output
 Parameters Our Values Level 1 CMOS Model
Switching Threshold Voltage (Vth) 0.9 V 0.7 - 0.9 V

Maximum Gain -6.88 -10 to -20

High Output Voltage (VoH) 1.50 V Vdd=1.5 V

Low Output Voltage (VOL) 0V 0V

Input Low Voltage (VIL) 0.8 V 0.3 V - 0.5 V

Input High Voltage (VIH) 1.0 V 1.0 V - 1.2 V

High Noise Margin (NMH) 0.50 V 0.75 V

Low Noise Margin (NML) 0.80 V 0.75 V

Conclusion
● Lower power consumption due to reduced body effect, thinner oxide, and lower leakage
current.
● Faster switching due to optimized threshold voltage and capacitance.
● Better noise immunity for stable digital logic operation.
● More predictable behavior due to controlled channel-length modulation.
● Balanced gain ensures power-efficient transitions in digital circuits.
Reference
● Janelle Leger, Magnus Berggren and Sue Carter, Chapter 9: Organic Electrochemical Transistors
for Sensor Applications, CRC Press, 2011.
● D. A. Bernards and G. G. Malliaras, "Steady-State and Transient Behavior of Organic
Electrochemical Transistors", Advanced Functional Materials, vol. 17, no. 17, pp. 3538-3544, Nov.
2007.
● J. T. Friedlein, S. E. Shaheen, G. G. Malliaras and R. R. McLeod, "Optical Measurements Revealing
Nonuniform Hole Mobility in Organic Electrochemical Transistors", Advanced Electronic
Materials, vol. 1, no. 11, Nov. 2015.
● Y. H. Jun and S. B. Park, "Piecewise polynomial models for MOSFET DC characteristics with
continuous first order derivative", IEE Proceedings G - Electronic Circuits and Systems, vol. 135,
no. 6, pp. 241-246, Dec. 1988.
● D.A. Bernards, R.M. Owens and G.G. Malliaras, Chapter 9: PEDOT:PSS-Based Electrochemical
Transistors for Ion-to-Electron Transduction and Sensor Signal Amplification, Springer, 2008.
Thank you….