1.
Difference between RAM and ROM in PIC microcontrollers
• RAM (Random Access Memory) is a volatile memory used to store temporary data
during the execution of programs. It stores variables, stack data, and intermediate
results.
• ROM (Read-Only Memory) is non-volatile and used to permanently store the
program code written by the user. It retains its contents even after the power is off.
2. List two addressing modes of the PIC microcontroller
1. Immediate Addressing Mode: The operand is specified directly in the instruction.
Example: MOVLW 0x55 moves the value 0x55 to the W register.
2. Direct Addressing Mode: The address of the operand is given explicitly in the
instruction.
Example: MOVWF 0x20 stores the value of W into file register 0x20.
3. Write the function of coprocessors in ARM architecture
Coprocessors in ARM architecture extend the functionality of the CPU by handling specific
tasks such as:
• Performing complex mathematical computations (e.g., floating-point operations).
• Supporting signal processing.
• Managing memory protection and system control (e.g., CP15 in ARM).
They improve performance by offloading tasks from the main CPU.
4. Define the term "interrupt" and its importance in ARM microcontrollers
An interrupt is a mechanism that temporarily halts the normal execution of the program to
respond to urgent events or signals.
• In ARM microcontrollers, interrupts allow real-time response to hardware events
(e.g., timers, I/O signals).
• They improve system efficiency by enabling multitasking and quick handling of
asynchronous events.
5. Compare and Contrast Flash and EEPROM memory
Feature Flash Memory EEPROM
Erase Type Block or sector-wise Byte-wise
Speed Faster Slower
Durability Fewer write/erase cycles Higher write endurance
Use Program storage in microcontrollers Storing small data like configuration
6. Define the purpose of serial communication in ARM microcontrollers
Serial communication in ARM microcontrollers is used to transfer data one bit at a time
over a communication channel such as:
• UART, SPI, or I2C protocols.
• It facilitates communication between the microcontroller and peripherals like
sensors, memory, and computers.
• It is essential for data logging, debugging, and device-to-device communication.
7. Write the importance of the Thumb instruction set in ARM programming
The Thumb instruction set in ARM provides 16-bit compact instructions instead of the 32-
bit ARM instructions.
• Reduces code size, making it ideal for memory-constrained systems.
• Improves execution efficiency and performance in embedded applications.
• Maintains compatibility with the full ARM instruction set.
8. Mention the applications of filters implemented on ARM microcontrollers
Filters on ARM microcontrollers are used for:
• Signal conditioning in sensor data processing.
• Noise reduction in analog-to-digital conversions.
• Audio signal processing in multimedia systems.
• Control systems in robotics and industrial automation.
9. How does a PIC microcontroller generate gate signals for inverters?
PIC microcontrollers generate gate signals using:
• PWM (Pulse Width Modulation) modules to control the timing and width of pulses.
• These PWM signals are used to switch power electronic devices (like MOSFETs or
IGBTs) in inverters.
• The signal pattern is controlled by firmware to ensure proper operation and voltage
regulation.
10. Define a standalone data acquisition system
A standalone data acquisition system is an embedded system that:
• Collects, processes, and stores data from various sensors.
• Operates independently without needing a host PC.
• Examples include weather monitoring systems, industrial data loggers, and
environmental data collectors.
PART A – (10 × 2 = 20 Marks)
1. Applications of PIC Microcontroller:
o PIC microcontrollers are widely used in a variety of embedded applications
due to their flexibility and low power consumption. Some applications
include:
▪ Home automation systems (e.g., smart lighting, HVAC control)
▪ Robotics and mechatronics (e.g., motor control, sensor integration)
▪ Automotive electronics (e.g., dashboard systems, sensor monitoring)
▪ Industrial control systems (e.g., PLCs, factory automation)
▪ Consumer electronics (e.g., microwave ovens, washing machines)
2. I/O Ports in PIC Microcontroller:
o Depending on the PIC variant, common I/O ports include:
▪ PORTA: Often used for analog input or general-purpose digital I/O.
▪ PORTB: Digital I/O with interrupt-on-change capability.
▪ PORTC: Supports UART, SPI, I2C, and digital I/O.
▪ PORTD and PORTE: Available in higher-end PICs, often used for
parallel communication or LCD interfacing.
3. Expand CPSR and SPSR in ARM:
o CPSR: Current Program Status Register – holds condition flags (Zero, Carry,
Negative, Overflow), control bits (interrupt mask), and processor mode bits.
o SPSR: Saved Program Status Register – used to save CPSR when switching
modes (e.g., during exceptions).
4. External Interrupts of ARM:
o IRQ (Interrupt Request): Standard interrupt with lower priority.
o FIQ (Fast Interrupt Request): High-priority interrupt with faster context
switching.
o External sources can trigger these through GPIO pins configured as interrupt
inputs.
5. Advantages of EEPROM over Flash:
o Byte-wise erasability (Flash erases in blocks or pages)
o More write-erase cycles (higher endurance)
o Ideal for storing non-volatile configuration data or small logs
o Faster write and update operations compared to flash
6. Functions of CCP Modules:
o Capture: Records the value of Timer when an event occurs on a pin.
o Compare: Generates an output event when the timer reaches a certain
value.
o PWM (Pulse Width Modulation): Controls devices like motors or LED
brightness.
7. Thumb Mode in ARM:
o A 16-bit compressed instruction set that improves code density.
o Suitable for memory-constrained applications.
o Increases performance by reducing instruction size and memory bandwidth.
o Supported in ARM7TDMI and newer cores.
8. Addition Instruction in ARM:
o ADD R0, R1, R2
o Adds the contents of registers R1 and R2, stores the result in R0.
o Syntax: ADD destination, operand1, operand2
9. Define Hamming Code:
o A method of error detection and correction.
o Detects and corrects single-bit errors and detects double-bit errors.
o Uses parity bits at specific positions to ensure correctness.
10. What is DAS?
o Data Acquisition System (DAS): A system used to acquire, process, and
store physical parameters like temperature, pressure, or voltage.
o Interfaces with sensors and converts analog signals into digital data for
monitoring and analysis.
PART B — (5 × 13 = 65 marks)
Q11 (a): Describe the architecture of the PIC microcontroller, detailing the memory
organization and its impact on performance.
1. Overview of PIC Microcontroller Architecture:
• PIC (Peripheral Interface Controller) microcontrollers are RISC-based devices
by Microchip.
• Architecture: Harvard architecture (separate buses for instruction and data
memory).
• Key components:
o CPU core
o Flash Program Memory
o RAM (Data Memory)
o EEPROM (non-volatile data storage)
o Timers/Counters
o Interrupt controller
o I/O ports
o Serial communication modules (USART, SPI, I2C)
2. Memory Organization:
• Program Memory (Flash):
o Stores user-written program code.
o Non-volatile.
o Size depends on the model (e.g., 1K to 128K+).
• Data Memory (RAM):
o Volatile memory used during execution.
o Used for variable storage and stack.
• EEPROM:
o Stores data even after power-off.
o Useful for storing calibration constants, settings.
• Memory Banking:
o RAM is organized into banks.
o Bank selection done using RP0, RP1 bits in the STATUS register.
3. Memory Map:
• Program Memory starts at 0x0000.
• Interrupt vector at 0x0004.
• RAM memory (data memory) is divided into general-purpose and special-
function registers (SFRs).
4. Performance Impact:
• Harvard architecture allows instruction fetch and data operations to occur
simultaneously → faster execution.
• RISC instruction set allows single-cycle execution (most instructions).
• Banked memory can cause complexity but allows extended memory access.
Q12 (a): Discuss the role of interrupts in ARM microcontrollers and explain how they
manage and prioritize tasks.
1. What is an Interrupt?
• An interrupt is a signal that causes the CPU to temporarily halt the current
execution and service an event (like a peripheral needing attention).
2. Types of Interrupts in ARM:
• IRQ (Interrupt Request): Normal interrupt, lower priority.
• FIQ (Fast Interrupt Request): Higher priority, fast response.
• Software Interrupts: Triggered by executing a special instruction.
• External/Internal Interrupts: From hardware peripherals or internal sources.
3. Vector Table:
• ARM processors have an interrupt vector table at a fixed memory location
containing addresses of ISR (Interrupt Service Routines).
4. Interrupt Management:
• On interrupt:
o CPU saves the current context (registers).
o Jumps to ISR.
o Restores context after servicing.
• NVIC (Nested Vectored Interrupt Controller) in Cortex-M handles:
o Prioritization.
o Masking/enabling.
o Nesting of interrupts.
5. Prioritization:
• NVIC assigns programmable priority levels.
• Allows pre-emption (higher priority interrupt can interrupt lower one).
• Prevents critical task starvation via tail-chaining and latency control.
6. Advantages:
• Efficient resource usage (no polling).
• Fast response to real-time events.
• Allows multitasking in embedded systems.
Q13 (a): Explain the structure and operation of EEPROM in both PIC and ARM
microcontrollers and highlight their differences and applications.
1. EEPROM Overview:
• Electrically Erasable Programmable Read-Only Memory.
• Non-volatile: retains data after power off.
• Byte-level read/write access.
2. EEPROM in PIC:
• Embedded as internal EEPROM.
• Accessed via registers: EEDATA, EEADR, EECON1, EECON2.
• Requires write sequence for safety:
o Set address in EEADR.
o Load data into EEDATA.
o Enable write, unlock using EECON2 (write 0x55 and 0xAA).
• Slower writes; interrupt disabled during operation.
3. EEPROM in ARM (External or simulated):
• Not always embedded; usually external I2C EEPROM chips.
• Interfaced via I2C/SPI using GPIO.
• Controlled through drivers/APIs.
• EEPROM emulation also possible using Flash memory.
4. Comparison Table:
Feature PIC EEPROM ARM EEPROM (External/Emulated)
Access Built-in, simple Requires communication protocol
Speed Slower Faster via DMA in some cases
Size Few KBs Higher capacity possible
Control Direct via registers Via software or APIs
5. Applications:
• Store calibration data, user configurations, passwords, device IDs.
Q14 (a): Discuss how the Thumb instruction set optimizes code density and
performance in ARM microcontrollers.
1. Thumb Instruction Set:
• 16-bit compressed version of the 32-bit ARM instructions.
• Used in ARM7TDMI, Cortex-M series.
• Offers reduced code size with minimal performance loss.
2. Features:
• Executes in Thumb mode.
• Reduced instruction size = more instructions fit into memory.
• Faster instruction fetch due to smaller size.
3. Advantages:
• Code Density: Saves flash/RAM memory.
• Execution Speed: Improved fetch rate; better suited for slow memory systems.
• Power Efficiency: Reduced memory access saves power.
• Ideal for Embedded Systems: Where cost and space are constraints.
4. Performance:
• Slight reduction in raw performance vs ARM (due to limited instruction set).
• However, higher cache efficiency improves real-world speed.
5. Switching Between Modes:
• ARM and Thumb interworking possible via the BX instruction.
Q15 (a): Discuss the use of Hamming code in microcontroller programming for error
detection and correction, and provide a programming example in ARM.
1. Hamming Code Basics:
• Error detection and correction method.
• Introduces redundant bits (parity bits) into data.
• Capable of correcting single-bit errors and detecting two-bit errors.
2. Working Principle:
• Data bits and parity bits are arranged at powers of 2 positions.
• Each parity bit checks certain bits in the sequence.
• At receiver, parity is recalculated and compared.
• Error position = binary combination of failing parity bits.
3. Hamming Code Calculation Example:
• For 4-bit data: d3 d2 d1 d0, parity bits added: p1, p2, p4
• Total bits = 7.
• Error detection via syndrome calculation.
4. Applications in Microcontrollers:
• ECC (Error Correction Code) in Flash or RAM.
• Space applications, automotive systems.
• Reliable sensor data communication.
5. Programming Example (Pseudocode - ARM-like logic):
CopyEdit
uint8_t encodeHamming(uint8_t data) {
uint8_t d0 = (data >> 0) & 1;
uint8_t d1 = (data >> 1) & 1;
uint8_t d2 = (data >> 2) & 1;
uint8_t d3 = (data >> 3) & 1;
uint8_t p1 = d0 ^ d1 ^ d3;
uint8_t p2 = d0 ^ d2 ^ d3;
uint8_t p4 = d1 ^ d2 ^ d3;
uint8_t encoded = (p1 << 0) | (p2 << 1) | (d0 << 2) | (p4 << 3) |
(d1 << 4) | (d2 << 5) | (d3 << 6);
return encoded;
PART B – (5 × 13 = 65 Marks)
11. (a) Architecture of PIC Microcontroller
The architecture of a PIC microcontroller is based on the Harvard architecture, which has
separate buses for program and data memory. This allows simultaneous access, improving
performance.
Key Components:
• Central Processing Unit (CPU): Executes instructions, handles arithmetic/logical
operations.
• Program Memory (Flash): Stores the program code.
• Data Memory (SRAM): Temporarily holds variables and stack data.
• EEPROM: Non-volatile memory used for data retention after power-off.
• I/O Ports: Interface to external peripherals (PORTA–PORTE).
• Timers/Counters: Perform timing operations, event counting.
• ADC (Analog to Digital Converter): Converts analog inputs into digital format.
• CCP Module: Used for Capture, Compare, PWM.
• USART/USART: Communication modules for serial data transfer.
• Interrupt Controller: Manages and prioritizes interrupt events.
Impact of Memory Organization:
• Harvard architecture allows instruction and data fetches to occur simultaneously.
• Increases execution speed.
• RISC design (Reduced Instruction Set Computing) offers fast execution (1
instruction per cycle).
(Diagram: Include CPU at center, connected to Program Memory, Data Memory,
Peripherals, Timers, etc.)
11. (b) Registers of PIC Microcontroller
PIC microcontrollers contain various types of registers:
1. General Purpose Register (WREG):
o Working register used in arithmetic and logic operations.
2. Status Register (STATUS):
o Holds ALU status flags: Z (Zero), C (Carry), DC (Digit Carry), and RP (Register
Bank Select).
3. File Select Register (FSR) and INDF:
o Used for indirect addressing.
4. Program Counter (PC):
o Holds the address of the next instruction.
5. PCL and PCLATH:
o PCL: Low byte of the Program Counter.
o PCLATH: High byte (used during jumps/calls).
6. INTCON:
o Controls interrupt enable and flags.
7. TRISx and PORTx:
o TRIS: Data direction register for I/O.
o PORT: Actual I/O register.
8. OPTION_REG:
o Configures timers, pull-up resistors, interrupt edge.
9. TMR0, TMR1, TMR2:
o Timer/counter registers.
10. ADCON0 and ADCON1:
o Configure ADC channel and operation.
11. TXREG and RCREG:
o Transmit and receive data registers for USART.
PART C – (1 × 15 = 15 Marks)
16. (a) Create a simple program in ASM/C to implement a block copy subroutine in an
ARM microcontroller, explaining its purpose and each line of the code.
Introduction
A block copy subroutine copies a block of memory (array/data) from a source location to a
destination. This is common in memory management, buffer copying, and initialization
tasks.
Below is a simple Assembly (ASM) program for ARM that performs block copying.
Assumptions
• ARM7 architecture (e.g., LPC2148).
• Source and destination addresses are in RAM.
• Copying N bytes of data.
Program (ARM ASM)
asm
CopyEdit
AREA BlockCopy, CODE, READONLY
ENTRY
MOV R0, #0x40000000 ; R0 = source base address
MOV R1, #0x40000100 ; R1 = destination base address
MOV R2, #0x10 ; R2 = count = 16 bytes
CopyLoop
LDRB R3, [R0], #1 ; Load byte from source and post-increment R0
STRB R3, [R1], #1 ; Store byte to destination and post-increment R1
SUBS R2, R2, #1 ; Decrement count
BNE CopyLoop ; Repeat until R2 == 0
B .
END
Line-by-Line Explanation
Instruction Explanation
AREA BlockCopy,... Defines the code segment named "BlockCopy".
ENTRY Entry point for execution.
MOV R0, #0x40000000 Load source start address into R0.
MOV R1, #0x40000100 Load destination start address into R1.
MOV R2, #0x10 Set loop counter to 16 (i.e., copy 16 bytes).
CopyLoop: Label marking start of loop.
LDRB R3, [R0], #1 Load 1 byte from address in R0 to R3 and increment R0.
STRB R3, [R1], #1 Store byte from R3 to address in R1 and increment R1.
SUBS R2, R2, #1 Decrement byte counter; updates flags.
BNE CopyLoop If R2 ≠ 0, branch to CopyLoop.
B. Infinite loop (end of program).
Purpose of Code
This subroutine efficiently transfers a block of data from one memory location to another
using ARM’s post-indexed addressing mode and loop structure.
Applications
• DMA buffer replication
• Bootloader firmware copying
• Initializing or restoring memory regions
16. (b) Describe the ARM programmer’s model and explain the function of registers
within it.
Introduction
The ARM programmer's model defines the set of registers and the status/control
mechanisms visible to the programmer. ARM uses a load/store RISC architecture with a
uniform set of general-purpose registers.
ARM Programmer’s Model (ARM7/ARM Cortex-M)
1. General Purpose Registers (R0–R12)
• Total: 13
• Used for data operations, parameter passing, temporary variables.
• Example:
o R0–R3: Used to pass function arguments and return values.
o R4–R12: Used for general-purpose local variables.
2. Stack Pointer (R13 / SP)
• Points to the current top of the stack.
• Automatically used in function calls, interrupts, and local storage.
• Modified using PUSH/POP instructions.
3. Link Register (R14 / LR)
• Stores return address when a function or subroutine is called using BL (Branch with
Link).
• Can be manipulated manually to implement context switching in embedded OS.
4. Program Counter (R15 / PC)
• Holds the address of the next instruction to be executed.
• Automatically incremented as instructions are fetched.
5. Program Status Registers
• CPSR (Current Program Status Register):
o Holds condition flags (N, Z, C, V), interrupt disable bits, processor mode bits.
o Affects conditional execution and exception handling.
Flag Description
N Negative result
Z Zero result
C Carry out
V Overflow occurred
• SPSR (Saved Program Status Register):
o Used in exception modes to store previous CPSR values.
6. Processor Modes in ARM
ARM has multiple operating modes:
• User: Normal execution.
• FIQ: Fast interrupt.
• IRQ: Standard interrupt.
• Supervisor: OS-level tasks.
• Abort: Memory error.
• Undefined: Invalid instruction.
• System: Privileged mode for OS tasks.
Each mode can have its own banked registers for R13, R14, and SPSR to prevent context
conflicts.
Diagram: ARM Programmer's Model
pgsql
CopyEdit
+-------------------------+
| R15 – Program Counter |
+-------------------------+
| R14 – Link Register |
+-------------------------+
| R13 – Stack Pointer |
+-------------------------+
| R0 – R12 – General Regs |
+-------------------------+
| CPSR – Status Register |
+-------------------------+
| SPSR – (in exception) |
+-------------------------+
Significance in Embedded Systems
• Efficient function call/return via LR and PC.
• Stack-based memory allows for real-time context switching.
• CPSR enables condition-based instruction execution.
• Separate modes and banked registers aid secure interrupt handling.
Conclusion
The ARM programmer’s model offers a simple but powerful set of registers that facilitate
fast processing, modular programming, and reliable interrupt handling—all vital in real-
time embedded systems.
PART C – (1 × 15 = 15 Marks)
16. (a) ARM Assembly Program: Block Copy Subroutine
AREA BlockCopy, CODE, READONLY
ENTRY
; R0 - Source address
; R1 - Destination address
; R2 - Number of words to copy
MOV R0, #0x20000000 ; Load source base address into R0
MOV R1, #0x20000010 ; Load destination base address into R1
MOV R2, #10 ; Set loop counter for 10 words
CopyLoop
LDR R3, [R0], #4 ; Load a word from address in R0 into R3, increment R0 by 4
STR R3, [R1], #4 ; Store word in R3 into address in R1, increment R1 by 4
SUBS R2, R2, #1 ; Decrement counter R2
BNE CopyLoop ; If R2 is not zero, branch to CopyLoop
END
Line-by-Line Explanation:
• MOV R0, #0x20000000: Sets source memory location.
• MOV R1, #0x20000010: Sets destination memory location.
• MOV R2, #10: Specifies number of 32-bit words to copy.
• LDR R3, [R0], #4: Loads word from source address into R3, increments R0.
• STR R3, [R1], #4: Stores R3 into destination address, increments R1.
• SUBS R2, R2, #1: Decreases the count and updates condition flags.
• BNE CopyLoop: Branches to CopyLoop if R2 != 0.
Purpose:
• Efficiently copies a block of memory from one location to another using ARM
instructions.
• Useful in embedded systems for moving sensor data, buffers, etc.
16. (b) ARM Programmer's Model and Register Function
The ARM programmer's model provides a structured view of all accessible registers and
components from a programmer's perspective.
Registers in ARM (in User Mode):
1. General Purpose Registers (R0–R12):
o Used for data manipulation and storage.
2. Stack Pointer (SP/R13):
o Points to the top of the current stack.
o Used during function calls, exception handling.
3. Link Register (LR/R14):
o Stores return address when a function is called using BL (Branch with Link).
4. Program Counter (PC/R15):
o Points to the address of the next instruction to be executed.
5. CPSR (Current Program Status Register):
o Holds status flags (Zero, Carry, Negative, Overflow), interrupt masks, and
mode bits.
o Critical for conditional execution and system state.
6. SPSR (Saved Program Status Register):
o Available in exception modes.
o Saves CPSR during exception entry, restored during return.
Processor Modes:
• User Mode: Normal program execution.
• FIQ Mode: Fast interrupt handling.
• IRQ Mode: Standard interrupt handling.
• Supervisor Mode: Operating system privilege mode.
• Abort/Undefined/System Modes: Handle invalid instructions/memory access.
Usage and Importance:
• The register model allows multitasking, nested interrupts, context switching.
• Enables efficient subroutine handling with SP and LR.
• CPSR allows flexible control of execution via flags.
Conclusion:
Understanding and efficiently using the ARM register model is critical to developing
optimized embedded software and handling low-level hardware interaction.
