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Lab5 Cache System

The document outlines a lab activity for CSI 251/CSI 263 focused on cache simulation, including participation activity 5.1.4 related to cache terminology and memory hierarchy. It explains the concepts of hit rate, miss rate, hit time, and miss penalty, as well as direct cache mapping and the mechanics of cache simulation. Key points include how memory references are mapped to cache blocks and the conditions for cache hits and misses.

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34 views3 pages

Lab5 Cache System

The document outlines a lab activity for CSI 251/CSI 263 focused on cache simulation, including participation activity 5.1.4 related to cache terminology and memory hierarchy. It explains the concepts of hit rate, miss rate, hit time, and miss penalty, as well as direct cache mapping and the mechanics of cache simulation. Key points include how memory references are mapped to cache blocks and the conditions for cache hits and misses.

Uploaded by

mrtbsekati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CSI 251/CSI 263 LAB FRI 26 APRIL

CACHE SIMULATION

1. USE PARTICIPATION ACTIVITY 5.1.4 IN ZYBOOK


PARTICIPATION ACTIVITY
5.1.4: Cache terminology.
A memory hierarchy is composed of an upper level and a lower level. Data are
requested by the processor. 9 out of 10 requests find the data in the upper level and
returns the data in 0.4 ns. The remaining requests require 0.7 ns to return the data.
Determine the corresponding values for the upper level memory.
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Hit rate
Miss rate
Hit time
Miss penalty
2. REVIEW DIRECT CACHE MAPPING

PLEASE TAKE NOTE


• Cache index = x modulo 8 as in above example
• The computation can be done either in binary as in above example
• OR in base 10, then covert back to binary e.g . 12 modulo 8 = 4 = 1002

3. CACHE SIMULATION
Study and understand the simulation below.
1. The three lowest bits of the memory reference are used to
determine which cache block the memory reference is mapped to.
2. The corresponding tag is compared to the upper 2 bits of the
memory reference to determine if the word in the cache
corresponds to the requested word.
3. The valid bit indicates that the cache entry contains valid
information. A cache hit occurs if the valid bit is set and the tag
matches the upper bits of the memory reference.
4. A cache miss occurs if the requested word is not in the cache.
5. Upon a miss, the requested word is fetched from memory and
inserted into the cache.
6. A cache miss also occurs if the cache block does not contain valid
data, which would also result in fetching the requested word from
memory.

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