● What is a microprocessor?

cessor? SRAM: SRAM stands for Static RAM, and it is a particular type of RAM It supports Direct Memory Access (DMA). When an interfacing device
Microprocessor is a controlling unit of a micro-computer, fabricated on a which is faster than DRAM, but more expensive and bulker, having six needs to access the microprocessor, DMA controller places a high input
small chip transistors in each cell. For those reasons SRAM is generally only used as on HOLD line. Microprocessor then relinquishes control of the bus and
capable of performing ALU (Arithmetic Logical Unit) operations and a data cache within a CPU itself or as RAM in very high-end server acknowledges the receipt of the request to the DMA controller. When the
communicating systems. A small SRAM cache of the most imminently -needed data can DMA operation is over, HOLD line will be brought down by the DMA
with the other devices connected to it. Microprocessor consists of an ALU, result in significant speed improvements in a system controller and in turn, CPU will exit from the hold state.
register array, and a control unit. ALU performs arithmetical and logical ● ROM Computer Memory ● Use of ALE pin of 8085?
operations on the data received from the memory or an input device. ROM stands for read-only memory, and the name stems from the fact that A positive going pulse on the ALE line indicates that the bits on AD7 —
Register array consists of registers identified by letters like B, C, D, E, H, L while data can be read from this type of computer memory, data cannot AD0
and accumulator. The control unit controls the flow of data and instructions normally be written to it. It is a very fast type of computer memory which is Are address bits. This signal is utilized to handle the low order address
within the computer. usually installed close to the CPU on the motherboard. ROM is a type of from the multiplexed bus and make a separate set of eight address lines.
● What is a bus?Explain different types of buses in 8085. non-volatile memory, which means that the data stored in ROM persists in ● Use of READY pin of 8085?
Bus is a group of conducting wires which carries information, all the the memory even when it receives no power – for example when the Microprocessor waits until the signal on this line is high to access data
peripherals are computer is turned off. In that sense it is similar to secondary memory, from a peripheral device. This is used to delay the microprocessor Read or
connected to microprocessor through Bus.There are three types of buses which is used for long term storage. Write cycles until a slow peripheral device is ready to access the data.
Address bus,data bus and control bus. PROM: It stands for Programmable Read-Only Memory, and it is different ● Timing diagram
Address bus: It is a group of conducting wires which carries address from true ROM in that while a ROM is programmed (i.e. has data written to Timing Diagram is a graphical representation. It represents the execution
only.Address bus is unidirectional because data flow in one direction, from it) during the manufacturing process, a PROM is manufactured in an time taken by each instruction in a graphical format. The execution time is
microprocessor to memory or from microprocessor to Input/output devices empty state and then programmed later using a PROM programmer or represented in T-states.Instruction Cycle:The time required to execute an
(That is, Out of Microprocessor). Length of Address Bus of 8085 burner. instruction is called instruction cycle.Machine Cycle:The time required to
microprocessor is 16 Bit (That is, Four Hexadecimal Digits), ranging from EPROM: It stands for Erasable Programmable Read-Only Memory, and as access the memory or input/output devices is called machine cycle.T-
0000 H to FFFF H, (H denotes Hexadecimal). the name suggests, data stored in an EPROM can be erased and the State:The machine cycle and instruction cycle takes multiple clock
Data bus: It is a group of conducting wires which carries Data only.Data EPROM reprogrammed. Erasing an EPROM involves removing it from the periods.A portion of an operation carried out in one system clock period is
bus is bidirectional because data flow in both directions, from computer and exposing it to ultraviolet light before re-burning it. called as T-state
microprocessor to memory or Input/Output devices and from memory or EEPROM: It stands for Electrically Erasable Programmable Read-Only ● T-state
Input/Output devices to microprocessor. Memory, and the distinction between EPROM and EEPROM is that the The machine cycle and instruction cycle takes multiple clock periods. A
Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two latter can be erased and written to by the computer system it is installed in. portion of an operation carried out in one system clock period is called as
Hexadecimal Digits), ranging from 00 H to FF H. (H denotes Hexadecimal). In that senseEEPROM is not strictly read-only. However in many cases the T-state.
Control bus: It is a group of conducting wires, which is used to generate write process is slow, so it is normally only done to update program code
timing and control signals to control all the associated peripherals, such as firmware or BIOS code on an occasional basis
microprocessor uses control bus to process data, that is what to do with ● 8085 microprocessor bus organization architecture
selected memory location. Bus is a group of conducting wires which carries information, all the
● Explain the architecture of computer System? peripherals are connected to microprocessors through Bus.
Computer is an electronic machine that makes performing any task very
easy. In computer, the CPU executes each instruction provided to it, in a ● Instruction cycle in 8085
series of steps, this series of steps is called Machine Cycle, and is
repeated for each instruction. One machine cycle involves fetching of
instruction, decoding the instruction, transferring the data, executing the
instruction.

(Adrs bus, Data bus, Control buss definitions needed)

● 8085 microprocessor Architecture with a neat diagram.
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit
The time required to fetch an instruction and necessary data f rom memory
microprocessor designed by Intel in 1977 using NMOS technology. It has and to execute it, is called an instruction cycle. Or the total time required to
● What is a microcontroller? execute an instruction is given by: IC = FC + EC (IC = Instruction Cycle,
A microcontroller is a small and low-cost microcomputer, which is the following configuration −
FC = Fetch Cycle, EC = Execute Cycle)
designed to perform the specific tasks of embedded systems like ● 8-bit data bus ●16-bit address bus, which can address upto 64KB ●A 16- Decode the instruction (Decode Cycle): The opcode fetched f rom the
displaying microwave’s information, receiving remote signals, etc. The bit program counter ●A 16-bit stack pointer ●Six 8-bit registers arranged in memory goes to the data register, DR and then to instruction register, IR.
general microcontroller consists of the processor, the memory (RAM,ROM, pairs: BC, DE, HL ●Requires +5V supply to operate at 3.2 MHZ single From the IR it goes to the decoder circuitry which decodes the instruction.
EPROM), Serial ports, peripherals (timers, counters), etc. phase clock Decoder circuitry is within the microprocessor.
● Microcontroller & Microprocessor- Differentiate It is used in washing machines, microwave ovens, mobile phones, etc. Execute the Instruction (Execute Cycle): After the instruction is decoded,
Microcontroller: Microcontrollers are used to execute a single task within execution begins.
an application * Its designing and hardware cost is low * Easy to replace * If the operand resides in the general purpose registers, execution is
It is built with CMOS technology, which requires less power to operate.* It immediately performed. The time taken in decoding and execution of an
consists of CPU, RAM, ROM, I/O ports. instruction is one clock cycle. In some situations, an execution cycle may
Microprocessor : Microprocessors are used for big applications. * Its involve one or more read or write cycles or both.
designing and hardware cost is high. * Not so easy to replace. * Its power ● Machine cycles of 8085 microprocessors
consumption is high because it has to control the entire system. * It doesn’t The time needed for completing one operation of accessing memory, I/O
consist of RAM, ROM, I/O ports. It uses its pins to interface to peripheral or acknowledging
devices. an external request is termed as Machine cycle. It is composed of T-states.
● Memory classification of computer systems One subdivision of the operation completed in one clock period is termed
A memory is just like a human brain. It is used to store data and as T-state. The 8085 microprocessor has 5 basic machine cycles. They
instructions. Computer Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O are ○ Opcode fetch cycle (4T)○ Memory read cycle (3 T) ○Memory write
Memory is the storage space in the computer, where data is to be & LOAD/STORE operations. It is connected to internal data bus & ALU. cycle (3 T) ○I/O read cycle (3 T) ○I/O write cycle (3 T)
processed and instructions required for processing are stored. The Arithmetic and logic unit: As the name suggests, it performs arithmetic ● opcode fetch machine cycle
memory is divided into large number of small parts called cells. Each and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit
location or cell has a unique address, which varies from zero to memory data.
size minus one. For example, if the computer has 64k words, then this General purpose register: There are 6 general purpose registers in 8085
memory unit has 64 * 1024 = 65536 memory locations. The address of processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data. These
these locations varies from 0 to 65535. registers can work in pair to hold 16-bit data and their pairing combination
Cache Memory: Cache memory is a very high speed semiconductor is like B-C, D-E & H-L.
memory which can speed up the CPU. It acts as a buffer between the CPU Program counter: It is a 16-bit register used to store the memory address
and the main memory. It is used to hold those parts of data and program location of the next instruction to be executed. Microprocessor increments
which are most frequently used by the CPU. The parts of data and the program whenever an instruction is being executed, so that the
programs are transferred from the disk to cache memory by the operating program counter points to the memory address of the next instruction that
system, from where the CPU can access them. is going to be executed.
Primary Memory: Primary memory holds only those data and instructions Flag register: It is an 8-bit register having five 1-bit flip-flops, which holds
on which the computer is currently working. It has a limited capacity and either 0 or 1 depending upon the result stored in the accumulator.
data is lost when power is switched off. It is generally made up of Address buffer and address-data buffer: The content stored in the
semiconductor devices. These memories are not as fast as registers. The stack pointer and program counter is loaded into the address buffer and ●Each instruction of the processor has one byte opcode. ●The opcodes
data and instruction required to be processed resides in the main memory. address-data buffer to communicate with the CPU. The memory and I/O are stored in memory. So, the processor executes the opcode fetch
It is divided into two subcategories RAM and ROM. chips are connected to these buses; the CPU can exchange the desired machine cycle to fetch the opcode from memory. ●Hence, every
Secondary Memory: This type of memory is also known as external data with the memory and I/O chips. instruction starts with the opcode fetch machine Cycle. ●The time taken by
memory or non-volatile. It is slower than the main memory. These are ● Pin configuration of the 8085 microprocessor the processor to execute the opcode fetch cycle is 4T.● In this time, the
used for storing data/information permanently. CPU directly does not Properties: Single + 5V Supply, 4 Vectored Interrupts (One is Non first 3 T-states are used for fetching the opcode from memory and the
access these memories, instead they are accessed via input-output Maskable) Serial In/Serial Out Port. Decimal, Binary, and Double Precision remaining T-states are used for internal operations by the processor.
routines. The contents of secondary memories are first transferred to the Arithmetic. Direct Addressing Capability to 64K bytes of memory. The Intel
main memory, and then the CPU can access it. For example, disk, CD- 8085A is a new generation, complete 8 bit parallel central processing unit
ROM, DVD, etc. (CPU). The 8085A uses a multiplexed data bus. The address is split
● RAM Computer Memory between the 8 bit address bus and the 8 bit data bus. Figures are at the
RAM memory is very fast, it can be written to as well as read, it is volatile end of the document.
(so all data stored in RAM memory is lost when it loses power) and, finally, A6 - A1s (Output 3 State) Address Bus; The most significant 8 bits of the
it is very expensive compared to all types of secondary memory in terms of memory address or the 8 bits of the I/0 address,3 stated during Hold and
cost per gigabyte. It is because of the relative high cost of RAM compared Halt modes. AD0 - 7 (Input/Output 3state) Multiplexed Address/Data Bus;
to secondary memory types that most computer systems use both primary Lower 8 bits of the memory address (or I/0 address) appear on the bus
and secondary memory. during the first clock cycle of a machine state. It then becomes the data
DRAM: DRAM stands for Dynamic RAM, and it is the most common type bus during the second and third clock cycles. 3 stated during Hold and Halt
of RAM used in computers. The oldest type is known as single data rate modes.
(SDR) DRAM, but newer computers use faster dual data rate (DDR) ALE (Output) Address Latch Enable: It occurs during the first clock cycle of
DRAM. DDR comes in several versions including DDR2 , DDR3, and a machine state and enables the address to get latched into the on chip
DDR4, which offer better performance and are more energy efficient than latch of peripherals. The falling edge of ALE is set to guarantee setup and
DDR. However different versions are incompatible, so it is not possible to hold times for the address information. ALE can also be used to strobe the
mix DDR2 with DDR3 DRAM in a computer system. DRAM consists of a status information.ALE is never 3stated.
transistor and a capacitor in each cell. ● Use of HOLD pin of the microprocessor
 ● Memory read machine cycle address. Note that the second byte is the low-order address and the third the stack: Direct method and Indirect method. using either LXI or the SPHL
byte is the high-order address. instruction.
●The memory read machine cycle is executed by the processor to ● Data transfer instructions of the 8085 microprocessor. ● Software interrupts
read a data byte from memory. ●The processor takes 3T states to execute These instructions are used to move data between the registers, or Software Interrupt is invoked by the use of INT instruction. This event
this cycle. The instructions which have more than one byte word size will between memory and the registers. These instructions perform a simple immediately stops execution of the program and passes execution over to
use the machine cycle after the opcode fetch machine cycle task – to copy data from a source to a destination. While copying the the INT handler. The INT handler is usually a part of the operating system
contents stored in the source are not altered. They are also referred to as and determines the action to be taken. It occurs when an application
copy instructions. program terminates or requests certain services from the operating system.
Software interrupts can be classified into two types: 1. Normal Interrupts.
2.Exception
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
● Hardware interrupts
Hardware Interrupt is caused by some hardware device such as a request
to start an I/O, a hardware failure or something similar. Hardware
interrupts were introduced as a way to avoid wasting the processor’s
valuable time in polling loops, waiting for external events.For example,
when an I/O operation is completed such as reading some data into the
● Counter computer from a tape drive. Hardware interrupts can be classified into two
Counters are primarily used to keep track of events types: 1. Maskable Interrupt. 2. Non Maskable Interrupt. They are INTR,
RST 7.5, RST 6.5, RST 5.5, TRAP
● Various interrupts of 8085
When microprocessor receives any interrupt signal from peripheral(s)
which are requesting its services, it stops its current execution and
program control is transferred to a sub-routine by generating CALL signal
● Memory write machine and after executing sub-routine by generating RET signal again program
The memory write machine cycle is executed by the processor to write a control is transferred to main program from where it had stopped.
data byte in a memory location. ●The processor takes 3T states to execute Hardware Interrupts: When microprocessors receive interrupt signals
this machine cycle. through pins (hardware) of microprocessor, they are known as Hardware
Interrupts. There are 5 Hardware Interrupts in 8085 microprocessors. They
are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Example: MVI B,00H ; INITIALIZE COUNTER, LOOP: DCR B ; Software Interrupts: are those which are inserted in between the program
COUNT=COUNT-1, MOV A,B ; MOVE COUNT TO ACC, OUT 01H ; which means these are mnemonics of microprocessor. There are 8
DISPLAY IT AT PORT 01H, JNZ LOOP ; IF COUNT>0 REPEAT software interrupts in the 8085 microprocessor. They are – RST 0, RST 1,
● Time delay RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
Delays are used to set up accurate delays between events. Vectored Interrupts: Vectored Interrupts are those which have fixed
vector address (starting address of sub-routine) and after executing these,
program control is transferred to that address.
Non-Vectored Interrupts: are those in which the vector address is not
predefined. The interrupting device gives the address of the sub-routine for
these interrupts. INTR is the only non-vectored interrupt in an 8085
microprocessor.
Maskable Interrupts: are those which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-
● I/O read machine cycle triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are
*The I/O Read cycle is executed by the processor to read a data byte from maskable interrupts in 8085 microprocessor.
I/O port or from the peripheral, which is I/O,mapped in the system. * The Non-Maskable Interrupts: are those which cannot be disabled or ignored
● Programming techniques and tools.
processor takes 3T states to execute this machine cycle. * The IN by microprocessor. TRAP is a non-maskable interrupt. It consists of both
Looping: It is used to instruct the microprocessor unit to repeat tasks.A
instruction uses this machine cycle during the levels as well as edge triggering and is used in critical power failure
loop is set up by instructing MPU to change sequence of execution and
execution. conditions.
perform the task given.This is accomplished by Jump Instructions.
Loops are of 2 types: • Continuous(repeats a task continuously) • ● SIM and RIM instructions
Conditional(repeats a task until certain data conditions are met) Enable Interrupt(EI) – The interrupt enable flip-flop is set and all interrupts
Indexing: It means counting or referencing objects with sequential are enabled following the execution of the next instruction followed by EI.
numbers.Data bytes are stored in memory location,and those data bytes No flags are affected. After a system reset, the interrupt enable flip-flop is
are referred to by their memory location. reset, thus disabling the interrupts. This instruction is necessary to enable
Counters: This programming technique uses INR or DCR instructions.A the interrupts again (except TRAP).
loop is established to update count and each count is checked to Disable Interrupt (DI) – This instruction is used to reset the value of
determine whether it has reached the final number and if not reached,then enable flip-flop hence disabling all the interrupts. No flags are affected by
the loop is repeated. this instruction.
Time Delay: It is a similar programming technique used to set up a Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts
counter. Register is loaded with a number depending on the time delay (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or
required and then the register is decremented until it reaches generate output data via the Serial Output Data (SOD) line. First the
zero.Register works on the principle of time delay within setting up a loop required value is loaded in accumulator then the SIM will take the bit
with a conditional jump instruction and the loop causes delay depending pattern from it.
upon the lock period of the system. It is achieved by two methods: • Using Read Interrupt Mask (RIM) – This instruction is used to read the status of
a register • Using a register pair the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A
● Various addressing modes of the 8085 register a bytewhich defines the condition of the mask bits for the
● Subroutine
microprocessor interrupts. It also reads the condition of SID (Serial Input Data) bit on the
• A subroutine is a small program written separately from the main
Immediate Addressing Mode: the source operand is always data. If the microprocessor.
program to perform a particular task that you may repeatedly require in the
data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit ● Peripheral device
main program. Essentially, the concept of a subroutine is that it is used to
then the instruction will be of 3 bytes. To communicate with the outside world microcomputers use peripherals
avoid the repetition of smaller programs. • Subroutines are written
Examples: MVI B 45 (move the data 45H immediately to register B), LXI (I/O devices).Commonly used peripherals are: A/D converter, D/A
separately and are stored in a memory location that is different from the
H3050 (load the H-L pair with the operand 3050H immediately), JMP converter, CRT, printers, Hard disks, floppy disks, magnetic tapes etc.
main program. You can call a subroutine multiple times from the main
address (jump to the operand address immediately) Peripherals are connected to the microcomputer through electronic circuits
program using a simple CALL instruction. And a RET instruction is used at
Register Addressing Mode: the data to be operated is available inside known as interfacing circuits.
the end of the subroutine to return to the main program.
the register(s) and register(s) is(are) operands. Therefore the operation is ● Features of 8255A
● Subroutine related instructions of the 8085
performed within various registers of the microprocessor.
microprocessor. The prominent features of 8255A are as follows − ●It consists of 3 8-bit IO
Examples: MOV A, B (move the contents of register B to register A), ADD
The 8085 microprocessor has 4 instructions to implement subroutines. The
B (add contents of registers A and B and store the result in register A), INR ports i.e. PA, PB, and PC. ●Address/data bus must be externally demux'd.
unconditional and conditional CALL and RET instructions. • In
A (increment the contents of register A by one)
unconditional CALL, when a subroutine is called the content of the PC is ●It is TTL compatible. ●It has improved DC driving capability.
Direct Addressing Mode: the data to be operated is available inside a
stored on the stack and the program execution is transferred to the ● PPI or 8255A
memory location and that memory location is directly specified as an
subroutine address. When the unconditional RET instruction is executed, A programmable peripheral interface(PPI) is a multiport device. The ports
operand. The operand is directly available in the instruction itself.
the memory address stored on the stack is retrieved and the sequence of may be programmed in a variety of ways as required by the programmer.
Examples: LDA 2050 (load the contents of memory location into
execution is resumed in the main program. • The conditional CALL and The device is very useful for interfacing peripheral devices. The term PIA,
accumulator A), LHLD address (load contents of 16-bit memory location
RET instructions are based on the four flag register conditions -S,Z,CY Peripheral Interface Adapter is also used by some manufacturers.
into H-L register pair), IN 35 (read the data from port whose address is 35)
and P. The conditions are tesed by checking the respective flags. In The Intel 8255 is a programmable peripheral interface (PPI). It has two
Register Indirect Addressing Mode: the data to be operated is available
conditional CALL , execution control is transferred to the subroutine if the versions, namely the Intel 8255A and Intel 8255A-5. General descriptions
inside a memory location and that memory location is indirectly specified
condition is met. In conditional RET instruction, the control returns to the for both are the same. There are some differences in their electrical
by a register pair.
main program if the condition is met, otherwise the sequence in the characteristics. Its main functions are to interface peripheral devices to the
Examples: MOV A, M (move the contents of thememory location pointed
subroutine is continued. microcomputer.
by the H-L pair to the accumulator), LDAX B (move contents of B-C
● Stack 8255A: The 8255A is a general purpose programmable I/O device
register to the accumulator), LXIH 9570 (load immediate the H-L pair with
The stack is a reserved area of the memory in RAM where we can store designed to transfer the data from I/O to interrupt I/O under certain
the address of the location 9570)
Temporary information. Interestingly, the stack is a shared resource as it conditions as required. It can be used with almost any microprocessor.It
● various instruction formats of 8085
can consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be
An instruction is a command to the microprocessor to perform a given task
Be shared by the microprocessor and the programmer. The programmer configured as per the requirement.
on a specified data. Each instruction has two parts: one is the task to be
Can use the stack to store data. And the microprocessor uses the stack to ● Operating Modes
performed, called the operation code (opcode), and the second is the data
execute subroutines. The 8085 has a 16-bit register known as the ‘Stack Mode 0 - Simple Input/output: The 8255 has two 8-bit ports (Port A and
to be operated on, called the operand. The operand (or data) can be
Pointer.’ its function is to hold the memory address of the stack. This Port B) and two 4-bit ports (Port Cupper and Port Clower). Each port can
specified in various ways. It may include 8-bit (or 16-bit) data, an internal
control is given to the programmer. The programmer can decide the be programmed in either input mode or output mode where outputs are
register, a memory location, or 8-bit (or 16-bit) address. In some
starting address of the stack by loading the address into the stack pointer latched and inputs are not latched. Ports do not have interrupt capability.
instructions, the operand is implicit.
register at the beginning of a program. Mode 1-Strobed Input/output: Mode 1 is strobed input/output mode of
One-word or 1-byte instructions: A 1-byte instruction includes the
● Implement a stack using instructions of 8085 operation. The Port A and Port B both are designed to operate in this
opcode and operand in the same byte. Operand(s) are internal register
The stack works on the principle of First In Last Out. The memory location mode of operation. When Port A and Port B are programmed in Mode 1,
and are coded into the instruction.
of the most recent data entry on the stack is known as the Stack Top. Two six pins of Port C are used for their control.
Two-word or 2-byte instructions: In a two-byte instruction, the first byte
operations used to control the movement of data into a stack and from a Mode 2 -Bidirectional Port: Mode 2 is strobed bidirectional mode of
specifies the operation code and the second byte specifies the operand.
stack. These two instructions are PUSH and POP. PUSH – This is the operation. In this mode, Port A can be configured as the bidirectional port
Source operand is a data byte immediately following the opcode.
instruction to write information on the stack. POP – This is the instruction and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port
Three-word or 3-byte instructions: In a three-byte instruction, the first
to read information from the stack. There are two methods to add data to C as handshake signals for data transfer. The remaining three signals from
byte specifies the opcode, and the following two bytes specify the 16-bit
Port C can be used either as simple I/O or as a handshake for port B.
 ● 8254 programmable interval timer ● Use of the instruction queue
8254 is a device designed to solve the timing control problems in a 6 Byte Prefetch Queue: ●It is a 6 byte queue (FIFO). ●Fetching the next ● 8086 and 8088 microprocessors
microprocessor. It has 3 independent counters, each capable of handling instruction (by BIU from CS) while executing the current instruction is
clock inputs up to 10 MHz and size of each counter is 16 bit. It operates in called pipelining. ●Gets flushed whenever a branch instruction occurs.
+5V regulated power supply and has 24 pin signals. All modes are ● Execution Unit (EU)
software programmable. The 8254 is an advanced version of 8253 which The main components of the EU are General purpose registers, the ALU,
did not offer the feature of read back command. Special purpose registers, Instruction Register and Instruction Decoder
Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to and the Flag/Status Register.
1.Fetches instructions from the Queue in BIU, decodes and executes
interface the 8253/54 to the system data bus. It has three basic functions − arithmetic and logic operations using the ALU. 2.Sends control signals for
●Programming the modes of 8253/54. ●Loading the count registers. internal data transfer operations within the microprocessor. 3.Sends
request signals to the BIU to access the external module. 4.It operates
●Reading the count values. with respect to T-states (clock cycles) and not machine cycles.
Read/Write Logic: It includes 5 signals, i.e. RD, WR, CS, and the address ● General purpose registers in 8086
lines A0 & A1. In the peripheral I/O mode, the RD and WR signals are AX register: It holds operands and results during multiplication and
connected to IOR and IOW, respectively. In the memory mapped I/O mode, division operations. Also an accumulator during String operations.
these are connected to MEMR and MEMW BX register: It holds the memory address (offset address) in indirect
Control Word Register: This register is accessed when lines A0 & A1 are addressing modes.
at logic 1. It is used to write a command word, which specifies the counter CX register: It holds count for instructions like loop, rotate, shift and string
to be used, its mode, and either a read or write operation. Following table operations.
shows the result for various control inputs. DX register: It is used with AX to hold 32 bit values during multiplication
● DMA controller in 8085 and division. ● Segmentation in 8086.
It is a hardware device that allows I/O devices to directlyaccess memory ● Special purpose registers ● Segmentation means dividing the memory into logically different parts
with less participation of the processor. DMA controller needs the same old Stack Pointer: Points to Stack top. Stack is in Stack Segment, used called segments. 8086 has a 20-bit address bus, hence it can access 1MB
circuits of an interface to communicate with the CPU and Input/Output during instructions like PUSH, POP, CALL, RET etc. memory. It is not possible to work with a 20 bit address as it is not a byte
devices. DMA Controller temporarily borrows the address bus,data bus Base Pointer:BP can hold an offset address of any location in the stack compatible number i.e. (20 bits is two and a half bytes). ●To avoid working
and control bus from the microprocessor and transfers the data directly segment. It is used to access random locations of the stack. with this incompatible number, we create a virtual model of the memory.
from the external device to memory location and vice versa. Source Index: It holds an offset address in the Data Segment during Here the memory is divided into 4 segments: Code, Stack Data and Extra.
● 8086 microprocessor string operations. The max size of a segment is 64KB and the minimum size is 16 bytes.
The 8086 Microprocessor is an enhanced version of the 8085 Destination Index: It holds offset addresses in Extra Segment during ●Now programmer can access each location with a VIRTUAL ADDRESS.
Microprocessor that was designed by Intel in 1976. It is a 16-bit string operations The Virtual Address is a combination of Segment Address and Offset
Microprocessor in a 40 pin, Dual Inline Packaged IC. It Has 20 address ● Use of flag registers in 8086 Address. Segment Address indicates where the segment is located in the
lines and16 data lines that provides up to 1MB storage. It consists of a The Flag register is a Special Purpose Register. Depending upon the memory (base address) and Offset Address gives the offset of the target
powerful instruction set, which provides operations like multiplication and value of result after any arithmetic and logical operation the flag bits location within the segment. ●Since both, Segment Address and Offset
division easily. It supports two modes of operation, i.e. Maximum mode become set (1) or reset (0).There are total 9 flags in 8086 and the flag Address are 16 bits each, they both are compatible numbers and can be
and Minimum mode. Maximum mode is suitable for systems having register is divided into two types:Status Flags and Control Flags easily used by the programmer. Hence, we can access 1 MB memory
multiple processors and Minimum mode is suitable for systems having a using only a 16 bit offset address for most part of the program.
single processor. ● Physical address is calculated in 8086.
● Features of the 8086 Physical Address (20 bit) = Segment Address(16 bit) X 10H + Offset
●It has an instruction queue, which is capable of storing six instruction Address (16 bit)
Status Flags – There are 6 flag registers in 8086 microprocessor which
bytes from the memory resulting in faster processing. ●It was the first 16- become set(1) or reset(0) depending upon condition after either 8-bit or
bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16- 16-bit operation.
Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it
bit external data bus resulting in faster processing. ●It is available in 3 indicates the number is negative and the sign flag becomes set, i.e. 1. If
versions based on the frequency of operation − 8086 → 5MHz 8086-2 → the MSB is 0, it indicates the number is positive and the sign flag becomes
The value of Code Segment (CS) Register is 4042H and the value of
reset i.e. 0. from 00H to 7F, sign flag is 0 from 80H to FF, sign flag is 1
8MHz (c)8086-1 → 10 MHz ● It uses two stages of pipelining, i.e. Fetch different offsets is as
Zero Flag (Z) – After any arithmetic or logical operation if the result is 0
follows:BX: 2025H , IP: 0580H , DI: 4247H. Calculate the effective address
(00)H, the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
Stage and Execute Stage, which improves performance. ●Fetch stage can of the memory location pointed by the CS register.
00H zero flag is 1. from 01H to FFH zero flag is 0
prefetch up to 6 bytes of instructions and stores them in the queue. Solution: The offset of the CS Register is the IP register. Therefore, the
Auxiliary Carry Flag (AC) – This flag is used in BCD number system(0-9).
effective address of the memory location pointed by the CS register is
If after any arithmetic or logical operation D(3) generates any carry and
●Execute stage executes these instructions. ●It has 256 vectored calculated as follows:
passes on to B(4) this flag becomes set i.e. 1, otherwise it becomes reset
Effective address= Base address of CS register X 10H + Address of IP
interrupts. ●It consists of 29,000 transistors. i.e. 0. This is the only flag register which is not accessible by the
= 4042H X 10H + 0580H
● Differentiate between 8085 and 8086 programmer1-carry out from bit 3 on addition or borrow into bit 3 on
= (40420 + 0580)H
subtraction 0-otherwise
Size − 8085 is an 8-bit microprocessor, whereas 8086 is a 16-bit = 41000H
Parity Flag (P) – If after any arithmetic or logical operation the result has
microprocessor. even parity, an even number of 1 bits, the parity register becomes set i.e. 1,
otherwise it becomes reset i.e. 0. 1-accumulator has even number of 1 bits
Address Bus − 8085 has a 16-bit address bus while 8086 has a 20-bit
0-accumulator has odd parity
address bus. Carry Flag (CY) – Carry is generated when performing n bit operations
and the result is more than n bits, then this flag becomes set i.e. 1,
Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1
otherwise it becomes reset i.e. 0. During subtraction (A-B), if A>B it
Mb of memory. becomes reset and if (A<B) it becomes set. Carry flag is also called the
borrow flag. 1-carry out from MSB bit on addition or borrow into MSB bit on
Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has
subtraction 0-no carry out or borrow into MSB bit
an instruction queue. Overflow Flag (O) – This flag will be set (1) if the result of a signed
operation is too large to fit in the number of bits available to represent it,
Pipelining − 8085 doesn’t support a pipelined architecture while 8086
otherwise reset (0). After any operation, if D[6] generates any carry and
supports a pipelined Architecture. passes to D[7] OR if D[6] does not generate carry but D[7] generates, the
overflow flag becomes set, i.e., 1. If D[6] and D[7] both generate carry or
I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = both do not generate any carry, then the overflow flag becomes reset, i.e.,
65,536 I/O's. 0.
● Addressing modes of 8086.
Cost − The cost of 8085 is low whereas that of 8086 is high. The way of specifying data to be operated by an instruction is known
● Bus Interface Unit (BIU): as addressing modes. This specifies that the given data is an immediate
It provides the interface of 8086 to external memory and I/O devices data or an address. It also specifies whether the given operand is register
via the System Bus. It performs various machine cycles such as or register pair. Types of addressing modes:1. Register mode – In this
memory read, I/O read etc. to transfer data between memory and I/O type of addressing mode both the operands are registers. Example:MOV
devices. AX, BX ADD AL, BL
●It generates the 20 bit physical address for memory access. ●It 2. Immediate mode – In this type of addressing mode the source operand
fetches instructions from the memory. ●It transfers data to and from is a 8 bit or 16 bit data. Destination operand can never be immediate data.
the memory and I/O. ●Maintains the 6 byte prefetch instruction Example:MOV AX, 2000 ADD AL, 45
queue(supports pipelining). BIU mainly contains the 4 Segment 3. Displacement or direct mode – In this type of addressing mode the
registers, the Instruction Pointer, a prefetch queue and an Address effective address is directly given in the instruction as displacement.
Generation Circuit. Example:MOV AX, [DISP] MOV AX, [0500]
● Instruction pointer in 8086 4. Register indirect mode – In this addressing mode the effective
It is a 16 bit register. It holds the offset of the next instructions in the Code address is in SI, DI or BX. Example:MOV AX, [DI] ADD AL, [BX] MOV AX,
Segment. ●IP is incremented after every instruction byte is fetched. ●IP [SI]
gets a new value whenever a branch instruction occurs. ●CS is multiplied 5. Based indexed mode – In this the effective address is sum of base
by 10H to give the 20 bit physical address of the Code Segment. ●Address register and index register. Base register: BX, BP Index register: SI, DI
of the next instruction is calculated as CS x 10H + IP.
Example: CS = 4321H IP = 1000H, then CS x 10H = 43210H + offset =
44210H. This is the address of the instruction.
● various segment registers used in 8086
Code Segment register: CS holds the base address for the Code
Segment. All programs are stored in the Code Segment and accessed via
the IP.
Data Segment register: DS holds the base address for the Data Segment.
Stack Segment register: SS holds the base address for the Stack
Segment.
Extra Segment register: ES holds the base address for the Extra
Segment.
Address Generation Circuit: ●The BIU has a Physical Address
Generation Circuit. ●It generates the 20 bit physical address using
Segment and Offset addresses using the formula: ●Physical Address =
Segment Address x 10H + Offset Address