Digital fundamentals question banks answers
4 marks
UNIT 1 – 4 MARKS
Q1. Find 1’s complement of: a) (110001)₂ b) (111001)₂
Definition:
1’s complement of a binary number is obtained by inverting all bits — 0 becomes 1 and 1 becomes 0.
Answer:
• a) (110001)₂ → 1’s complement = (001110)₂
• b) (111001)₂ → 1’s complement = (000110)₂
Q2. Simplify the conversion: a) (498)₁₀ to binary b) (160)₁₀ to binary
Definition:
To convert decimal to binary, divide the number by 2 repeatedly and write remainders in reverse.
Answer:
Answer:
a) 498 ÷ 2 = 249 R0
→ 249 ÷ 2 = 124 R1
→ 124 ÷ 2 = 62 R0
→ 62 ÷ 2 = 31 R0
→ 31 ÷ 2 = 15 R1
→ 15 ÷ 2 = 7 R1
→ 7 ÷ 2 = 3 R1
→ 3 ÷ 2 = 1 R1
→ 1 ÷ 2 = 0 R1
(498)₁₀ = (111110010)₂
b) Similar method:
→ (160)₁₀ = (10100000)₂
Q3. Find 2’s complement of (10100)₂
Definition:
2’s complement is obtained by taking the 1’s complement and adding 1 to the result.
Answer:
• 1’s complement of (10100)₂ = (01011)₂
• Add 1 → (01011 + 1) = (01100)₂
Q4. Distinguish between Analog and Digital signals
Definition:
Analog signals are continuous in nature, while digital signals are discrete and binary.
Answer:
Feature Analog Signal Digital Signal
Signal Type Continuous Discrete
Data Form Real-world values Binary (0 and 1)
Waveform Sine wave Square wave
Noise Resistance Low High
Accuracy Less More
Example Radio, Thermometer Computer, Digital Clock
Q5. Evaluate conversion from decimal to octal: a) (79)₁₀ b) (32)₁₀
Definition:
Convert decimal to octal by repeated division by 8 and reading the remainders bottom to top.
Answer:
• a) 79 ÷ 8 = 9 R7
→ 9 ÷ 8 = 1 R1
→ 1 ÷ 8 = 0 R1
(79)₁₀ = (117)₈
• b) 32 ÷ 8 = 4 R0
→ 4 ÷ 8 = 0 R4
(32)₁₀ = (40)₈
UNIT 2 – 4 MARKS
Q1. Construct NAND and NOR gate
Definition:
NAND and NOR gates are universal gates; any logic function can be implemented using them.
Answer:
• NAND Gate:
Truth Table:
A B Y = ¬(A·B)
0 0 1
0 1 1
1 0 1
1 1 0
• NOR Gate:
Truth Table:
A B Y = ¬(A + B)
0 0 1
0 1 0
1 0 0
1 1 0
Q2. Summarize Don’t care method
Definition:
In K-map simplification, 'don't care' conditions (X) represent irrelevant combinations and help in simplification.
Answer:
1. Represented as X in K-map.
2. Can be grouped with 1s to form larger blocks.
3. Helps simplify logic circuits.
4. Common in finite state machines.
5. Makes logic expression minimal.
6. Ignored or treated as 1 during grouping.
Q3. Define K-map
Definition:
K-map (Karnaugh Map) is a visual method for minimizing Boolean expressions using adjacent grouping.
Answer:
1. Developed by Maurice Karnaugh.
2. Grid with cells = minterms.
3. Adjacent cells differ by one variable.
4. Group sizes: 1, 2, 4, 8…
5. Reduces logic gate usage.
6. Used in combinational logic.
UNIT 3 – 4 MARKS
Q1. Explain Demultiplexer
Definition:
A demultiplexer takes a single input and distributes it to one of many outputs based on selection lines.
Answer:
1. 1-to-n format (1 input, n outputs).
2. Uses n = 2^s, where s = select lines.
3. Example: 1x4 Demux → 2 select lines.
4. Output = Input × Selector.
5. Used in communication systems.
6. Serial to parallel converter.
Q2. Construct truth table and logic circuit for 4:2 Encoder
Definition:
A 4:2 encoder encodes 4 input lines into 2 output lines.
Answer:
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
I3 I2 I1 I0 O1 O0
1 0 0 0 1 1
• Outputs:
O1 = I2 + I3
O0 = I1 + I3
• Circuit uses OR gates.
Q3. Explain 1x2 Demultiplexer
Definition:
A 1x2 demultiplexer sends 1 input to one of 2 outputs based on a select line.
Answer:
1. Inputs: 1 data (D), 1 select (S).
2. Outputs: Y0 = D·S’, Y1 = D·S.
3. Uses AND and NOT gates.
4. Only one output active at a time.
5. Example: Data routing.
6. Used in processor control.
UNIT 4 – 4 MARKS
Q1. Define Cascading Counter
Definition:
Cascading is combining two or more counters to increase count range.
Answer:
1. Output of one counter → Clock of next.
2. Common in ripple counters.
3. Expands bit range (e.g., 4-bit → 8-bit).
4. Used in multi-digit timers.
5. Ripple delay may occur.
6. Example: Stopwatch counters.
Q2. Determine benefits of Register
Definition:
Registers are high-speed storage units inside CPUs used to hold data temporarily.
Answer:
1. Fastest memory.
2. Holds intermediate results.
3. Aids arithmetic/logic execution.
4. Acts as buffer for I/O operations.
5. Reduces memory access time.
6. Supports control operations.
Q3. Illustrate symbolic representation for different types of flip-flops
Definition:
Symbolic representation shows the structure and input/output of flip-flops in circuit diagrams.
Answer:
1. SR flip-flop: Inputs S, R; Outputs Q, Q̅
2. D flip-flop: Input D; Output Q
3. T flip-flop: Input T; Toggles output
4. JK flip-flop: Inputs J, K; versatile
5. All flip-flops include clock input.
6. Shapes standardized in logic design.
Q4. Summarize a note on: Flip flop
Definition:
Flip-flops are sequential logic circuits used to store binary data (1 bit each).
Answer:
1. Basic memory elements.
2. Controlled by clock pulses.
3. Used in counters and registers.
4. Types: SR, D, JK, T.
5. Can be edge or level triggered.
6. Stores state information.
UNIT 5 – 4 MARKS
Q1. Discuss on EPROM
Definition:
EPROM (Erasable Programmable Read-Only Memory) can be erased using UV light and reprogrammed.
Answer:
1. Non-volatile memory.
2. Erasable by ultraviolet light.
3. Can be reprogrammed many times.
4. Used for firmware storage.
5. Transparent quartz window on top.
6. Replaced in many cases by EEPROM.
Q2. List out the benefits of counter
Definition:
Counters are circuits that count pulses and are used in digital systems for timing and sequencing.
Answer:
1. Used to count events or time.
2. Required in digital clocks, timers.
3. Helps in instruction sequencing.
4. Used in frequency division.
5. Interfaces with microprocessors.
6. Acts as program step counters.
Q3. Illustrate ROM
Definition:
ROM (Read-Only Memory) stores permanent instructions/data that cannot be modified during normal operation.
Answer:
1. Non-volatile memory.
2. Stores boot instructions.
3. Cannot be written easily.
4. Types: PROM, EPROM, EEPROM.
5. Used in embedded systems.
6. Cannot be modified by user easily.
6 marks
UNIT 1 – 6 MARKS
Q1. Simplify the conversion from decimal to binary: a) (34)₁₀ b) (66)₁₀
Definition:
To convert a decimal number to binary, divide it repeatedly by 2 and write the remainders in reverse order (bottom to top). This
method is known as successive division by 2.
a) (34)₁₀ to Binary:
1. 34 ÷ 2 = 17 R0
2. 17 ÷ 2 = 8 R1
3. 8 ÷ 2 = 4 R0
4. 4 ÷ 2 = 2 R0
5. 2 ÷ 2 = 1 R0
6. 1 ÷ 2 = 0 R1
→ Binary: (34)₁₀ = (100010)₂
b) (66)₁₀ to Binary:
1. 66 ÷ 2 = 33 R0
2. 33 ÷ 2 = 16 R1
3. 16 ÷ 2 = 8 R0
4. 8 ÷ 2 = 4 R0
5. 4 ÷ 2 = 2 R0
6. 2 ÷ 2 = 1 R0
7. 1 ÷ 2 = 0 R1
→ Binary: (66)₁₀ = (1000010)₂
Q2. Elaborate Arithmetic and Logic Unit (ALU) of a computer design
Definition:
The ALU (Arithmetic and Logic Unit) is a fundamental part of the CPU responsible for performing arithmetic operations (like
addition and subtraction) and logic operations (like AND, OR, NOT).
Answer:
1. ALU is part of the processor that handles mathematical operations.
2. Performs arithmetic operations: addition, subtraction, increment, decrement.
3. Performs logical operations: AND, OR, XOR, NOT, comparison.
4. Works with registers and the control unit.
5. Controlled by control signals generated by the control unit.
6. Uses multiplexers and logic gates to process input data.
7. Inputs come from internal CPU registers.
8. Outputs are fed to system bus or stored in registers.
Q3. Explain in brief about the digital computer architecture
Definition:
Digital computer architecture describes the internal structure and working of the computer system components such as the CPU,
memory, and input/output units.
Answer:
1. Input Unit: Takes instructions from user (keyboard, mouse).
2. Central Processing Unit (CPU): Consists of ALU and Control Unit.
3. Arithmetic Logic Unit (ALU): Performs all arithmetic and logic operations.
4. Control Unit: Manages signals and controls data flow between components.
5. Memory Unit: Stores data and instructions temporarily (RAM) and permanently (ROM).
6. Output Unit: Displays result to user (monitor, printer).
7. Bus System: Includes address, data, and control bus for data transmission.
8. Registers: Temporary storage areas inside CPU for fast data access.
Q4. Determine the 1’s and 2’s complement of: a) (1100)₂ b) (1010)₂
Definition:
1’s complement is found by inverting the bits of the binary number.
2’s complement is obtained by adding 1 to the 1’s complement and is widely used for representing negative numbers.
a) (1100)₂
• 1’s complement: (0011)₂
• Add 1 → (0011 + 1) = (0100)₂
• 2’s complement = (0100)₂
b) (1010)₂
• 1’s complement: (0101)₂
• Add 1 → (0101 + 1) = (0110)₂
• 2’s complement = (0110)₂
Q5. Distinguish between octal and decimal number systems
Definition:
The octal number system uses base-8 (digits 0 to 7), whereas the decimal system uses base-10 (digits 0 to 9). Both are positional
number systems.
Answer:
Feature Octal Number System Decimal Number System
Base 8 10
Digits Used 0 to 7 0 to 9
Power of Base Powers of 8 Powers of 10
Common Usage Used in digital systems Used in general mathematics
Conversion Easy from binary Requires conversion for binary
Example (125)₈ = 1×8²+2×8+5 (125)₁₀ = 1×10²+2×10+5
Number of Symbols 8 Symbols 10 Symbols
Representation Length Shorter in binary groups Longer compared to octal
UNIT 2 – 6 MARKS
Q1. Prove the theorem of Boolean Algebra: a) A + 1 = 1, b) A · 1 = A
Definition:
Boolean algebra theorems are rules used to simplify and prove logic expressions.
Answer:
• a) A + 1 = 1 (Dominance Law)
1. A can be either 0 or 1.
2. If A = 0 → 0 + 1 = 1
3. If A = 1 → 1 + 1 = 1
4. Therefore, A + 1 = 1 for all cases.
5. Verified using truth table.
6. Used to simplify logic expressions.
7. Replaces entire expression with constant 1.
8. Removes redundant terms.
• b) A · 1 = A (Identity Law)
1. A can be either 0 or 1.
2. If A = 0 → 0 · 1 = 0
3. If A = 1 → 1 · 1 = 1
4. So, A · 1 = A in all cases.
5. Also proven by truth table.
6. Used in logic gate simplification.
7. Helps reduce logic circuits.
8. Removes unnecessary multiplication with 1.
Q2. Illustrate the truth table and diagram of AND, OR, NOT gates
Definition:
Logic gates are basic building blocks of digital circuits. Each gate performs a specific logic function.
Answer:
• AND Gate
Symbol: A · B
ABY
000
010
100
111
• OR Gate
Symbol: A + B
ABY
000
011
101
111
• NOT Gate
Symbol: A'
AY
01
AY
10
• All three gates can be implemented using diodes and transistors.
• Truth tables validate the gate operations.
• Logic symbols are standardized.
• Used in all digital circuits.
• Can be combined to form complex circuits.
Q3. Minimize using K-map: F(A, B, C) = ∑m(0, 1, 6, 7)
Definition:
Karnaugh Map (K-map) is a method to simplify Boolean expressions by grouping adjacent 1s.
Answer:
1. 3-variable K-map (A, B, C)
2. Enter 1 in cells for minterms 0, 1, 6, 7
3. Group (0,1) → BC'
4. Group (6,7) → A·B
5. Final simplified expression:
F = A·B + B'·C'
6. Reduces gate count in circuits
7. Minimization improves speed and efficiency
8. Can be extended to 4-variable K-map
Q4. Design Ex-NOR and Ex-OR logic circuit
Definition:
Exclusive-OR (XOR) and Exclusive-NOR (XNOR) are special gates used for comparison and parity checking.
Answer:
• XOR (⊕)
Equation: A ⊕ B = A'B + AB'
Truth Table:
ABY
000
011
ABY
101
110
• XNOR (⊙)
Equation: A ⊙ B = AB + A'B'
Truth Table:
ABY
001
010
100
111
6. Circuit built using AND, OR, NOT gates
7. XNOR is complement of XOR
8. Used in arithmetic, comparators
Q5. Construct steps for simplification of Boolean function using K-map
Definition:
K-map simplifies Boolean expressions by grouping minterms in powers of 2 (1, 2, 4, 8, etc.).
Answer:
1. Draw a K-map grid for given variables
2. Enter 1s for the given minterms
3. Identify adjacent 1s (can include don't cares)
4. Group them in pairs, quads, octets
5. For each group, write simplified term
6. Eliminate changing variables
7. Combine all simplified terms
8. Final expression has fewer literals
UNIT 3 – 6 MARKS
Q1. Distinguish between Encoder and Decoder
Definition:
An encoder converts input signals into a binary code. A decoder converts binary code into outputs.
Answer:
Feature Encoder Decoder
Function Converts input to binary code Converts binary to output lines
Inputs 2ⁿ input lines n input lines
Outputs n output lines 2ⁿ output lines
Example 8-to-3 encoder 3-to-8 decoder
Applications Keyboard encoding Memory decoding
Logic Design Uses OR gates Uses AND gates
Priority May use priority encoders Not applicable
Direction Data compression Data expansion
Q2. Discuss Half-Adder in detail
Definition:
A half-adder adds two single binary digits and gives sum and carry as output.
Answer:
1. Inputs: A and B
2. Sum (S) = A ⊕ B = A'B + AB'
3. Carry (C) = A · B
4. Truth table:
ABSC
0 000
0 110
1 010
1 101
5. Logic diagram includes XOR and AND gates
6. Cannot handle carry input
7. Used in simple binary addition
8. First step in building full adder
Q3. Discuss Full-Adder in detail
Definition:
A full-adder adds three binary bits (A, B, Cin) and produces a Sum and Carry output.
Answer:
1. Inputs: A, B, Cin
2. Sum = A ⊕ B ⊕ Cin
3. Carry = AB + BCin + ACin
4. Truth table:
A B Cin S C
000 00
001 10
010 10
011 01
100 10
101 01
110 01
111 11
5. Constructed using two half adders + OR gate
6. Supports carry chaining
7. Used in ALU and arithmetic circuits
8. Basic unit in ripple-carry adder
UNIT 4 – 6 MARKS
Q1. List out the uses of Shift Register to serialize data
Definition:
Shift registers are sequential logic circuits that shift data in or out one bit at a time.
Answer:
1. Convert parallel data to serial (PISO)
2. Store temporary data in communication
3. Used in UARTs and modems
4. Delay elements in digital circuits
5. Generate pseudo-random sequences
6. Perform binary multiplication/division
7. Enable data movement in microcontrollers
8. Act as memory in small systems
Q2. Distinguish between Latch and Flip-Flop
Definition:
Latch is level-triggered memory, while flip-flop is edge-triggered. Both store 1-bit data.
Answer:
Feature Latch Flip-Flop
Trigger Type Level-triggered Edge-triggered
Control Signal Enable Clock
Operation Changes as long as enabled Changes on clock edge
Speed Faster Slightly slower
Usage Small memory elements Counters, registers
Types SR, D SR, D, T, JK
Design Simplicity Simple Slightly complex
Reliability Prone to glitches More reliable
Q3. Illustrate the uses of Flip-Flops
Definition:
Flip-flops are memory elements in sequential circuits that store binary information.
Answer:
1. Used in binary counters
2. Memory storage for 1-bit
3. Registers and buffers
4. Frequency dividers
5. Data synchronization
6. Timing control circuits
7. Toggle switches in circuits
8. Sequence detectors in FSMs
UNIT 5 – 6 MARKS
Q1. Construct a combinational circuit representation of Synchronous Counter
Definition:
Synchronous counters are digital counters where all flip-flops are triggered by a common clock signal.
Answer:
1. Clock input shared by all flip-flops
2. Uses JK or T flip-flops
3. Count advances on clock edge
4. No ripple delay (faster)
5. Circuit uses logic gates to control toggling
6. Example: 3-bit synchronous counter
7. Output follows binary count sequence
8. Used in digital clocks, timers
Q2. Define in detail about Ripple Counters
Definition:
Ripple counter (asynchronous counter) has clock signal applied only to first flip-flop; others are triggered by the previous one’s
output.
Answer:
1. Each flip-flop is triggered by output of previous
2. Least significant FF gets clock input
3. Slow due to propagation delay
4. Simple in design
5. Can be up/down counter
6. Uses T or JK flip-flops
7. Count = 2ⁿ, where n = no. of FFs
8. Used in frequency counters
Q3. Elaborate in brief: a) RAM b) ROM c) PROM
Definition:
Memory types differ by usage, volatility, and write/read capabilities.
Type Full Form Description
RAM Random Access Mem Volatile memory; Read/write
ROM Read Only Mem Non-volatile; Read-only
PROM Programmable ROM Written once after manufacturing
7. RAM is temporary storage
8. ROM/PROM used for firmware
Q4. Summarize note on: a) Synchronous counter b) Asynchronous counter
Definition:
Counters increment numbers based on clock pulses. They are categorized as synchronous or asynchronous.
Feature Synchronous Counter Asynchronous Counter
Clock Input Common to all FFs Given to first FF only
Speed Faster Slower
Delay Minimal Ripple delay
Design Complex Simple
Accuracy High Low for high frequencies
Propagation Parallel Sequential
Example Digital clocks Simple timers
Application High-speed devices Low-speed counting
Q5. Explain up/down ripple counter
Definition:
An up/down ripple counter counts in both ascending and descending binary sequences.
Answer:
1. Uses T or JK flip-flops
2. UP count: 000, 001, 010...
3. DOWN count: 111, 110, 101...
4. Direction controlled by a mode pin
5. Triggering based on output of previous FF
6. Propagation delay exists
7. Used in elevators, scoreboards
8. Simple implementation but slower
10 marks
UNIT 1 – 10 MARKS
Q1. Summarize binary, decimal, octal, and hexadecimal number systems
Definition:
Number systems are ways to represent numbers using different bases. Binary (base 2), Decimal (base 10), Octal (base 8), and
Hexadecimal (base 16) are widely used in digital systems.
Answer:
Feature Binary Decimal Octal Hexadecimal
Base 2 10 8 16
Digits used 0, 1 0–9 0–7 0–9, A–F
Positional value Powers of 2 Powers of 10 Powers of 8 Powers of 16
Application Digital circuits Daily use Digital shortcuts Memory addresses
Example 1010₂ = 10 10₁₀ 12₈ = 10 A₁₆ = 10₁₀
10 key points:
1. Binary: Used in computers, only 0 and 1.
2. Decimal: Our everyday number system.
3. Octal: Used as a shorthand for binary (groups of 3).
4. Hexadecimal: Used for addressing and debugging.
5. Conversion possible between all systems.
6. Binary to Octal: Group 3 bits.
7. Binary to Hex: Group 4 bits.
8. Octal/Hex to Decimal uses positional weights.
9. Conversion improves code efficiency.
10. Represent data in compact form.
11. Reduces human error in large binary strings.
12. Common in microprocessor programming.
13. Used in digital communication and storage.
Q2. Formulate about number system and its different types available in detail
Definition:
Number systems define how numbers are represented and manipulated in computing. Different types use different bases.
Types of Number Systems:
1. Binary (Base 2) – Digits: 0,1 – Used in computers.
2. Decimal (Base 10) – Digits: 0–9 – Used in real-world math.
3. Octal (Base 8) – Digits: 0–7 – Compact binary form.
4. Hexadecimal (Base 16) – Digits: 0–9, A–F – Memory addresses.
5. BCD (Binary Coded Decimal) – Each digit in decimal is represented by 4 bits.
6. Gray Code – Only one bit changes between successive numbers; used in error correction.
7. Signed Number Representation – Sign-Magnitude, 1’s and 2’s Complement.
8. Floating Point Representation – Scientific notation for real numbers.
9. Excess-3 – Modified BCD; used in arithmetic operations.
10. ASCII – Represents characters in digital format.
11. Base-N Systems – Theoretical systems based on any base.
12. Each system serves specific purpose in computing.
13. Conversion between systems is essential for data processing.
Q3. Discuss in detail about Digital Computer
Definition:
A digital computer processes data in binary form and performs operations via digital circuits. It follows instructions and
manipulates data accordingly.
Answer:
1. Input Unit – Devices like keyboard/mouse feed data.
2. Output Unit – Devices like monitor/printer show results.
3. Central Processing Unit (CPU) – Brain of the computer.
4. Arithmetic Logic Unit (ALU) – Performs arithmetic and logical operations.
5. Control Unit – Directs operations of ALU, memory, and I/O.
6. Memory Unit – Stores data (RAM/ROM).
7. Registers – Small fast storage within CPU.
8. Buses – Data Bus, Address Bus, Control Bus.
9. Clock – Controls timing of operations.
10. Binary Operations – Everything is in 0s and 1s.
11. Sequential & Combinational Circuits used internally.
12. Follows fetch-decode-execute cycle.
13. Used in industries, education, entertainment, science.
Q4. List out the steps for 1’s and 2’s complement representation with sign and magnitude method
Definition:
These are methods to represent negative binary numbers. Sign-magnitude uses MSB as sign bit. 1’s and 2’s complement are
alternative binary representations.
Answer:
Sign & Magnitude:
1. MSB = 0 → positive, MSB = 1 → negative
2. Remaining bits = magnitude
3. Example: +5 = 0101, -5 = 1101
1’s Complement:
4. Flip all bits of the number
5. Positive numbers stay unchanged
6. Negative numbers: 1’s comp + sign bit
7. Example: -5 = 1010 (1’s of 0101)
2’s Complement:
8. Take 1’s complement
9. Add 1 to LSB
10. More widely used in computers
11. Example: -5 = 1011 (from 0101)
12. 2’s comp simplifies subtraction
13. Overflow can be detected by carry
UNIT 2 – 10 MARKS
Q1. Explain the basic types of logic gates in detail
Definition:
Logic gates are electronic components that implement Boolean functions. Each gate processes one or more binary inputs to
produce a single output.
Answer:
1. AND Gate – Y = A·B
2. OR Gate – Y = A + B
3. NOT Gate – Y = A̅
4. NAND Gate – Y = (A·B)̅
5. NOR Gate – Y = (A + B)̅
6. XOR Gate – Y = A⊕B
7. XNOR Gate – Y = A⊙B
8. Truth tables and logic symbols used for each
9. Universal Gates – NAND, NOR
10. XOR used in adders and parity checking
11. NOT is a single-input gate
12. Can be combined to make combinational circuits
13. Gates are built using transistors or CMOS logic
Q2. Illustrate the K-map method simplification with example
Definition:
K-map is a graphical method to simplify Boolean expressions by grouping adjacent 1s.
Steps:
1. Draw K-map (2, 3, or 4 variable)
2. Fill 1s based on minterms
3. Group adjacent 1s in powers of 2
4. Use don’t cares (X) if available
5. Write simplified terms per group
6. Eliminate changing variables
7. Combine all terms
8. Final expression is simplified
9. Example: F(A,B,C) = ∑(1,3,5,7)
10. K-map with 1s at mentioned positions
11. Final simplified: F = B
12. Reduces hardware requirements
13. Ensures minimal SOP or POS form
Q3. Explain Mc-Cluskey Tabulation methods in steps
Definition:
McCluskey method is a tabular approach to Boolean minimization, also called Quine–McCluskey method.
Steps:
1. List minterms in binary
2. Group by number of 1s
3. Compare and combine terms differing by one bit
4. Mark combined terms
5. Repeat until no further combinations
6. Uncombined terms = prime implicants
7. Create prime implicant table
8. Identify essential prime implicants
9. Cover remaining minterms
10. Final simplified Boolean expression
11. Suitable for computer implementation
12. Handles larger expressions better than K-map
13. Minimizes logic complexity
Q4. Explain DeMorgan’s theorems with truth table
Definition:
DeMorgan’s theorems allow expressing NAND and NOR logic using only AND, OR, and NOT gates. Two laws exist.
Theorems:
1. (A·B)' = A' + B'
2. (A + B)' = A'·B'
Truth Tables:
A B A·B (A·B)' A' B' A'+B'
000 1 1 1 1
010 1 1 0 1
100 1 0 1 1
111 0 0 0 0
(Similar table for 2nd theorem)
9. Used in logic simplification
10. Converts NOR/NAND to basic gates
11. Helps in implementing universal gate circuits
12. Demonstrates duality of logic
13. Applies in all Boolean algebra operations
Q5. Simplify Boolean expression: Y = BC + B'C + BA using theorem, truth table and logic diagram
Definition:
Boolean expressions can be simplified using laws like absorption, distribution, DeMorgan's, etc.
Given:
Y = BC + B'C + BA
Steps:
1. Use Distribution:
BC + B'C = C(B + B') = C·1 = C
2. Now, Y = C + BA
3. Cannot simplify further
4. Final simplified form: Y = C + BA
Remaining points:
5. Truth table confirms logic
6. Logic diagram uses OR, AND gates
7. Simplified version needs fewer gates
8. Faster computation
9. Reduces hardware cost
10. Applies associative, distributive laws
11. BC + B'C = C
12. Simplified circuit design
13. Efficient logic realization
UNIT 3 – 10 MARKS
Q1. Categorize the types of subtractors and discuss with logic circuit
Definition:
A subtractor is a combinational logic circuit that performs subtraction of binary numbers. There are two types: Half Subtractor
and Full Subtractor.
Answer:
1. Half Subtractor
• Subtracts two binary digits (A − B)
• Inputs: A, B
• Outputs:
o Difference (D) = A ⊕ B
o Borrow (Bo) = A̅ · B
• Truth Table:
A B D Bo
0000
0111
1010
1100
• Logic diagram uses XOR, NOT, AND gates
2. Full Subtractor
• Subtracts three binary digits (A − B − Bin)
• Inputs: A, B, Bin
• Outputs:
o D = A ⊕ B ⊕ Bin
o Bout = A̅ ·B + A̅ ·Bin + B·Bin
• Truth Table includes all 8 combinations
• Logic diagram involves two half subtractors + OR gate
• Used in ALU and multi-bit subtraction
• Can be cascaded for n-bit subtraction
• Handles borrow logic efficiently
• Diagram includes labeled logic blocks
Q2. Summarize adder and its types in detail
Definition:
Adders are digital circuits used to perform binary addition. Two main types are Half Adder and Full Adder.
Answer:
1. Half Adder:
• Adds 2 bits: A and B
• Sum (S) = A ⊕ B
• Carry (C) = A · B
• Truth Table and circuit use XOR and AND gates
• Limitation: No carry input
2. Full Adder:
• Adds 3 bits: A, B, Cin
• Sum = A ⊕ B ⊕ Cin
• Carry = AB + BCin + ACin
• Constructed from 2 half adders and 1 OR gate
• Truth table has 8 entries
• Used in multi-bit binary adders
• Supports ripple-carry design
• Core element in arithmetic units
• Used in CPUs, ALUs
• Logic circuit uses 3 logic levels
• Can be extended to 4-bit, 8-bit using cascading
Q3. Design and explain 8:3 Encoder with combinational logic circuit
Definition:
An 8-to-3 encoder takes 8 input lines and produces 3 output lines representing the binary code of the active input.
Answer:
1. Inputs: I0 to I7
2. Outputs: Y2, Y1, Y0
3. Only one input should be high at a time
4. Output equations:
o Y0 = I1 + I3 + I5 + I7
o Y1 = I2 + I3 + I6 + I7
o Y2 = I4 + I5 + I6 + I7
5. Priority encoders resolve multiple active inputs
6. Used in keyboards, interrupts
7. Truth Table (partial):
Input Output (Y2 Y1 Y0)
I0 000
I1 001
I2 010
Input Output (Y2 Y1 Y0)
I3 011
I4 100
I5 101
I6 110
I7 111
8. Logic diagram with OR gates
9. Requires 7 OR gates minimum
10. Compact representation of many inputs
11. Reduces wire complexity
12. Used in digital control systems
13. Optimized using enable inputs
Q4. Construct and explain 3:8 Decoder with combinational logic circuit
Definition:
A 3-to-8 decoder takes 3 input lines and generates 8 unique output lines. Only one output is high for any combination.
Answer:
1. Inputs: A, B, C
2. Outputs: Y0 to Y7
3. Each output represents one minterm
4. Output = 1 for unique input combination
5. Logic equations:
o Y0 = A̅ ·B̅ ·C̅
o Y1 = A̅ ·B̅ ·C
o Y2 = A̅ ·B·C̅ … up to Y7
6. Truth Table:
A B C Output
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
A B C Output
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
7. Logic diagram uses AND gates and NOT gates
8. Used in memory address decoding
9. Also for instruction selection
10. Can be implemented using universal gates
11. Enable input optional
12. Converts binary code into one-hot code
13. Core in microprocessor control logic
UNIT 4 – 10 MARKS
Q1. Elaborate the working principle of S-R flip-flop with logic circuit and truth table
Definition:
An S-R (Set-Reset) flip-flop is a bistable device with two stable states. It stores one bit and is the basic flip-flop type.
Answer:
1. Inputs: S (Set), R (Reset)
2. Outputs: Q, Q̅
3. Truth Table:
S R Q(next) Q̅
0 0 No change —
010 1
101 0
1 1 Invalid —
4. If S = R = 1 → invalid condition
5. Built using 2 NOR or 2 NAND gates
6. NOR-based SR Flip-Flop:
o S and R connected to NOR gates
o Cross-coupled configuration
7. Used in latches, memory design
8. Stores binary state
9. Clockless (level triggered)
10. Can be converted to other flip-flops
11. Diagram includes cross-linked NOR/NAND gates
12. Application: control logic, synchronizers
13. Q toggles only based on inputs
Q2. Construct half and full adder with truth table and logic circuit
(Already covered in Unit 3 Q2 – reuse if needed)
Q3. Illustrate the working and timing diagram of Master-Slave flip-flop
Definition:
A master-slave flip-flop consists of two flip-flops (master and slave) connected in series, triggered by opposite clock phases.
Answer:
1. Solves race-around problem in JK FF
2. Master triggered on clock high
3. Slave triggered on clock low
4. Inputs locked when clock = 1
5. Outputs transferred when clock = 0
6. Uses 2 JK flip-flops
7. Edge-triggered behavior
8. Timing diagram shows clock, inputs, Q
9. Output changes only on falling edge
10. Eliminates multiple toggling
11. Circuit uses clock inverter
12. Ensures stable output
13. Used in sequential design and counters
Q4. Determine working principle, diagram, and truth table of T & D Flip-Flops
Definition:
T (Toggle) and D (Data) flip-flops are types of clocked flip-flops used in sequential circuits.
T Flip-Flop:
1. Input: T, Clock
2. If T = 1 → Toggle
3. If T = 0 → No change
4. Truth Table:
T Q(next)
0Q
1 Q̅
5. Used in counters
6. Built using JK flip-flop
7. Edge-triggered
D Flip-Flop:
1. Input: D, Clock
2. Output Q = D after clock
3. Stores data on clock edge
4. Truth Table:
D Q(next)
00
11
5. Eliminates uncertain states
6. Used in registers and shift registers
7. Diagram includes single input and clock
8. Easy to implement
9. Timing diagram shows D synced to clock
10. Core in memory design
11. Edge-triggered or level-triggered
12. Flip-flops help sequence operations
13. Reusable in FSMs and pipelines
Q5. Determine working principle, diagram, and truth table of J-K Flip-Flop
Definition:
JK Flip-Flop is a universal flip-flop that eliminates the invalid state of SR flip-flop by toggling when both inputs are 1.
Answer:
1. Inputs: J, K, Clock
2. Outputs: Q, Q̅
3. Truth Table:
J K Q(next)
00Q
010
101
1 1 Q̅
4. Toggle feature when J = K = 1
5. Uses AND, OR, and NOT gates internally
6. Clock-controlled output
7. No invalid state
8. Used in counters, memory
9. More versatile than SR FF
10. Diagram uses cross-coupled AND-NOR gates
11. Can create T flip-flop from JK
12. Edge-triggered
13. Central in sequential circuits
UNIT 5 – 10 MARKS
Q1. Discuss different types of basic memory in detail
Definition:
Memory units store data and instructions. Basic types include RAM, ROM, PROM, EPROM, EEPROM, and cache.
Answer:
1. RAM – Temporary, volatile memory
2. ROM – Permanent, non-volatile memory
3. PROM – Programmed once by user
4. EPROM – Erased using UV light
5. EEPROM – Electrically erased and reprogrammed
6. Cache Memory – High-speed temporary memory
7. Flash Memory – Non-volatile, rewriteable
8. SRAM – Static RAM, faster and costly
9. DRAM – Dynamic RAM, slower and cheaper
10. Register Memory – Inside CPU, fastest
11. Secondary Storage – HDD, SSD
12. Virtual Memory – Disk as extended RAM
13. Each type serves specific purpose in system design
Q2. Construct 4-bit asynchronous counter and explain its working principle
Definition:
An asynchronous counter counts binary values using flip-flops where each flip-flop is triggered by the previous one’s output.
Answer:
1. 4 T flip-flops connected in series
2. First FF triggered by clock
3. Each next FF triggered by previous Q output
4. 2⁴ = 16 states (0000 to 1111)
5. Asynchronous = Ripple counter
6. Propagation delay between FFs
7. Used for counting pulses
8. Truth table for 4-bit binary count
9. Circuit diagram includes 4 FFs
10. Count resets after 1111
11. Simple implementation
12. Limited by speed
13. Output = binary count sequence
Q3. Elaborate in detail Up/down synchronous counters
Definition:
Up/down counters can count in both ascending and descending order. Synchronous means all FFs are triggered by a common
clock.
Answer:
1. Uses JK or T flip-flops
2. Control input determines direction
3. UP: 000 → 001 → … → 111
4. DOWN: 111 → 110 → … → 000
5. Clock signal is common to all FFs
6. No ripple delay
7. Logic gates control FF toggle conditions
8. Can be reset or preset
9. Useful in digital clocks, elevators
10. Can be designed as 3-bit or 4-bit
11. Count controlled using logic expressions
12. Compact and efficient
13. Accurate for high-frequency operations
