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OCR Computer Science 1.1 Notes Updated

The document explains the Central Processing Unit (CPU), its main components including the Control Unit, Arithmetic Logic Unit, and various registers, and outlines the Fetch-Decode-Execute cycle that the CPU uses to process instructions. It also discusses the Von Neumann architecture, which combines data and instructions in one memory, and factors affecting CPU performance such as clock speed, number of cores, and cache size. Additionally, it describes embedded systems as specialized computers designed for specific tasks, contrasting them with general-purpose PCs.

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35 views2 pages

OCR Computer Science 1.1 Notes Updated

The document explains the Central Processing Unit (CPU), its main components including the Control Unit, Arithmetic Logic Unit, and various registers, and outlines the Fetch-Decode-Execute cycle that the CPU uses to process instructions. It also discusses the Von Neumann architecture, which combines data and instructions in one memory, and factors affecting CPU performance such as clock speed, number of cores, and cache size. Additionally, it describes embedded systems as specialized computers designed for specific tasks, contrasting them with general-purpose PCs.

Uploaded by

sanchitjoshi2507
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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OCR GCSE Computer Science - 1.

1: Systems Architecture

What is the CPU?


- CPU = Central Processing Unit (the brain of the computer)
- It processes data and runs instructions
- Uses the Fetch-Decode-Execute Cycle to do its job

Main Components of the CPU


1. Control Unit (CU):
- Directs the CPU's operations
- Decodes instructions and controls data flow
2. Arithmetic Logic Unit (ALU):
- Handles calculations and logic operations
3. Registers:
- Small, fast memory used during processing
- Program Counter (PC): Holds address of next instruction
- Accumulator (ACC): Holds results of operations
- Memory Address Register (MAR): Holds memory address
- Memory Data Register (MDR): Holds fetched data
- Current Instruction Register (CIR): Holds current instruction

Fetch-Decode-Execute Cycle
The Fetch-Decode-Execute (FDE) cycle is the core process that the CPU uses to run instructions.
First, during the Fetch stage, the CPU retrieves an instruction from memory. The Program Counter
(PC) holds the address of the instruction, which is sent to the Memory Address Register (MAR). The
data at that address is then fetched into the Memory Data Register (MDR) and copied into the
Current Instruction Register (CIR). Next comes the Decode stage, where the Control Unit (CU)
interprets the instruction and decides what actions are needed. Finally, during the Execute stage,
the instruction is carried out. This could involve calculations by the Arithmetic Logic Unit (ALU),
moving data between registers, or interacting with memory. Once the instruction is executed, the
cycle repeats with the next instruction, allowing the CPU to carry out complex tasks step by step.

Von Neumann Architecture


- One memory holds both data and instructions
- Instructions are processed using the FDE cycle
- Standard design in most computers

Factors Affecting CPU Performance


- Clock Speed: Higher = faster processing (GHz)
- Number of Cores: More cores = multitasking
- Cache Size: More cache = faster access to frequently used data

Embedded Systems
- Computers built into devices for specific tasks
- Examples: Microwaves, washing machines
- Efficient, cheap, and task-specific
- Not general-purpose like a PC

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