PIO 8255 [PROGRAMMABLE INPUT-OUTPUT PORT]

 The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.
 The Intel's 8255 is designed for use with Intel's 8-bit, 16-bit and higher capability
microprocessors.
 It has 24 input/output lines which may be individually programmed in two groups of
twelve lines each, or three groups of eight lines.
 The two groups of I/O pins are named as Group A and Group B. Each of these two
groups contain a subgroup of eight I/O lines called as 8-bit port and another subgroup of
four I/O lines or a 4-bit port.
 Thus Group A contains an 8-bit port A along with a 4-bit port, C upper. The port A lines are
identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7.
 Group B contains an 8-bit port B, containing lines PB0 -PB7 and a 4-bit port C with lower bits
PC0-PC3.
 The port C upper and port C lower can be used in combination as an 8-bit port C. Both the port
Cs are assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and
two 4-bit I/O ports.
 All of these ports can function independently either as input or as output ports. This can
be achieved by programming the bits of an internal register of 8255 called as Control Word
Register (CWR).
 The 8-bit data bus buffer is controlled by the read/write control logic.
 The read/write control logic manages all of the internal and external transfers of both data
and control words.
 RD, WR, A 1, A0 and RESET are the inputs, provided by the microprocessor to the
READ/WRITE control logic of 8255.
 The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the
external system data bus.
 This buffer receives or transmits data upon the execution of input or output instructions by
the microprocessor. The control words or status information is also transferred through the
buffer.
PIN DESCRIPTION:

PA7-PA0: These are eight port A lines that act as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
PC0-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers lines.
This port also can be used for generation of handshake lines in mode 1or mode 2.
PC3-PC0 These are the lower port C lines, other details are the same as PC7-PC4 lines.
PB0-PB7 These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
RD This is the input line driven by the microprocessor and should be low to indicate
read operation to 8255.
WR This is an input line driven by the microprocessor. A low on this line indicates write
operation.
CS This is a chip select line. If this line goes low, it enables the 8255 to respond to RD
and WR signals, otherwise RD and WR signals are neglected.

A1-A0 These are the address input lines and are driven by the microprocessor. These lines (A 1 -
A0) with RD , WR and CS form the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e. three ports
and a control word register In case of 8086 systems, if the 8255 is to be interfaced with
lower order data bus, the A0 and A 1 pins of 8255 are connected with A 1and A2
respectively.

Port and register select signals

D0-D7 These are the data bus lines those carry data or control word to/from the micro-
proce ssor.
RESET A logic high on this line clears the control word register of 8255. All ports are set
as input ports by default after reset.
 MODES OF OPERATION OF 8255

 There are two basic modes of operation of 8255- I/Omode and Bit Set-Reset mode
(BSR).
 In the I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode
only port C (PC0-PC 7) can be used to set or reset its individual port bits.
 Under the I/O mode of operation, further there are three modes of operation of 8255, so
as to support different types of applications, viz. mode 0, mode 1 and mode 2.

BSR Mode
In this mode, any of the 8-bits of port C can be set or reset depending on B0 of the control word.
The bit to be set or reset is selected by bit select flags B3, B2 and B1of the CWR.

B3 B2 B1 Selected Bits of port C

0 0 0 Bo
0 0 1 B1
0 1 0 B2
0 1 1 B3
1 0 0 B4
1 0 1 B5
1 1 0 B6
1 1 1 B7

I/O MODES

MODE 0 (Basic I/O mode): This mode is also known as basic input/output mode. This
mode provides simple input and output capability using each of the three ports. Data can be
simply read from and written to the input and output ports respectively, after appropriate
initialisation.

The salient features of this mode are

 Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
 Any port can be used as an input or output port.
 Output ports are latched. Input ports are not latched.
 A maximum of four ports are available so that overall 16 I/O configurations are possible.
 All these modes can be selected by programming a register internal to 8255, known as
Control Word Register (CWR) which has two formats. The first format is valid for I/O
modes of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit
set/reset (BSR) mode of operation.
MODE I (Strobed I/O mode)
 This mode is also called as strobed input/output mode. In this mode the handshaking signals
control the input or output action of the specified port.
 Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes
port B and PC0-PC2 is called as group B for strobed data input/output.
 Port C lines PC3-PC5 provide strobe lines for port A. This group including port A and PC3-PC5
forms group A.
 Thus port C is utilized for generating handshake signals.

Features of Mode1

 Two groups-group A and group B are available for strobed data transfer.
 Each group contains one 8-bit data I/O port and one 4-bit control/data port.
 The 8-bit data port can be either used as input or an output port. Both the inputs and outputs are
latched.
 Out of 8-bit port C, P C0-PC2 are used to generate control signals for port B and PC3-PC5 are
used to generate control signals for port A. The lines PC6,PC7 may be used as independent data
lines.
The control signals for both the groups in input and output modes are

Input control signal definitions (mode 1)

STB (Strobe input) -If this line falls to logic low level, the data available at 8-bit input port is loaded into
input latches.
IBF (input buffer full) -If this signal rises to logic 1, it indicates that data has been loaded into the
latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising edge of
RD input.

INTR (Interrupt request):

 This active high output signal can be used to interrupt the CPU whenever an input device
requests the service. INTR is set by a high at STB pin and a high at IBF pin.
 INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4
(INTEA) or PC2 (INTE8) INTR is reset by a falling edge on RD input.
 Thus an external input device can request the service of the processor by putting the data on
the bus and sending the strobe signal.
Output control signal definitions (mode 1)

OBF (Output buffer full): This status signal, whenever falls to logic low, indicates that the CPU has
writ- ten data to the specified output port. The OBF flip-flop will be set by a rising edge of WR signal
and reset by a low going edge at the ACK input.
ACK (Acknowledge input): ACK signal acts as an acknowledgement to be given by an output device.
ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device
through the port is received by the output device.
INTR (Interrupt request): Thus an output signal that can be used to interrupt the CPU when an output
device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 'l '.It
is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset
mode of PC6 and PC2, respectively.
MODE 2 (Strobed bidirectional I/O)
 This mode of operation of 8255 is also known as strobed bidirectional I/O.
 This mode of operation provides 8255 with an additional feature for communicating with a
peripheral device on an 8-bit data bus.
 Handshaking signals are provided to maintain proper data flow and synchronization between
the data transmitter and receiver.
 The interrupt generation and other functions are similar to mode 1.
 Thus in this mode, 8255 is a bidirectional 8-bit port with handshake signals.
 The RD and WR signals decide whether the 8255 is going to operate as an input port or
output port.

The salient features of mode 2 of 8255 are

 The single 8-bit port in group A is available.
 The 8-bit port is bidirectional and additionally a 5-bit control port is available.
 Three I/O lines are available at port C, PC2-PC0.
 Inputs and outputs are both latched.
 The 5-bit control port C (PC3-PC7) is used for generating/accepting handshake signals for
the 8-bit data transfer on port A.

INTR (Interrupt request)

As in mode 1, this control signal is active high and is used to interrupt the microprocessor to
ask for transfer of the next data byte to/from it. This signal is used for input (read) as well as output
(write) operations.
OBF (Output buffer full) This signal, when falls to logic low level, indicates that the CPU has
written data to port A.
ACK (Acknowledge) This control input, when falls to logic low level, acknowledges that the
previous data byte is received by the destination and the next byte may be sent by the processor.
This signal enables the internal tristate buffers to send out the next data byte on port A.
INTEi (associated with OBF ) This can be controlled by bit set/reset mode with PC6.
Control signals for input operations
STB (Strobe input): A low on this line is used to strobe in the data into the input latches of 8255.

IBF (Input buffer full): When the data is loaded into the input buffer, this signal rises to logic '1'.
This can be used as an acknowledgement that the data has been received by the receiver.

INTERFACING ANALOG TO DIGITAL DATA CONVERTERS

 The PIO 8255 is used for interfacing the analog to digital converters with a microprocessor.
 The analog to digital converter is treated as an input device by the microprocessor, which sends
an initializing signal to the ADC to start the analog to digital data conversion process.
 The start of conversion signal is a pulse of a specific duration .The process of analog to
digital conversion is a slow process, and the microprocessor has to wait for the digital data till
the conversion is over.
 After the conversion is over, the ADC sends end of conversion (EOC) signal to inform the
microprocessor about it and the result is ready at the output buffer of the ADC.
 These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and
reading the digital output of the ADC are carried out by the CPU using 8255 I/O ports.
 The time taken by the converter to calculate the equivalent digital data output from the
moment of the start of conversion is called conversion delay.
 Successive approximation and dual slope integration techniques are the most popular
techniques used in the integrated ADC chips.
.

A general algorithm for ADC interfacing contains the following steps.

 Ensure the stability of analog input, applied to the ADC
 Issue start of conversion (SOC) pulse to ADC
 Read end of conversion (EOC) signal to mark the end of conversion process
 Read digital data output of the ADC as equivalent digital output.
 It may be noted that the analog input voltage must be a constant at the input of the ADC
right from the beginning to the end of the conversion to get correct results.
 This may be ensured by a sample and hold circuit which samples the analog signal and holds it
constant for a specified time duration.
 The microprocessor may issue a hold signal to the sample and hold circuit.
 If applied input changes before the complete conversion process is over, the digital equivalent
of the analog input calculated by the ADC may not be correct.

5.6.1 ADC 0808/0809

 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive
approximation converters.
 Successive approximation technique is one of the fastest technique used for the process of
analog to digital conversion.
 The conversion delay is 100 µs at a clock frequency of 640 kHz, which is quite low as
compared to other converters.
 These converters internally have a 3:8 analog multiplexer so that at a time eight different
analog inputs can be connected to the chips.
 Out of these eight inputs only one can be selected for conversion by using address lines
ADD A, ADD B and ADD C, as shown.
 The CPU may drive these lines using output port lines in case of multichannel applications.
In case of single input applications, these may be hardwired to select the proper input.

Analog /IP selected Address lines

C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1
Interface ADC 0808 with 8086 using 8255 ports. Use Port A of 8255 for transferring digital data
output of ADC to the CPU and Port C for control signals. Assume that an analog input is present at
I/P 2 of the ADC and a clock input of suitable frequency is available for ADC. Draw the schematic and
write required ALP.

 The analog input l/P2 is used and therefore address pins A, B & C should be 0 1 0 respectively to
select I/P2.
 The OE and ALE pins are already kept at +5V to select the ADC and enable the outputs.
 Port C upper acts as the input port to receive the EOC signal while port C lower acts as the output
port to send SOC to the ADC.
 Port A acts as an 8-bit input data port to receive the digital data output from the ADC.
 The 8255 control word is written as follows:

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0

MOV AL, 98H

OUT CWR, AL
MOV AL, 02H
OUT PORTB, AL
MOV AL, 00H
OUT PORTC, A L
MOV AL, 01 H
OUT PORTC, AL
MOV AL, 00H
OUT PORTC, A L
IN AL, PORTC
RCL
JNC WAIT
IN AL, PORTA
HLT
 INTERFACING DIGITAL TO ANALOG CONVERTERS
The digital to analog converters convert binary numbers into their analog equivalent voltages. The DAC find
applications in areas like digitally controlled gains, motor speed controls, programmable gain amplifiers.

DAC 0800 8-bit Digital to Analog Converter

The DAC 0800 is a monolithic 8-bit DAC manufactured by National Semiconductor. It has settling time
around 100 ms and can operate on a range of power supply voltages, i.e. from 4.5 V to + 18 V. usually
the supply V+ is 5 V or +12 V. The V-pin can be kept at a minimum of -12 V.

As it is an 8-bit DAC thus it contains 8 digital input lines. Other than the input lines we have two
dedicated pins that provide current output and complement of current output which is given the name
IOUT and I’OUT. There are a positive and a negative supply voltage pin along with a pin dedicated for
compensation voltage. Here VLC represents the threshold control pin and there are two pins for positive
and negative values of reference voltage denoted by VREF (+) and VREF (-).

Write an assembly language program to generate a triangular wave of frequency 500 Hz using the
interfacing circuit. The 8086 system operates at 8 MHz.The amplitude of the triangular wave should be
+5 V.

 The Vref+ should be tied to + 5 V to generate a wave of +5V amplitude.

 The required frequency of the output is 500 Hz, i.e. the period is 2 ms.
 Assuming the wave to be generated is symmetric, the waveform will rise for 1 ms and fall for 1
ms. this will be repeated continuously.

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0

Only port A is enabled as output port for DAC interfacing, so the CWR value is 80H
 MOV AL, 80 H ; Move 80Hvalue to AL
OUT CWR, AL ; Writes/out the data in AL to CWR
MOV AL, 00H ; Initialize AL with 00
OUT PORT A, AL ; write / out the value in AL to PORTA
BACK: INC AL ; Increment AL value
CMP AL, FFH ; compare the AL value with FF to check whether the count has been
reached, if it is below the value jump to the label “BACK”
JB BACK;
OUT PORTA, AL ; Write/ Out the value in AL (AL=FF) to PORTA
BACK1: DEC AL ; Decrement AL
CMP AL, 00 ; Compare AL with 00 to check whether the count has been reached,
if it is above jump to the label “BACK1”
JA BACK1
JMP BACK
STEPPER MOTOR INTERFACING
A stepper motor is a device used to obtain an accurate posi- tion control of rotating shafts. It employs
rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors. To rotate
the shaft of the stepper motor, a sequence of pulses is needed to
be applied to the windings of the stepper motor, in a proper
sequence. The number of pulses required for one complete
rotation of the shaft of the stepper motor are equal to its
number of internal teeth on its rotor. The stator teeth and the
rotor teeth lock with each other to fix a position of the shaft. With
a pulse applied to the wind- ing input, the rotor rotates by one
teeth position or an angle x. The angle x may be calculated as:
x = 360°/no.of rotor teeth
After the rotation of the shaft through angle x, the rotor
locks itself with the next tooth in the sequence on the
internal surface of stator. The internal schematic of a
typical stepper motor with four windings is shown in Fig.
5.49(a). The stepper motors have been designed to work
with digital circuits. Binary level pulses of 0-5V are
required at its winding inputs to obtain the rotation of shafts. The sequence of the pulses can be
decided, depending upon the required motion of the shaft. Figure shows a typical winding
arrangement of the stepper motor. s
N

N
Fig. Winding Arrangement of a Stepper Motor Fig A Stepper Motor Rotor
The circuit for interfacing a winding Wn with an I/O port is given in below Figure. Each of the windings
of a stepper motor need this circuit for its interfacing with the output port. A typical stepper motor may
have parameters like torque 3 kg-cm, operating voltage 12 V, current rating 0.2 A and a step angle 1.8°,
i.e. 200 steps/revolution (number of rotor teeth).

+
Vee

From
O/P port

Fig. Interfacing Stepper Motor Winding Wa

 A simple scheme for rotating the shaft of a stepper motor is called a wave scheme. In this
scheme, the windings Wa, Wb, Wc and Wd are applied with the required voltage pulses, in a
cyclic fashion.
 By reversing the sequence of excitation, the direction of rotation of the stepper motor shaft may
be reversed. Table below shows the excitation sequences for clockwise and anticlockwise
rotations.
 Another popular scheme for rotation of a stepper motor shaft applies pulses to two successive
windings at a time but these are shifted only by one position at a time.

Table Excitation Sequences of a Stepper Motor Using Wave Switching Scheme

MOTION STEP A B C D
1 1 0 0 0
2 0 1 0 0
Clockwise 3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
(Contd.)

MOTION STEP A B C D

1 1 0 0 0

2 0 0 0 1
Anticlockwise
3 0 0 1 0
4 0 1 0 0
5 1 0 0 0
Problem
Design a stepper motor controller and write an ALP to rotate shaft of a 4-phase stepper motor:
 in clockwise 5 rotations
 in anticlockwise 5 rotations
An Alternative Scheme for Rotating Stepper Motor Shaft

B C D
Motion Step A
Clockwise 1 0 0 1 1
2 0 1 1 0
3 1 1 0 0
4 1 0 0 1
5 0 0 1 1
Anticlockwise 1 0 0 1 1
2 1 0 0 1
3 1 1 0 0
4 0 1 1 0
5 0 0 0 0

The 8255 port A address is 0740H. The stepper motor has 200 rotor teeth. The port A bit PA0 drives
winding Wa, PA1 drives Wb and so on. The stepper motor has an inertial delay of 10 m sec. Assume
that the routine for this delay is already available.
The stepper motor connections for all the four windings. The ALP for rotating the shaft of the stepper
motor is

MOV AL, 80H

OUT CWR, A L
MOV AL, 88H
MOV CX, 1000
AGAIN1: OUT PORT A.AL
CALL DELAY
ROL AL, 01
DEC CX
JNZ AGAIN!
MOV AH, 88H
MOV CX, 1000
AGAIN2: OUT PORTA, AL
CALL DELAY
ROR AL, 01
DEC CX
JNZ AGAIN2
MOV AH, 4CH
INT 03H
 z

FWD

GND

PA2 PA1
PA3 Port of 8086 system PAo

Stepper Motor Windings Connections

PROGRAMMABLE INTERRUPT CONTROLLER 8259A

 Consider an application, where a number of I/O devices connected with a CPU desire to
transfer data using interrupt driven data transfer mode. In these types of applications, more
number of interrupt pins are required than available in a typical microprocessor.
 Moreover, in these multiple interrupt systems, the processor will have to take care of the
priorities for the interrupts, simultaneously occurring at the interrupt request pins.
 To overcome all these difficulties, we require a programmable interrupt controller which is
able to handle a number of interrupts at a time. This controller takes care of a number of
simultaneously appearing interrupt requests along with their types and priorities.
 This relieves the processor from all these tasks. The programmable interrupt controller
8259A from Intel is one such device. Its predecessor 8259 was designed to operate only with
8-bit processors like 8085.

ARCHITECTURE AND SIGNAL DESCRIPTIONS OF 8259A

Interrupt Request Register (IRR): The interrupts at IRQ input lines are handled by Interrupt Request
Register internally. IRR stores all the interrupt requests in it in order to serve them one by one on the
priority basis.

In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR keeps
a track of the requests being served.

Priority Resolver: This unit determines the priorities of the interrupt requests appearing
simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during
INTA pulse. The IRo has the highest priority while the IR7 has the lowest one, normally in fixed
priority mode. The priorities however may be altered by programming the 8259A in rotating priority
mode.
 Interrupt Mask Register (IMR): This register stores the bits required to mask the interrupt inputs.
IMR operates on IRR at the direction of the Priority Resolver.

Interrupt Control Logic: This block manages the interrupt and the interrupt acknowledge signals to
be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt
acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the
data bus.

Data Bus Buffer This tristate bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus. Control words, status and vector information pass through
data buffer during read or write operations.

Read/Write Control Logic This circuit accepts and decodes commands from the CPU. This
block also allows the status of the 8259A to be transferred on to the data bus.

Cascade Buffer/Comparator This block stores and compares the IDs of all the 8259As used
in the system. The three 1/0 pins CAS0-2 are outputs when the 8259A is used as a master.
The same pins act as inputs when the 8259A is in the slave mode. The 8259A in the master
mode, sends the ID of the interrupting slave device on these lines. The slave thus selected, will
send its pre-programmed vector address on the data bus during the next INTA pulse.

PIN DIAGRAM OF 8259A

CS This is an active-low chip select signal for enabling RD and

WR operations of 8259A. INTA function is independent of CS.

WR This pin is an active-low write enable input to 8259A. This

enables it to accept command words from CPU.

RD This is an active-low read enable input to 8259A. A low on this

line enables 8259A to release status onto the data bus of CPU.

D0-D7 These pins form a bidirectional data bus that carries 8-bit data either
to control word or from status word registers. This also carries interrupt
vector information.

CAS0-CAS1- Cascade Lines: A single 8259A provides eight vectored

interrupts. If more interrupts are required, the 8259A is used in the
cascade mode in which a master 8259A along with eight slaves 8259A can
provide upto 64 vectored interrupt lines. These three lines act as select lines for addressing the slaves

PS / EN: This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as a
buffer enables receivers. If this is not able to control buffer transmitter used in buffered mode then the
pin is used as input to designate whether the chip is used as a master (SP = 1) or a slave EN=0
IRo-IR7 (Interrupt requests): These pins act as inputs to accept interrupt requests to the CPU. In the
edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high state. It is
held high until it is acknowledged, and just by latching it to high level, if used in the level triggered
mode.

INTA (Interrupt acknowledge): This pin is an input used to strobe-in 8259A interrupt vector data on to
the data bus.
INT: This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU
and is connected to the interrupt input of CPU.

 The device 8259A can be interfaced with any CPU using either polling or interrupt. In polling, the
CPU keeps on checking each peripheral device in sequence to ascertain if it requires any service
from the CPU. If any such service request is noticed, the CPU serves the request and then goes on
to the next device in sequence. After all the peripheral devices are scanned as above the CPU
again starts from the first device. This type of system operation results in the reduction of
processing speed because most of the CPU time is consumed in polling the peripheral devices.

 In the interrupt driven method, the CPU performs the main processing task till it is interrupted by
a service requesting peripheral device. The net processing speed of these type of systems is high
because the CPU serves the peripheral only if it receives the interrupt request. Ifmore than one
interrupt requests are received at a time, all the requesting peripherals are served one by one on
priority basis. This method of interfacing may require additional hardware if number of
peripherals to be interfaced is more than the interrupt pins available with the CPU.
Interrupt Sequence in an 8086 System

The interrupt sequence in an 8086-8259A system

is described as follows:
 One or more IR lines are raised high that set
corresponding IRR bits.
 8259A resolves priority and sends an INT
signal to CPU.
 The CPU acknowledges with INTA pulse.
 Upon receiving an INTA signal from the
CPU, the highest priority ISR bit is set and
the corresponding IRR bit is reset. The 8259A
does not drive data bus during this period.
 The 8086 will initiate a second INTA pulse.
During this period 8259A releases an 8-bit
pointer on to data bus from where it is read by
the CPU.
 This completes the interrupt cycle. The ISR bit
is reset at the end of the second INTA pulse if
automatic end of interrupt (AEOI) mode is
programmed. Otherwise
 ISR bit remains set until an appropriate EOI
command is issued at the end of interrupt
subroutine.
 Command Words of 8259A
The command words of 8259A are classified in two groups, viz. Initialization Command Words
(ICWs) and Operation Command Words (OCWs).

Initialization Command Words (ICWs) Before it starts functioning, the 8259A must be
initialized by writing two to four command words into the respective command word registers.
These are called as Initialization Command Words (ICWs).
 If A 0 = 0 and D4 = 1, the control word is recognized as ICW 1.It contains the control bits
for edge/level triggered mode, single/cascade mode, call address interval and whether
ICW4 is required or not, etc.
 If A0 = 1, the control word is recognized as ICW2. The ICW2 stores details regarding
interrupt vector addresses. The initialization sequence of 8259A is described in from of a
flow chart above.
 Once ICW 1 is loaded, the following initialization procedure is carried out internally.The edge
sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive, IMR is cleared, IR7
input is assigned the lowest priority, Slave mode address is set to 7, Special mask mode is
cleared and the status read is set to IRR
 If IC4 = 0, all the functions of ICW4 are set to zero. Master/slave bit in ICW4 is used in the
buffered mode only.
 In 8086/88 based system, five most significant bits of the interrupt type byte are inserted in
place of T7 -T3 respectively and the remaining three bits (Ag, A 9 and A 10) are inserted
internally as 000

INITIALIZATION COMMAND WORD 1 (ICW1)

T7-T3 –
 For 8085 system they are filled by A15-A11 of the interrupt vector address and the least
significant 3 bits are same as the respective bits of vector address.
 For 8086 system they are filled by most significant 5 bits of interrupt type and the least
significant 3 bits are 0,pointing to IR0. Other seven interrupt levels' vector addresses are
internally generated automatically by 8259 using IR0 vector. Address interval is always four in an
8086 based system.

INITIALIZATION COMMAND WORD 2 (ICW2)

ICW 1 and ICW2 are compulsory command words in initialization sequence of 8259A as is evident from
the above registers. While ICW3 and ICW4 are optional.

INITIALIZATION COMMAND WORD 3 (ICW3)

The ICW3 is read only when there are more than one 8259A’s in the system, i.e. cascading is used
(SNGL = 0). The SNGL bit in ICW 1 indicates whether the 8259A is in the cascade mode or not. The
ICW3 loads an 8-bit slave register. Its detailed functions are as follows:
 In the master mode (i.e. SP = 1 or in buffer mode MIS = I in ICW4), the 8-bit slave register will
be set bit-wise to '1' for each slave in the system, as shown in Fig. 6.16. The requesting slave will
then release the second byte of a CALL sequence.
 In slave mode (i.e. SP = 0 or if BUF = 1 and M/S = 0 in ICW4) bits D2 to D0 identify the slave,
i.e. 000 to 111 for slave I to slave8. The slave compares the cascade inputs with these bits and if
they are equal, the second byte of the CALL sequence is released by it on the data bus.
ICW4: The use of this command word depends on the IC4 bit of ICW 1. IfIC4 = 1, ICW4 is used,
otherwise it is neglected. The bit functions of ICW4 are described as follows:
SFNM Special fully nested mode is selected, if SFNM = 1.
BUF If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as enable output and
the master/slave is determined using the MIS bit of ICW4.
M/S If M/S= 1, 8259A is a master. If M/S = 0, 8259A is a slave. If BUF =0, M/S is to be neglected.
AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.
mPM: If the mPM bit is 0, the Mcs-85 system operation is selected and if mPM =l, 8086/88
operation is selected.

INITIALIZATION COMMAND WORD 4 (ICW4)

Operation Command Words
 Once 8259A is initialized using the previously discussed command words for initialization,
it is ready for its normal function, i.e. for accepting the interrupts but 8259A has its own
ways of handling the received interrupts called as modes of operation.
 These modes can be selected by programming, i.e. writing three internal registers called as
operation command word registers. The data written into them (hit pattern) is called as operation
command words. In the three operation command words OCW 1,OCW2 and OCW 3,every bit
corresponds to some operational feature of the mode selected, except for a few bits those are
either '1' or '0'.

OCW1 is used to mask the unwanted interrupt requests. If the mask bit is '1', the corresponding interrupt
request is masked, and if it is '0', the request is enabled.

In OCW2 the three bits, viz. R, SL and EOI control the end of interrupt, the rotate mode and their
combinations as shown in Fig. 6.18 (b). The three bits L2, L1 and L0 in OCW 2 determine the interrupt
level to be selected for operation , if the SL bit is active, i.e. 'l'.
In OCW3,
 If the ESMM bit, i.e. Enable Special Mask Mode bit is set to '1', the SMM bit is enabled to select
or mask the Special Mask Mode.
 When ESMM bit is 'O', the SMM bit is neglected.
 If the SMM bit, i.e. Special Mask Mode bit is '1 ', the 8259A will enter special mask mode
provided ESMM = 1.
 If ESMM = 1and SMM =0, the 8259A will return to the normal mask mode.
OPERATING MODES OF 8259

The different modes of operation of 8259A can be programmed by setting or resting the appropriate bits
of the ICWs or OCWs as discussed previously. The different modes of operation of 8259A are explained
in the following text:

Fully Nested Mode:

 This is the default mode of operation of 8259A. IR0 has the highest priority and IR7 has the
lowest one. When interrupt requests are noticed, the highest priority request amongst them is
determined and the vector is placed on the data bus. The corresponding bit of ISR is set and
remains set till the microprocessor issues an EOI command just before returning from the service
routine or the AEOI bit is set.
 If the ISR (In Service) bit is set, all the same or lower priority interrupts are inhibited but higher
levels will generate an interrupt, which will be acknowledged only if the microprocessor's
Interrupt enable Flag (IF) is set. The priorities can afterwards be changed by programming the
rotating priority modes.

End of Interrupt (EOI):

 The ISR bit can be reset either with AEOI bit of ICW 1 or by EOI command, issued before
returning from the interrupt service routine. There are two types of EOI commands specific and
non-specific.
 When 8259A is operated in the modes that preserve fully nested structure, it can determine which
ISR bit is to be reset on EOI. When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR hit out of those already set.
 When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to
determine the last level acknowledged. In this case a specific EOI command is issued to reset a
particular ISR bit.
 An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific
EOI of 8259A, if it is in special mask mode.

Automatic Rotation
 This is used in the applications where all the interrupting devices are of equal priority. In this
mode, an Interrupt Request (IR) level receives lowest priority after it is served while the next
device to be served gets the highest priority in sequence. Once all the devices are served like this,
the first device again receives highest priority.

Automatic EOI Mode

 Till AEOI = I in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A performs a
non-specific EOI operation at the trailing edge of the last INTA pulse automatically. This mode
should be used only when a nested multilevel interrupt structure is not required with a single
8259A.
 Specific Rotation:
 In this mode a bottom priority level can be selected, using L2, L1 and L0 in OCW2 and R = l, SL
= 1, EOI = 0. The selected bottom priority fixes other priorities. If IR5 is selected as a bottom
priority, then IR5 will have least priority and IR4 will have a next higher priority.
 Thus IR6 will have the highest priority. These priorities can be changed during an EOI command
by programming the rotate on specific EOI command in OCW2.
Special Mask Mode In the special mask mode, when a mask bit is set in OCW 1, it inhibits further
interrupts at that level and enables interrupt from other levels, which are not masked.

Edge and Level Triggered Mode: This mode decides whether the interrupt should be edge triggered or
level triggered. If bit LTIM of ICW 1 = 0, they are edge triggered, otherwise the interrupts are level
triggered.

Poll Command
 In the polled mode of operation, the INT output of 8259A is neglected, though it functions
normally, by not connecting INT output or by masking INT input of the microprocessor. The
poll mode is entered by setting P = 1 in OCW 3.
 The 8259A is polled by using software execution by microprocessor instead of the requests on
INT input. The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An
appropriate ISR bit is set, if there is a request. The priority level is read and a data word is placed
on to data bus, after RD is activated.

Special Fully Nested Mode

 This mode is used in more complicated systems, where cascading is used and the priority has to be
programmed in the master using ICW4. This is somewhat similar to the normal nested mode.
 In this mode, when an interrupt request from a certain slave is in service, this slave can further
send requests to the master, if the requesting device connected to the slave has higher priority than
the one being currently served.
 In this mode, the master interrupts the CPU only when the interrupting device has a higher or the
same priority than the one currently being served. In normal mode, other requests than the one
being served are masked out.
DMA CONTROLLER 8257
 The Direct Memory Access or DMA mode of data transfer is the fastest amongst all the modes
of data transfer. In this mode, the device may transfer data directly to/from memory without
any interference from the CPU.
 8257 is a four channel DMA controller designed to be interfaced with their family of
microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access
request input i.e. HOLD in minimum mode.
 In maximum mode of the microprocessor RQ/GT pin is used as bus request input. On
receiving the HLDA signal (in minimum mode) or RQ/ GT signal (in maximum mode)
from the CPU.
 The requesting device gets the access of the bus, and it completes the required number of DMA
cycles for the data transfer and then hands over the control of the bus back to the CPU.

INTERNAL ARCHITECTURE OF 8257

 The chip supports four DMA channels, i.e. four peripheral devices can independently
request for DMA data transfer through these channels at a time.
 The DMA controller has 8-bit internal data buffer, a read/write unit, a control unit, a priority
resolving unit along with a set of registers.

Register Organisation of 8257:

 The 8257 performs the DMA operation over four independent DMA channels. Each of the
four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and
terminal count register.
 Also, there are two common registers for all the channels, namely, mode set register and
status register. Thus there are a total of ten registers. The CPU selects one of these ten
registers using address lines A 0-A 3. Table below shows how the A 0-A 3 bits may be used
for selecting one of these registers.
DMA Address Registers
 Each DMA channel has one DMA address register. The function of this register is to
store the address of the starting memory location, which w ill be accessed by the DMA
channel.
 Thus the starting address of the memory block which will be accessed by the device
is first loaded in the DMA address register of the channel.
 The device that wants to transfer data over a DMA channel, will access the block of
memory with the starting address stored in the DMA Address Register.
Terminal Count Register:
 Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-
bitregister is used for ascertaining that the data transfer through a DMA channel ceases or
stops after the required number of DMA cycles. Thus this register should be appropriately
written before the actual DMA operation starts.
 The low order 14-bits of the terminal count register are initialized with the binary
equivalent of the number of required DMA cycles minus one.
 After each DMA cycle, the terminal count register content will be decremented by one
and finally it becomes zero after the required number of DMA cycles are over.
 The bits 14 and 15 of this register indicate the type of the DMA operation (transfer).
 Mode Set Register

 The mode set register is used for programming the 8257 as per the requirements of the
system. The function of the mode set register is to enable the DMA channels
individually and also to set the various modes of operation.
 A DMA channel should not be enabled till the DMA address register and the terminal
count register contain valid information, otherwise, an unwanted DMA request may
initiate a DMA cycle, probably destroying the valid memory data.

 A0-A15 DMA Starting Address, C0-C13 Terminal Count Value (N-1), Rd & Wr.

 Table of DMA Operation Selection Using A14 RD and A15.WR

Bit Bit Type of DMA

15 14 Operation
Verify DMA
0 0
Cycle
Write DMA
0 1
Cycle
Read DMA
1 0
Cycle
1 1 (Illegal)
.

MODE SET REGISTER

 If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is
reached, and it further prevents any DMA cycle on the channel. To enable the channel again,
this bit must be re-programmed.
 If the TC STOP bit is programmed to be zero, the channel is not disabled, even after the count
reaches zero and further requests are allowed on the same channel.
 The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without
immediate software intervention between the two successive blocks.
 The channel 2 registers are used as usual, while the channel 3 registers are used to store the block
re-initialization parameters, i.e. the DMA starting address and the terminal count.
  After the first block is transferred using DMA, the channel 2 registers are reloaded with the
corresponding channel 3 registers for the next block transfer, if the Update flag is set.
 The extended write bit, if set to '1', extends the duration of MEMW and IOW signals by
activating them earlier. This is useful in interfacing the peripherals with different access times.
 If the peripheral is not accessed within the stipulated time, it is expected to give the 'NOT
READY' indication to 8257, to request it to add one or more wait states in the DMA cycle. The
mode set register can only be written into.
STATUS REGISTER
 The lower order 4-bits of this register contain the terminal count status for the four individual
channels. If any of these bits is set, it indicates that the specific channel has reached the
terminal count condition.
 These bits remain set till either the status is read by the CPU or the 8257 is reset. The update
flag is not affected by the read operation. This flag can only be cleared by resetting 8257 or by
resetting the auto load bit of the mode set register.
 If the update flag is set, the contents of the channel 3 registers are reloaded to the corresponding
registers of channel 2, whenever the channel 2 reaches a terminal count condition, after
transferring one block and the next block is to be transferred using the auto load feature of
8257.
 The update flag is set every time, the channel 2 registers are loaded with contents of the channel
3 registers. It is cleared by the completion of the first DMA cycle of the new block. This register
can only be read.

Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver

 The 8-bit, tristate, bidirectional buffer interfaces the internal bus of 8257 with the external
system bus under the control of various control signals.
 In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals,
decodes the A0-A 3 lines and either writes the contents of the data bus to the addressed
internal register or reads the contents of the selected register depending upon whether
IOW or IOR signal is activated.
 In master mode, the read/write logic generates the IOR and IOW signals to control the
data flow to or from the selected peripheral. The control logic controls the sequences of
operations and generates the required control signals like AEN, ADSTB, MEMR,
MEMW, TC and MARK along with the address lines A4-A 7, in master mode.
 The priority resolver resolves the priority of the four DMA channels depending upon
whether normal priority or rotating priority is programmed.
Signal Descriptions of 8257

DRQ0-DRQ3: These are the four individual

channel DMA request inputs, used by the
peripheral devices for requesting DMA services.
The DRQ0 has the highest priority while DRQ3
has the lowest one, if the fixed priority mode is
selected.

DACKo -DACK3: These are the active-low

DMA acknowledge output lines which inform
the requesting peripheral that the request has been
honored and the bus is relinquished by the CPU.
These lines may act as strobe lines for the
requesting devices.
D0-D7 These are bidrectional, data lines used to
interface the system bus with the internal data bus
of 8257. These lines carry command words to
8257 and status word from 8257,in slave mode,
i.e. under the control of CPU. The data over these
lines may be transferred in both the directions.
When the 8257 is the bus master (master mode,
i.e. not under CPU control), it uses D0-D7 lines to
send higher byte of the generated address to the
latch. This address is further latched using ADSTB
signal. The address is transferred over D0-D7
during the first clock cycle of the DMA cycle.
During the rest of the period, data is available on
the data bus.
IOR: This is an active-low bidirectional tristate input
line that acts as an input in the slave mode. In slave
mode, this
input signal is used by the CPU to read internal registers of 8257. This line acts as output in master
mode. In master mode, this signal is used to read data from a peripheral during a memory write
cycle.

IOW: This is an active-low, bidirectional tristate line that acts as input in slave mode to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address
register or terminal count register. In the master mode, it is a control output that loads the data
to a peripheral during DMA memory read cycle (write to peripheral).

CLK: This is a clock frequency input required to derive basic system timings for the internal
operation of 8257.

RESET: This active-high asynchronous input disables all the DMA channels by clearing the mode
register and tri-states all the control lines.

A0-A3: These are the four least significant address lines. In slave mode, they act as input which
select one of the registers to be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
CS This is an active-low chip select line that enables the read/write operations from/to 8257, in
slave mode. In the master mode, it is automatically disabled to prevent the chip from getting
selected (by CPU) while performing the DMA operation.

A4-A7 This is the higher nibble of the lower byte address generated by 8257 during the master
mode of DMA operation.

READY This is an active-high asynchronous input used to stretch memory read and write cycles
of 8257 by inserting wait states. This is used while interfacing slower peripherals.

HRQ The hold request output requests the access of the system bus. In the non-cascaded 8257
systems, this is connected with HOLD pin of CPU. In the cascade mode, this pin of a slave is
connected with a DRQ input line of the master 8257, while that of the master is connected with
HOLD input of the CPU.

HLDA The CPU drives this input to the DMA controller high, while granting the bus to the
device. This pin is connected to the HLDA output of the CPU. This input, if high, indicates to the
DMA controller that the bus has been granted to the requesting peripheral by the CPU.

MEMR This active-low memory read output is used to read data from the addressed memory
locations during DMA read cycles.

MEMW This active-low three state output is used to write data to the addressed memory location
during DMA write operation.

ADSTB This output from 8257 strobes the higher byte of the memory address generated by the
DMA controller into the latches.

AEN This output is used to disable the system data bus and the control the bus driven by the
CPU. This may be used to disable the system address and data bus by using the enable input of the
bus drivers to inhibit the non-DMA devices from responding during DMA operations. This also may
be used to transfer the higher byte of the generated address over the data bus. Ifthe 8257 is VO
mapped, this should be used to disable the other I/Odevices, when the DMA controller address is on
the address bus.

TC
 Terminal count output indicates to the currently selected peripheral that the present DMA
cycle is the last for the previously programmed data block. If the TC STOP bit in the mode
set register is set, the selected channel will be disabled at the end of the DMA cycle.
 The TC pin is activated when the 14-bit content of the terminal count register of the selected
channel becomes equal to zero. The lower order 14 bits of the terminal count register are to
be programmed with a 14-bit equivalent of (N-1), if n is the desired number of DMA cycles.

MARK The modulo 128 mark output indicates to the selected peripheral that the current DMA
cycle is the 128th cycle since the previous MARK output. The mark will be activated after each
128 cycles or integral multiples of it from the beginning of the data block (the first DMA cycle), if
the total number of the required DMA cycles (n) is completely divisible by 128.

Vcc: This is a +5V supply pin required for operation of the circuit. GND. This is a return line for
the supply (ground pin of the IC).
 PROGRAMMABLE COMMUNICATION INTERFACE 8251 USART
Intel's 825lA is a universal synchronous asynchronous receiver and transmitter compatible with Intel's
Processors. This may be programmed to operate in any of the serial communication modes built into it. This
chip converts the parallel data into a serial stream of bits suitable for serial transmission. It is also able to
receive a serial stream of bits and convert it into parallel data bytes to be read by a microprocessor.

Architecture and Signal Descriptions of 825 I

 The architectural block diagram of 825 l A is followed by the functional description of each
block.
 The data buffer interfaces the internal bus of the circuit with the system bus. The read write
control logic controls the operation of the peripheral depending upon the operations initiated by
the CPU.
 This unit also selects one of the two internal addresses those are control address and data address
at the behest of the C/͞D signal. The modem control unit handles the modem handshake signals to
coordinate the communication between the modem and the USART.
 The transmit control unit transmits the data byte received by the data buffer from the CPU for
further serial communication. This decides the transmission rate which is controlled by the TXC
input frequency. This unit also derives two transmitter status signals namely
 TXRDY and TXEMPTY. These may be used by the CPU for handshaking. The transmit buffer is
a parallel to serial converter that receives a parallel byte for conversion into a serial signal and
further transmission onto the communication channel. The receive control unit decides the receiver
frequency as controlled by the RXC input frequency. This unit generates a receiver ready
(RXRDY) signal that may be used by the CPU for handshaking. This unit also detects a break in
the data string while the 8251 is in asynchronous mode. In synchronous mode, the 8251 detects
SYNC characters using SYNDET/BD pin.
The pin configuration of 825IA is shown in Fig. 6.27. The following text describes the signal
descriptions of 8251A:

D0-D7: This is an 8-bit data bus used to read or write status, command word or data from or to
the USART
C/͞D-Control Word/Data: This input pin, together with RD and WR inputs, informs the 825lA
that the word on the data bus is either a data or control word/status information. If this pin is 1,
control/status is on the bus, otherwise data is on the bus.
RD This active-low input to 825lA is used
to inform it that the CPU is reading either data or
status information from its internal
registers.
WR: This active-low input to 825lA is used
to inform it that the CPU is writing data or
control word to 825 1A.
CS-This is an active-low chip select input of
825lA. If it is high, no read or write
operation can be carried out on 8251. The
data bus is tristated if this pin is high.
CLK: This input is used to generate internal
device timings and is normally connected to
clock generator output. This input frequency
should be at least 30 times greater than the
receiver or transmitter data bit transfer rate.

RESET: A high on this input forces the

825 l A into an idle state. The device will
remain idle till this input signal again goes
low and a new set of control word is written
into it. The minimum required reset pulse
width is 6 clock states, for the proper reset operation.

TXC Transmitter Clock Input: This transmitter clock input controls the rate at which the
character is to be transmitted. The baud rate (lx) is equal to the TXC frequency in synchronous
transmission mode. In asynchronous mode, the baud rate is one of the three fractions, i.e. 1, 1/ 16 or
1/64 of the TXC. The serial data is shifted out on the successive negative edge of the TXC.

TXD Transmitted Data Output: This output pin carries serial stream of the transmitted data bits
along with other information like start bit, stop bits and parity bit, etc.
RXC Receiver Clock Input This receiver clock input pin controls the rate at which the character is to
be received. In synchronous mode, the baud rate is equal to the RXC frequency. In asynchronous mode,
the baud rate is one of the three fractions, i.e. 1, 1/16and l/64th of the RXC frequency. The received data
is read into the 8251 on rising edge of RXC. In most of the systems, the RXC and RXC frequencies are
equal.

RXD-Receive Data Input This input pin of 825lA receives a composite stream of the data to be
received by 825 IA.

RXRDY-Receiver Ready Output This output indicates that the 825IA contains a character to be read
by the CPU. The RXRDY signal may be used either to interrupt the CPU or may be polled by the CPU.
To set the RXRDY signal in asynchronous mode, the receiver must be enabled to sense a start bit and a
complete character must be assembled and then transferred to the data output register.
In synchronous mode, to set the RXRDY signal, the receiver must be enabled and a character must finish
assembly and then be transferred to the data output register. If the data is not successfully read from the
receiver data output register before assembly of the next data byte, the overrun condition error flag is set
and the previous byte is over written by the next byte of the incoming data and hence it is lost.

TXRDY-Transmitter Ready This output signal indicates to the CPU that the internal circuit of the
transmitter is ready to accept a new character for transmission from the CPU. The TXRDY signal is set
by a leading edge of write signal if a data character is loaded into it from the CPU. Inthe polled
operation, the TXRDY status bit will indicate the empty or full status of the transmitter data input
register.

DSR -Data Set Ready This input may be used as a general purpose one bit inverting input port. Its
status can be checked by the CPU using a status read operation. This is normally used to check if the
data set is ready when communicating with a modem.

DTR -Data Terminal Ready This output may be used as a general purpose one bit inverting output
port. This can be programmed low using the command word. This is used to indicate that the device is
ready to accept data when the 8251 is communicating with a modem.

RTS-Request to Send Data This output also may be used as a general purpose one bit inverting out- put
port that can be programmed low to indicate the modem that the receiver is ready to receive a data byte
from the modem. This signal is used to communicate with a modem.

CTS -Clear to Send If the clear to send the input line is low, the 8251A is enabled to transmit the serial
data, provided the enable bit in the command byte is set to '1'. If a Tx disable or CTS disable command
occurs, while the 825lA is transmitting data, the transmitter transmits all the data written to the USART
prior to disabling the CTS or Tx. If the CTS disable or Tx disable command occurs just before the last
character appears in the serial bit string, the character will be retransmitted again whenever the CTS is
enabled or the Tx enable occurs.

TXE-Transmitter Empty If the 825lA, while transmitting, has no characters to transmit, the TXE
output goes high and it automatically goes low when a character is received from the CPU, for further
transmission. In synchronous mode, a 'high' on this output line indicates that a character has not been
loaded the SYNC character or characters are about to be or are being transmitted automatically as 'fillers'. The
TXE signal can be used to indicate the end of a transmission mode.
SYNDET/BD-Synch Detect/Break Detect This pin is used in
 The synchronous mode for detecting SYNC characters (SYNDET) and may be used as either input or
output. This can be programmed using the control word. After resetting, it is in the output mode. When
used as an output, the SYNDET pin will go high to indicate that the 825lA has located a SYNC character
in the receive mode.
 The SYN-DET signal is automatically reset upon a following status read operation. When this is used as
input, a positive going signal will cause the 825lA to start assembling a data character on the rising edge
of the next RXC.
 In the asynchronous mode, the pin acts as a break detect output. This goes high whenever the RXD pin
remains low through two consecutive stop bit sequences. A stop bit sequence contains a stop bit, a start
bit, data bits and parity bits. This is reset only with master chip reset or the RXD returning high.
 If the RXD re- turns to '1', during the last bit of the next character after the break, the break detect is
latched up. The 825 lA can now be cleared only with chip reset.

Description of 8251A Operating Modes

 The 8251 can be programmed to operate in its various modes using its mode control words. A set of
control words is written into the internal registers of 825 IA to make it operate in the desired mode.
 Once the 825lA is programmed as required, the TXRDY output is raised 'high' to signal the CPU that
the 825l is ready to receive a data byte from it that is to be further converted to serial format and
transmitted.
 This automatically goes low when CPU writes a data byte into 8251A. In receiver mode, the 8251A
receives a serial data byte from a modem or an I/O device. After receiving the entire data byte, the
RXRDY signal is raised high to inform the CPU that the 825 IA has a character ready for it.
 The RXRDY signal is automatically reset after the CPU reads the received byte from the 8251. The
8251A cannot initiate transmission until the TX enable bit in the command word is set and a CTS
signal is received from the modem or receiving I/0 device.

The control words of 825lA are divided into two functional types:

Mode Instruction control word

Command Instruction control word

Asynchronous Mode

Mode Instruction Control Word This defines the general operational characteristics of 825lA. After
internal (reset command) or external (reset input pin) reset, this must be written to configure the 825lA as
per the required operation. Once this has been written into 8251A, SYNC characters or command
instructions may be programmed further as per the requirements. To change the mode of operation from
synchronous to asynchronous or vice-a-versa, the 825 1A has to be reset using master chip reset.

Asynchronous Mode (Transmission) When a data character is sent to 8251A by the CPU, it adds start
bits prior to the serial data bits, followed by optional parity bit and stop bits using the asynchronous mode
instruction control word format. This sequence is then transmitted using TXD output pin on the falling edge
of TXC . When no data characters are sent by the CPU to 825 IA the TXD output remains 'high', if a 'break'
has not been detected.
 Mode Instruction Format

Asynchronous Mode (Receive)

 A falling edge on RXD input line marks a start bit. At baud rates of 16x and 64x, this start bit is
again checked at the center of start bit pulse and if detected low, it is a valid start bit which starts
counting. The bit counter locates the data bits, parity bit and stop bit.
 If a parity error occurs, the parity error flag is set. If a low level is detected as the stop bit, the
framing error flag is set. The receiver requires only one stop bit to mark end of the data bit string,
regardless of the stop bit programmed at the transmitting end.
 This 8-bit character is then loaded into parallel I/O buffer of 8251A. RXRDY pin is then raised
high to indicate to the CPU that a character is ready for it. If the previous character has not been
read by the CPU, the new character replaces it, and the overrun flag is set indicating that the
previous character is lost.
 These error flags can be cleared using an error reset instruction. If character length is 5 to 7 bits
then the remaining bits are set to zero.

Synchronous Mode (Transmission)

 The TXD output is high until the CPU sends a character to 8251A which usually is a SYNC
character. When CTS line goes low, the first character is serially transmitted out. All the
characters are shifted out on the falling edges of TXC. Data is shifted out at the same rate as
TXC, over TXD output line.
 If the CPU buffer becomes empty, the SYNC character or characters are inserted in the data
stream over TXD output. The TXEMPTY pin is raised high to indicate that the 825lA is empty
(i.e. it does not have any byte to transmit) and is transmitting SYNC characters. The TXEMPTY
pin is reset, automatically when a data character is written to 825lA by the CPU.
Synchronous Mode (Receiver):
 In this mode, the character synchronization can be achieved internally or externally. If this mode
is programmed, then 'ENTER HUNT' command should be included in the first command
instruction word written into the 825lA. The data on RXD pin is sampled on rising edge of the
RXC.
 The content of the receiver buffer is compared with the first SYNC character at every edge until
it matches. If 8251A is programmed for two SYNC characters, the subsequent received character
is also checked. When both the characters match, the hunting stops.
 The SYNDET pin is set high and is reset automatically by a status read operation. If a parity bit
is programmed, the SYNDET signal will not go as high as the middle of parity bit, or till the
middle of the last data bit.
 In the external SYNC mode, synchronization is achieved by applying a high level on the
SYNDET input pin that forces 8251A out of HUNT mode. The high level can be removed after
one RXC cycle.
 An ENTER HUNT command has no meaning in asynchronous mode. The parity and overrun
error both are checked in the same way as in asynchronous mode.

Synchronous Mode Instruction Format

Command Instruction Definition:

The command instruction controls the actual operations of the selected format like enable
transmit/receive, error reset and modem control. Once the mode instruction has been written into 825 IA
and the SYNC characters are inserted internally by 825lA, all further control words written with C/D͞ = 1
will load a command instruction. A reset operation returns 825lA back to mode instruction format.
Status Read Definition:

 This definition is used by the CPU to read the status of the active 825lA to confirm if any error
condition or other conditions like the requirement of processor service has been detected, during
the operation.
 A read command is issued by processor with C/D͞ = 1to accomplish this function. Some of the bits
in the definition have the same significances as those of the pins of 825 IA. These are used to
interface the 825lA in a polled configuration, besides the interrupt controlled mode. The pin
TXRDY is an exception.

Command Instruction Format

Status Read Instruction Format