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Topic – Layout in VLSI Top 20 VLSI
Layout Interview
Questions &
Answers
Prepared by : VLSI Geeks
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Top 20 VLSI Layout Interview Questions
and Answers
1. What is the difference between DRC and LVS?
DRC (Design Rule Check) verifies that the layout complies with the set of manufacturing
rules defined by the foundry, such as spacing, width, enclosure, and density rules. Violations
might lead to issues during fabrication or poor yield. LVS (Layout Versus Schematic)
compares the extracted netlist from the layout with the schematic netlist to ensure
functional correctness — it checks connectivity, device matching, and parameter values to
confirm that the physical layout matches the intended circuit design.
2. What is antenna effect in VLSI layout?
The antenna effect arises when long interconnect lines, especially during intermediate
metal processing, collect charge from plasma etching. If these lines are not connected to the
gate oxide of a MOS transistor through diffusion or contacts, the charge may accumulate and
damage the thin gate oxide. This is mitigated using antenna diodes that provide a discharge
path, or by rerouting with higher metal layers that have vias already formed to diffusion.
3. What is the purpose of the well tap and substrate contact?
Well taps and substrate contacts serve to properly bias the wells (n-well for PMOS and p-
substrate for NMOS) to VDD and GND respectively. This prevents floating wells, reduces
susceptibility to noise and latch-up, and ensures correct transistor operation. Without
these, minority carriers can build up, leading to unintended conduction paths or failure.
4. What is a via, and why are multiple vias used?
Vias are vertical interconnects that connect metal layers (e.g., Metal1 to Metal2). Using
multiple vias between layers increases current-carrying capacity, improves reliability, and
reduces resistance and electromigration risks. It’s a standard practice to use via arrays in
power and high-current nets.
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5. What is the significance of metal density rules?
Metal density rules ensure uniform distribution of metal across the chip. Non-uniform metal
distribution causes dishing or erosion during CMP (Chemical Mechanical Planarization),
which leads to variations in thickness, parasitics, and yield. Foundries specify both
minimum and maximum density constraints to ensure reliable manufacturing.
6. What are dummy fills and why are they needed?
Dummy fills are non-functional shapes (usually metal or poly) added to regions with low
pattern density. They help meet metal or poly density requirements for planarization and
reduce topography variations. They are spaced so that they do not interfere with signal
lines or cause parasitic coupling.
7. What is latch-up and how is it prevented?
Latch-up is a condition where a parasitic SCR (Silicon-Controlled Rectifier) forms a low-
impedance path between power and ground, leading to excessive current and potential chip
destruction. It’s prevented by using proper well tap spacing, guard rings, deep n-well
isolation, and substrate contacts to keep junctions properly biased and limit injection
currents.
8. What is a guard ring and its function?
A guard ring is a ring of diffusion tied to VDD or GND surrounding sensitive devices or
blocks. It collects injected carriers and prevents latch-up and noise coupling. It provides
isolation between analog/digital or high-voltage/low-voltage domains and is commonly
used around ESD structures or IO pads.
Fig. – Showing guard ring (just for representational purpose)
9. What is the difference between soft and hard macros?
Soft macros are IPs delivered in synthesizable RTL (e.g., Verilog or VHDL), giving flexibility
to the implementation team for synthesis and place & route. Hard macros are fully placed
and routed blocks (e.g., memories, PLLs) delivered as GDSII files with fixed area, power, and
timing characteristics.
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10. Why is metal slotting used?
Wide metal lines are slotted to relieve mechanical stress during fabrication and to meet
metal density rules. Without slotting, metal layers may peel or crack due to thermal
expansion and stress differences during CMP or etching.
11. What is electromigration and how is it addressed in layout?
Electromigration is the movement of metal atoms caused by high current densities, leading
to open circuits or voids over time. It’s addressed by ensuring that current density limits are
not exceeded, using wider metal traces, redundant vias, and verifying with EM-aware tools
during physical verification.
12. What is the use of N-well proximity spacing rule?
This rule ensures that N-wells are spaced sufficiently apart to avoid latch-up and leakage.
When N-wells from different voltage domains are placed too close, junction leakage or
unintended conduction paths can form, causing circuit malfunction.
13. What is a filler cell in standard cell layout?
Filler cells are non-functional cells inserted between standard cells to fill gaps. They
maintain continuity of metal rails (like VDD/GND) and satisfy well tie and spacing rules.
They also help align edge boundaries of cell rows.
14. What are boundary cells?
Boundary cells are special cells placed at the edges of macros or rows to isolate the core
logic from periphery circuits. They prevent signal leakage, protect signal integrity, and
ensure DRC compliance at the die edge.
15. What is the function of decap cells?
Decap cells are standard cells that contain large decoupling capacitors between power and
ground rails. They stabilize supply voltage by absorbing noise and switching transients,
improving power integrity in dense switching blocks.
16. What are metal slot and stripe structures?
Metal stripes are wide wires used for power delivery. To manage thermal stress and meet
density rules, these stripes are slotted (have periodic gaps) to improve reliability. Slotting
helps prevent cracking and ensures uniform etch characteristics.
17. What is meant by M1 pitch and its significance?
M1 pitch is the center-to-center distance between two adjacent Metal1 lines. It defines the
minimum routing pitch and impacts the cell height, area, and routability. Smaller pitch
enables higher density but requires more advanced manufacturing processes.
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18. What is the role of the placement blockage?
Placement blockages restrict standard cell placement in specific regions, like analog blocks,
macro boundaries, or timing-critical areas. They help avoid congestion, signal interference,
or unintended overlaps with special IPs.
19. What is IR drop and how is it minimized?
IR drop is the voltage drop across power distribution lines due to resistance. It is minimized
by using wider metal rails, multiple vias, power mesh structures, and inserting decap cells.
Accurate IR analysis tools help identify hotspots early in the design.
20. What are the typical steps in physical verification?
Physical verification includes:
- DRC (Design Rule Check)
- LVS (Layout vs. Schematic)
- ERC (Electrical Rule Check)
- Antenna checks
- Density and CMP checks
Each step ensures manufacturability, correctness, and long-term reliability of the chip
before tape-out.
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