Prerana Educational and Social Trust (R.
)
PES INSTITUTE OF TECHNOLOGY AND MANAGEMENT
NH-206, Sagar Road, Shivamogga-577204, Karnataka, India.
Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi, Recognised by Govt. of Karnataka
Department of Computer Science &Engineering (Data Science)
MICROCONTROLLERS (BCS402) QUESTION BANK
🔹 Module 1 – ARM Basics & Embedded Systems
1. Differentiate between i) Microcontroller and Microprocessor ii) RISC vs CISC iii)
Applications of ARM Microcontroller
2. Write a note on i) RISC design philosophy (4 rules) ii) ARM design philosophy
3. Explain the ARM embedded device architecture with a neat diagram. (Embedded
System hardware/hardware components/AMBA bus technology)
4. Describe embedded system software components and their roles.
5. With a neat diagram, explain ARM core dataflow model. (general purpose registers
and special registers)
6. Describe the Current Program Status Register (CPSR). (monitor & control operations)
7. Discuss ARM Processor Modes and Banked Registers with neat figures.
8. What is ARM pipeline? Illustrate the stages in ARM 9 and ARM10 with example.
9. Describe core extensions in ARM with neat block diagram.
🔹 Module 2 – ARM Instruction Set
1. Explain different data processing instructions in ARM with examples. (MOV, MVN..)
2. Explain different ARM arithmetic instructions with examples. (ADD,RSB,ADC…)
3. Discuss ARM logical and compare instructions with examples (AND, EOR, CMP, CMN,
TEQ, TST)
4. Explain barrel shifter operations with neat figure and examples. (LSL, ASR, ROR…)
5. Explain branch instructions in ARM with execution flow and examples. (B, BL, BX)
6. Describe single-register load/store addressing modes with syntax and examples
7. Describe multiple-register load/store addressing modes with syntax and examples.
8. Write a note on i) Stack operation in ARM ii) Swap (Both with eamples)
9. Explain software interrupt (SWI) instruction and their usage. (complete description
with example).
10. Describe Program Status Register instructions and usage. (MRS, MSR)
11. Discuss coprocessor instructions in ARM with example. (CDP, MRC MCR, LDC STC)
12. Compare conditional execution in ARM instructions (e.g., EQ, NE conditions).
Note: MLA, ASR, BIC, CMN, MVN, MRS, MSR, RSC, LDR, STRH, SWP
Prerana Educational and Social Trust (R.)
PES INSTITUTE OF TECHNOLOGY AND MANAGEMENT
NH-206, Sagar Road, Shivamogga-577204, Karnataka, India.
Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi, Recognised by Govt. of Karnataka
Department of Computer Science &Engineering (Data Science)
🔹 Module 3 – C Compilers & Optimization
1. Explain different basic data types in C with example programs.
2. Describe efficient use of C types. (avoiding char and short). (v1 to v4 examples)
3. How compiler handles fixed number of iterations with example. (v5 and v6).
4. How compiler handles a “for loop” with variable number of iterations N and loop
controlling with examples. (v7 to v10)
5. Discuss Register allocation strategies for optimization in ARM.
6. Explain pointer aliasing and its implications on optimization with examples.
7. Explain function calling is used by ARM through APCS with an example.
8. Discuss any 6 portability issues and how compilers address them.
9. Develop an ALP to find sum the first 10 integers.
10. Write C program to print squares of 0–9 using functions and explain conversion to
assembly function with command.
11. Write an ALP and C program to find smallest/largest number/arrange in
ascending/descending order.
Note: Read All Lab programs that can be asked in 2nd and 3rd Modules
🔹 Module 4 – Exception Handling & Firmware
1. What are Interrupts? Explain ARM processor exceptions and modes along with vector
Table with neat figure and Table.
2. Explain exception priorities and link register offset with neat tables for both.
3. Describe assigning interrupts and interrupt latency.
4. Illustrate sequence of operations that occurs when an IRQ and FIQ exceptions is
raised with an ARM processor with neat flow diagrams.
5. Write a code to enable and disable IRQ and FIQ interrupts.
6. Outline basic interrupt stack design & implementation with neat figures and
example.
7. What is Firmware & Bootloader? Describe Firmware Execution Flow.
8. List features of ARM firmware suite(Angel, HAL) with examples (e.g., RedBoot).
9. Explain Sandstone directory layout and execution flow.
Note: Part1 – 1 to 6
Part2 – 7 to 9
Prerana Educational and Social Trust (R.)
PES INSTITUTE OF TECHNOLOGY AND MANAGEMENT
NH-206, Sagar Road, Shivamogga-577204, Karnataka, India.
Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi, Recognised by Govt. of Karnataka
Department of Computer Science &Engineering (Data Science)
🔹 Module 5 – Cache & Memory Architecture
1. Write a note on memory hierarchy with neat diagram.
2. Write a note on i) MMU ii) Logical and Physical Cache with neat figures
3. Draw and explain the basic architecture of cache memory.
4. Describe process involved in mapping main memory to cache memory. (operation of
cache controller) with neat figure.
5. Explain set associative cache with a block diagram.
6. Explain Write Buffer and Cache Efficiency(equation).
7. Write a note on Cache write policy both write back or write through.
8. Discuss cache line replacement policies
9. Explain allocation policy on a cache miss.
10. Describe the role of Coprocessor 15 in cache control.
Nithin H V Dr. Sunitha B S
Course Instructor HOD
