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Procedure

The document outlines procedures for receiving and sending MSI interrupts using the AXI bridge. It details steps for enabling the MSI controller, programming addresses, detecting transactions, handling interrupts, and acknowledging them. Additionally, it describes the process for sending an MSI interrupt, including enabling generation, setting parameters, initiating requests, and verifying transmission.

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44 views2 pages

Procedure

The document outlines procedures for receiving and sending MSI interrupts using the AXI bridge. It details steps for enabling the MSI controller, programming addresses, detecting transactions, handling interrupts, and acknowledging them. Additionally, it describes the process for sending an MSI interrupt, including enabling generation, setting parameters, initiating requests, and verifying transmission.

Uploaded by

kvasita1
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Procedure: Receiving an MSI Interrupt Using the AXI Bridge

Steps
1. Enable MSI Controller:
o Activate the MSI interrupt controller by setting CX_MSI_CTRL_ENABLE to 1.
This prevents MSI write transactions from propagating onto the AXI bus and
enables local handling.
2. Program MSI Address:
o Configure the system MSI address in MSI_CTRL_ADDR_REG and
MSI_CTRL_UPPER_ADDR_REG.
3. Enable Interrupt Vectors:
o Use the MSI_CTRL_INT_0_EN_REG register to enable the desired MSI interrupt
vectors for detection.
4. Detect MSI Transactions:
o The MSI controller monitors incoming memory write transactions for a match with
the programmed MSI address and other attributes such as:
 No-snoop (NS) and relaxed ordering (RO) set to 0.
 Length field indicating a payload of 1 DWORD.
 Specific byte enable (FBE and LBE) settings.
5. Handle MSI Interrupts:
o When a valid MSI is detected:

 The msi_ctrl_int signal is asserted.


 The vector details are logged in MSI_CTRL_INT_0_STATUS_REG.
6. Acknowledge and Clear Interrupts:
o Read the interrupt status register to identify the active vector.

o Write 1 to the corresponding bit in MSI_CTRL_INT_0_STATUS_REG to clear the


interrupt.
Important Considerations:
 MSI detection only operates when at least one interrupt vector is enabled.
 Masking individual vectors can be controlled via the MSI_CTRL_INT_0_MASK_REG.
Procedure: Sending an MSI Interrupt Using the MSI Interface
Steps
1. Enable MSI Generation:
o Assert the cfg_msi_en bit in the MSI control register to enable MSI functionality.

2. Set MSI Parameters:


o Write the target MSI address to the MSI Lower Address and MSI Upper Address
registers.
o Write the MSI data (corresponding to the interrupt vector) into the MSI Data
register.
3. Initiate MSI Request:
o Use the ven_msi_req signal to request the core to generate an MSI.

o Provide additional MSI parameters:

 ven_msi_vector[4:0] to specify the vector ID.


 ven_msi_func_num to identify the function making the request.
 ven_msi_tc[2:0] to select the traffic class.
4. Perform Handshake:
o Keep ven_msi_req asserted until the core acknowledges the request by
asserting the ven_msi_grant signal (a one-cycle pulse).
5. Handle Multiple Requests:
o If additional MSI requests are required, reassert ven_msi_req without waiting for
deassertion.
6. Verify MSI Transmission:
o Check the corresponding status registers or logs to confirm successful
transmission of the MSI.

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