DAR ES SALAAM INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER STUDIES
END OF SEMESTER I EXAMINATION – 2013/2014
CSEU 07302 MICROPROCESSOR TIME: 3HRS
B Eng. 12Co, E, and T
Instructions
1. This paper consists of two sections A and B
2. Answer ALL questions, in Section A and Any Three questions from section B
3. Cellular phones are not allowed in the examination room.
4. Write your examination number in every page of your answer booklet(s) provided.
5. You are not allowed to write anything in the question paper.
6. The use of computer is STRICTLY NOT ALLOWED
This paper consists of four (2) printed pages
SECTION A (20 Marks)
Answer all questions in this section
1. (a) Describe two methods of interfacing I/O devices in Microprocessor systems
(b) List two groups of signals that interconnect the components of microprocessor system.
(c) List two main types of computer memory and give two example of each.
(d) Why are RAMS not usually used for long term storage?
(e) Why are Three-state drivers useful in computer hardware?
(f) Why can microprocessor system perform many different functions?
(g) What is the name of a program which is executed by the CPU when an interrupt occurs?
(h) Describe a programmable interface device
(i) Describe a programmable timer/counter device.
(j) How microprocessor does know which bytes to interpret as opcodes?
Section B. Answer only four questions. Each question is 10 marks
2. Given two 3X8 decoder and I/O devices, (a) design and draw an I/O interface circuit where the
address of both the input and output is 51H. (b) The input address is 51 while the output is 55
3 a) List and describe three operating modes of the Intel 8255A in I/O mode.
(b) Write a control word to setup the Intel 8255A programmable Peripheral Interface such that ports A and C
are used to control a keyboard. Port A is used as an input port and port C is a scan port of the keyboard. Port
B is used to connect the input switches. Use Fig. 1 if required.
1=I/O mode, 0 =BSR mode Port C lower ( 1=input, 0=output)
Mode port A: (00=mode 0, 01=mode 1, 1X= 2) Port B (1=input, 0=output)
Port A: ( 1= input, 0 = output) Port B Modes: (0 =mode 0, 1=mode 1)
Port C upper: (1=input, 0=output)
Fig. 1
(4) Two kilobyte of RAM and 2K byte ROM memory is required. Design a memory interface for the
memory, given one 3 X 8 decoder and several memory chips of 2K X 4 of RAM and ROM. The
starting address of the ROM is 0000H. The RAM starts where the ROM ends. Give the address of
the last memory location on the RAM.
(5) Write an Intel 8085 microprocessor machine language which will copy 256 byte of data from
memory location starting address 4000H and copy it to memory location starting from address
5000H.
(6) Write a program to generate a squire waveform using.
(7) (a) List two major architectural differences between microprocessors.
(b) List and describe three microprocessor architectural techniques being used to increase speed.
Marking scheme
SECTION A (20 Marks)
Answer ten Questions only, Each question carry Two marks.
Q. 1 (a) Memory mapped: This is a method where by the address of I/O are part of the memory map. The
address bits for the memory are the same as those of I/O devices. The I/O commands are the same as
the read and write command for memory. The second method is I/O mapped. In this method the
address for I/O and memory are separated. When the CPU wants to read or write it differentiates
(b) (i) Address bus, (ii) Data bus, (iii) Control bus
(c) (i) Main memory: ROM and RAM; (ii) Secondary or storage memory: Disks and tapes
(d) They are not used for long term storage because they loose data storage when power is switch off.
(e) Three state drivers are useful because they allow more than one device to be connected together
and communicate through that point
(f) Microprocessor can perform many different functions because in most of the function are done though
program. With change of a program the processor will perform different activities.
(g) The program is known as interrupt servicing routine (ISR).
(h) Is a device designed perform various input/output functions, and these functions can be programmed
into the device by writing an instruction in its internal register, called the control register
(i) The are devices designed to generate accurate time delayers using the system’s clock and count
occurrences of external events. It can be used for applications such as a real time clock, an event
counter, and a signal generator.
(j) The microprocessor knows which code to interpret as opcodes because each opcode implies the number
of information bytes that follow it. And the first byte is the opcode.
Section B. Answer only four questions. Each question is 10 marks
Q.2
A5 A7 A6
(a) OO
OUTPUT
A4
A3
A2 Q4
A1 A0
O
OO
INPUT
Q2
IORQ
RD
WR
Q1
O
A5 A7 A6
(b) OO
Q5
AND OUTPUT
A4
A3
A2
Q4 AND
A1 A0
O
OO
INPUT
Q2
IORQ
RD
WR
Q1
3. (a)(i) Mode 0 Simple I/O for port A, B and C
(ii) Mode 1 Hand shaking I/O for port A, B. Port C bits used for handshake
(ii) Mode 2 Bidirectional data bus for port A.
(b) Control word is 92 please see the drawing below
4.
1 0 0 1 0 0 1 0
4
A14 A15 +5V
O O
A13 Q1
A12 Q0
A11
A10
O O O O O O O O O O
CS RD
CS RD CS RD WR CS RD WR
2048K
2048K 2048 K 208K
A0
D7 D4 D3 D0 D7 D4 D3 D0
5.
LABLE MNUMONICS ADDRESS CONTS
START MVI H,FF 0800 26
0801 FF
LXI B,4000 0802 01
0803 00
0804 40
LXI D,5000 0805 11
0806 00
0807 50
AGAIN LDAX B 0808 0A
STAX D 0809 1A
DCX B 080A 0B
DCX D 080B 1B
DCR H 080C 25
JNZ AGAIN 080D C2
080E 08
080F 08
HLT 0810 76
6. START: MVI A,00H
LOOP: STA OUT
CALL DELAY
MVI A, FFH
STA OUT
CALL DELAY
JMP LOOP
HLT
DELAY: MVI B, COUNT
RPT: DCR B
JNZ RPT
RET
7. (a) (i) Length of the microprocessor’s data word.
(ii) The size of memory which the microprocessor can directly address
(iii) The speed which the microprocessor can execute instruction.
(b) (i) Parallel processing: Is a method where processing involves two microprocessors in the same
product. Two microprocessors working on a job which could be done by a single processor but
which can be done faster with two microprocessors.
(ii) Co-processor: Is very much like processing. In this case you have the main processor and
another processor helping the main processor to do specific/special functions.
(iii) Cache memory: Is a very fast memory. This very fast memory may be locked very close to the
microprocessor or it may be included with the microprocessor. The data or instructions are
per-fetched and put in the cache memory so the CPU can access data or instruction very fast.
(iv) Pipelining: Is another architecture technique where it works like an assembly line. The
pipelined architecture processes a number of instructions at one time. Each instruction is
processed a little at each station just like a production is built at each station on an assembly
line. This makes the process is done quicker because each station has dedicated logic to do the
process faster.
(v) Wide data bus: Wide data bus allows the user to process certain functions faster because it
eliminates the need to perform an intermediate storage in memory.
