3-BUS CONCEPT AND MICROPROCESSOR OPERATION

The 3-Bus concept is a term used to describe the communication system of

a microprocessor. It describes the communication within and outside the
microprocessor that results in the transfer of data between different
components of the microprocessor and/or other devices.

A bus is a set of physical connections (cables, circuits, etc.) that can be

shared by multiple hardware components to communicate with one
another. Memory and input/ output devices are connected to the Central
Processing Unit through a group of lines called a bus. These lines are
designed to transfer data between different components. A bus connects
independent components of a computer system to pass signals between
them. The computer system bus is the method by which data is
communicated between all the internal pieces of a computer. The bus has
features such as bus width and bus speed that affects the system
performance. The bus width is the number of bits (electrical wires) the bus
can carry at time. There are 8-, 16-, 32-, and 64-bit buses where each wire
carries 1-bit at a time. The bus speed, on the other hand, is the number of
data packets sent or received per second. It is measured in Hertz. The bus
speed is also known as the Front Side Bus (FSB) speed. The product of the
bus speed and the width is known as the bus bandwidth. Buses serve the
following functions: (a) Data sharing, (b) Addressing, (c) Control signal, (d)
Provision of power to components, and (e) Sharing of system time.

The bus system is the important part of computer architecture which helps
the computer microprocessor to communicate efficiently with memory as
well input/output devices. The performance and reliability of a computer
system is dependent on the design and implementation of the computer
bus system. At a high level, the System Bus: connects the processor to the
RAM, to the hard drive, to the I/O drives, and to all the other components of
the computer.

Types of Computer Bus

• Address Bus
• Data Bus
• Control Bus

1. Address Bus
Address Bus is a collection of wires used to identify particular location in
main memory. Put differently, the information used to describe the memory
locations travels along the address bus.

The address bus transports memory addresses which the processor wants
to access in order to read or write data. The address bus is unidirectional.

The size of address bus determines how many unique memory locations
can be addressed.

Example:

A system with 4-bit address bus can address 16 Bytes of memory.

A system with 16-bit address bus can address 64 KB of memory

A system with 20-bit address bus can address 1 MB of memory.

2. Data Bus

A collection of wires through which data is transmitted from one part of a

computer to another is called Data Bus. Data Bus can be thought of as a
highway on which data and instructions travels within a computer. The main
objective of data bus is transfer of the data between microprocessor to
input/ output devices or memory. The data bus transfers instructions
coming from or going to the processor.

The data bus is bidirectional because the data can flow in either direction
from CPU to memory (or input/output device) or from memory to the CPU.

The size (width) of bus determines how much data can be transmitted at
one time.

Example:

A 16-bit bus can transmit 16 bits of data at a time.

32-bit bus can transmit 32 bits at a time.

3. Control Bus

The connections that carry control information between the microprocessor

and other devices within the computer is called Control Bus.
The main objective of control bus is the carriage of all signal’s controller from
processor to other hardware device. The control bus transports orders and
synchronization signal coming from the control unit and travelling to all
other hardware components

The Control bus is bidirectional because the data can flow in either direction
from CPU to memory (or input/output device) or from memory to the CPU.

It also transmits response signals from the hardware.

Example:

This bus is used to indicate whether the microprocessor is reading from

memory or writing to memory.

The system bus combines the functions of the control, address, and data
bus. Each byte of memory stored in RAM has a unique address associated
with it, which are similar to IP addresses. When the microprocessor wants to
access data that is stored in memory, it puts the data address on the
address bus, and then sets the control bus to indicate that it is waiting for
data. The main memory controller will place the requested data on the data
bus and change the control bus to indicate that the data is ready. The
microprocessor is then free to read the data from the data bus.

Peripheral Bus concepts

A device requires both input and output to be useful. There are a number of
common concepts required for useful communication with peripherals.

Interrupts

An interrupt allows the device to literally interrupt the processor to flag some
information. For example, when a key is pressed, an interrupt is generated to
deliver the key-press event to the operating system. Each device is assigned
an interrupt by some combination of the operating system and BIOS.

Devices are generally connected to an programmable interrupt

controller (PIC), a separate chip that is part of the motherboard which
buffers and communicates interrupt information to the main processor.
Each device has a physical interrupt line between it and one of the PIC's
provided by the system. When the device wants to interrupt, it will modify the
voltage on this line.

A very broad description of the PIC's role is that it receives this interrupt and
converts it to a message for consumption by the main processor. While the
exact procedure varies by architecture, the general principle is that the
operating system has configured an interrupt descriptor table which pairs
each of the possible interrupts with a code address to jump to when the
interrupt is received.

Overview of handling an interrupt

The device raises the interrupt to the interrupt controller, which passes the
information onto the processor. The processor looks at its descriptor table,
filled out by the operating system, to find the code to handle the fault.

Most drivers will split up handling of interrupts into bottom and top halves.
The bottom half will acknowledge the interrupt, queue actions for processing
and return the processor to what it was doing quickly. The top half will then
run later when the CPU is free and do the more intensive processing. This is
to stop an interrupt hogging the entire CPU.

Types of interrupts

There are two main ways of signalling interrupts on a line

— level and edge triggered.

Level-triggered interrupts define voltage of the interrupt line being held high
to indicate an interrupt is pending. Edge-triggered interrupts
detect transitions on the bus; that is when the line voltage goes from low to
high. With an edge-triggered interrupt, a square-wave pulse is detected by
the PIC as signalling and interrupt has been raised.

The difference is pronounced when devices share an interrupt line. In a level-

triggered system, the interrupt line will be high until all devices that have
raised an interrupt have been processed and un-asserted their interrupt.

In an edge-triggered system, a pulse on the line will indicate to the PIC that
an interrupt has occurred, which it will signal to the operating system for
handling. However, if further pulses come in on the already asserted line
from another device.

The issue with level-triggered interrupts is that it may require some

considerable amount of time to handle an interrupt for a device. During this
time, the interrupt line remains high and it is not possible to determine if any
other device has raised an interrupt on the line. This means there can be
considerable unpredictable latency in servicing interrupts.

With edge-triggered interrupts, a long-running interrupt can be noticed and

queued, but other devices sharing the line can still transition (and hence
raise interrupts) while this happens. However, this introduces new problems;
if two devices interrupt at the same time it may be possible to miss one of
the interrupts, or environmental or other interference may create
a spurious interrupt which should be ignored.

Non-maskable interrupts

It is important for the system to be able to mask or prevent interrupts at

certain times. Generally, it is possible to put interrupts on hold, but a
particular class of interrupts, called non-maskable interrupts (NMI), are the
exception to this rule. The typical example is the reset interrupt.

NMIs can be useful for implementing things such as a system watchdog,

where a NMI is raised periodically and sets some flag that must be
acknowledged by the operating system. If the acknowledgement is not seen
before the next periodic NMI, then system can be considered to be not
making forward progress. Another common usage is for profiling a system.
A periodic NMI can be raised and used to evaluate what code the processor
is currently running; over time this builds a profile of what code is being run
and create a very useful insight into system performance.

IO Space

Obviously, the processor will need to communicate with the peripheral

device, and it does this via IO operations. The most common form of IO is so
called memory mapped IO where registers on the device are mapped into
memory. This means that to communicate with the device, you need simply
read or write to a specific address in memory.
DMA

Since the speed of devices is far below the speed of processors, there needs
to be some way to avoid making the CPU wait around for data from devices.

Direct Memory Access (DMA) is a method of transferring data directly

between a peripheral and system RAM. The driver can setup a device to do
a DMA transfer by giving it the area of RAM to put its data into. It can then
start the DMA transfer and allow the CPU to continue with other tasks.

Once the device is finished, it will raise an interrupt and signal to the driver
the transfer is complete. From this time the data from the device (say a file
from a disk, or frames from a video capture card) is in memory and ready
to be used.

Other Buses

Other buses connect between the PCI bus and external devices.

USB

From an operating system point of view, a USB device is a group of end-

points grouped together into an interface. An end-point can be
either in or out and hence transfers data in one direction only. End-points
can have a number of different types:

• Control end-points are for configuring the device, etc.

• Interrupt end-points are for transferring small amounts of data. They
have higher priority.
• Bulk end-points, which transfer large amounts of data but do not get
guaranteed time constraints.
• Isochronous transfers are high-priority real-time transfers, but if they
are missed, they are not re-tried. This is for streaming data like video
or audio where there is no point sending data again.

There can be many interfaces (made of multiple end-points) and interfaces

are grouped into configurations. However, most devices only have a single
configuration.
MICROPROCESSOR OPERATION

Microprocessor performs primarily four operations.

1. Memory Read: Reads data from memory.
2. Memory Write: Writes data into memory.
3. I/O read: Accepts data from input devices.
4. I/O Write: Sends data to output devices.

All these operations are part of the communication process between the
Microprocessor and peripheral devices (including memory). To
communicate with a peripheral (or a memory location), the Microprocessor
needs to perform the following steps:

Step 1 : Identify the peripheral or the memory location (with its address).
Step 2 : Transfer data
Step 3 : Provide timing or synchronization signals.

The internal operations microprocessor can perform are:

1. Store bits data (depending on the microprocessor).

2. Perform arithmetic and logical operations.
3. Test for conditions.
4. Sequence the execution of instructions.

5. Store data temporarily during execution in the defined R/W memory

locations called the stack.

To perform these operations, the microprocessor requires registers, an

arithmetic logic unit (ALU) and control logic, and internal buses (path for
information flow).

To illustrate further on microprocessor operations, we will consider

specifically 8085 microprocessor.

The architecture of.8085 is shown in figure given below. The internal

architecture of 8085 includes the ALU, timing and control unit, instruction
register and decoder, register array, interrupt control and serial I/O control.

The ALU performs the arithmetic and logical operations. The operations
performed by ALU of 8085 are addition, subtraction, increment, decrement,
logical AND, OR, EXCLUIVE -OR, compare, complement and left / right shift.
The accumulator and temporary register are used to hold the data during
an arithmetic / logical operation. After an operation the result is stored in the
accumulator and the flags are set or reset according to the result of the
operation.

Registers

The 8085 has six general - purpose registers to perform the first operation
listed above, that is, to store 8-bit data during a program execution. These
registers are identified as B, C, E, H, and L. They can be combined as register
pairs - BC, DE, and HL - to perform some 16-bit operation.

1. Accumulator

The accumulator is an 8-bit register that is part of the arithmetic logic unit
(ALU). This register is used to store 8-bit data and to perform arithmetic and
logical operations. The result of an operation is stored in the accumulator.
The accumulator is also identified as register A.
2. Flags

The ALU includes five flip-flops that are set or reset according to data
conditions in the accumulator and other registers. The microprocessor uses
them to perform the third operation; namely testing for data conditions.

The bit position of the flip flop in flag register is:

All of the three flip flops set and reset according to the stored result in the
accumulator. For example, after an addition of two numbers, if the result in
the accumulator is larger than 8-bit, the flip-flop indicates a carry by setting
CY flag to 1. When an arithmetic operation results in zero, Z flag is set to 1. The
S flag is just a copy of the bit D7 of the accumulator. A negative number has
a 1 in bit D7 and a positive number has a 0 in 2’s complement representation.
The AC flag is set to 1, when a carry result from bit D3 passes to bit D4. The P
flag is set to 1, when the result in accumulator contains even number of 1s.
3. Stack Pointer (SP):

The stack pointer SP, holds the address of the stack top. The stack is a
sequence of RAM memory locations defined by the programmer. The stack
is used to save the content of registers during the execution of a program.

4. Program Counter (PC):

The program counter (PC) keeps track of program execution. To execute a

program the starting address of the program is loaded in program counter.
The PC sends out an address to fetch a byte of instruction from memory and
increment its content automatically. Hence, when a byte of instruction is
fetched, the PC holds the address of the next byte of the instruction or next
instruction.

Timing and Control Unit

It provides timing and control signal to the microprocessor to perform the

various operation. It has three control signals that It uses to control all
external and internal circuits. It operates with reference to clock signal nd
synchronizes all the data transfers.

There are three control signals:

1.ALE-Address Latch Enable, It provides control signal to synchronize the

components of microprocessor.
2.RD- This is active low used for reading operation.
3.WR-This is active low used for writing operation.
There are three status signals used in microprocessor S0, S1 and IO/M. It
changes its status according the provided input to these pins.

Serial Input Output Control

This unit contains only two pins. This unit is used for serial data
communication.

Interrupt Unit

This unit has 6 interrupt pins. Generally, an external hardware is connected

to these pins. These pins provide interrupt signal sent by external hardware
to microprocessor and microprocessor sends acknowledgement for
receiving the interrupt signal. The INTA is used for the acknowledgement.