vss | | [| ae TECO) Sixth Semester Hts : AM Semester BEL Degree Examination, dane/tuty 2024 VLSI Design and Testi Time: 3 hrs, Mas. Marks: 100 Note: myer any RIE. PU questions, choosing ONE full question from each moutute, . . Modules 1 & Skate Moore's law, elaborate with staph b. Derive the expression tir dian eutrent it tinear aan saturation regions, Explain the fotlowing non-ideal charaeteristies 1) Body effect ii) Channet length modulation (1 Marte (QO Marky (00 Mtr) & = or Explain working of AMOS enhancement mode tr relevant equations, NW inverter circuit and exp nv the schematic of )ESA¥BC ii) F=ARYC msistor operation with neat sketehes and (08 turks) DC transtee charaeteristies, (OX Marks) (04 Darks) Explain CMOS fabrication proces 0 Narky) With relevant equations explain transient response of CMOS inverter, (WS Marks) With neat diagrams explain layout design rules, (WS Marks) with necessary di OR Dray the stick diagram and layout of three input NAND gate. (06 Marks) Find maximum and minimunr rise time and fall time delays of two input NAND gate (06 Marks) Estimate the minimum delay of the path from A to B in Fig.Q.4(e) and choose transistor zes to achieve this delay, ‘The initial NAND2 gate may present a load of 8A of transistor width on the input and the output load is equivalent to 45A of transistor width. "4 EG) (O8 Marks) Modute-3 Explain the operation of three transistor DRAM cell with necessary timing ingr erky Draw the structure of NAND flash memory cell and explain the operation. (06 Marks) Explain ferroelectric RAM with necessary diagrams. (06 Marks) 1of210 ve oe oP 21 OR arams (ox lain read and write operations of SRAM cell with necessary diagrams foes Explain read an a wee : hhat is row decoder? Explain with an examp! / cel Explain data programming and erasing methods of flash memory. Moi le-4 or Briefly explain different types of faults in digital circuits. ence with respect to Consider the logic circuit shown in Fig.Q.7(b) find Boolean difference with respect to , al tol F % ap Fig.Q.7(b) , 06; Explain detection of multiple faults in combinational logic circuits. (06; A OR With neat sketch, explain path oriented decision making algorithm, (10 Fora give logic network determine tests for checking all single node faults Fig. Q.8(4 (oy * Fig.Q.8(b) Module-§ }) Controllability ii) Observabi ity. Briefly explain : Con ; (06: Explain adhoc design rules for improving testability. (06 With neat diagram explain partial sean, (On ; OR List LSSD design rules, Qo Explain test generation based on functional fault models, acI8EC72 Seventh Seme: emester B.E. Degree Examination, June/July 2024 VLSI Design Max. Marks: 100 Ans " 1 ic er any FIVE full questions, choosing ONE full question from each module Define Moore’s law. Modutest a the design of a CMOS compound OR-OR-AND invert gate ecciaraad A+B)(C=D). (i) Sketch a transistor level schematic (ii) Sketch a stick diagram (ii) Estimate area fi ing Derive the taneferchamcterstcr cf ee acteristics of CMOS Inverter (graphical). (08 Marks) - OR Explain all the non-ideal effects in MOS transistor. (io Marks) With neat sketches explain the operation of MOSFET and derive the equation for drain current in all the regions, (1oMarks) Modu! Explain VLSI design flow (Qo Marks) What is scaling? What are types of scaling and write scaling factors for deviee parameters? (Wo Marks) OR Draw the schematic and layout of bso input NAND gate. (06 Marks) Explain layout design rules for wel, transistor rule and metal rules (os Marks) Define terms: (i) Metallization (i) Passivation (iti) Metrology (06 Marks) Modutes3 Explain Elmore delay model (od Mako) De al eflort, Write the logical efforts of common gates do Marky) 4 (FOS) inverter shown in Fig.QS(c), Assume the the delay of the Fanout - of ; tc cess with t= 15 ps. inverter is constnicted in 3 180 nm proc Pee (a7 Marks) 2. Q5(¢ Lof210 a, oP 18EC7, OR What is Ratioed logic? Explain following ratiocd logic circuits (Pseudo nMOS Gi) Ganged CMOS ii) Source follower pull-up logic (22 Ma Explain Cascade Voltage Switch Logic (CVSL). Realize the input AND/NAND sie CVSL. (08 Ma, Module-4 Explain the general structure of ratioed synchronous dynamic circuits. (05 Many With necessary circuit diagram, explain dynamic shift register (ratioless) with enhanceme, load. (08 May, What are the advantages of dynamic CMOS logic and explain the working of dynan, CMOS inverter. (07 Man, OR Write the basic building block ofa CMOS transmission gate dynamic shift register. 1 (04 Mark 2 With generalized circuit diagram, explain domino CMOS logic and using the same real: the following Boolean function: Z = AB + (C+ D)(E+F)+GH (11 Mar With necessary diagram, explain aD flipflop with two phase non-overlapping clocks. Modu With neat circuit diagram, explain full CMOS SRAM cell, Draw the circuit of 3-bit BIST register and explain, Explain the terms: (i) Observability (ji) Fault coverage (ii) Controllability OR With necessary circuit diagram, explain the operation of three transistor DRAM cell. (08. Mat What is a’ fault model? Explain stuck-at model with examples. (07 Mat (05 Mad Explain the logic verification principles. ear_ Bes sea | nth Semester BK, p, ree F Stor BE. Deg be “LITT Seve IGECT2 ixaminath te VLSI Design. lon, Dec.2023/San.2024 Time: 3 hrs, Max. 3 es: 100 hoosing ONE, suitably assumes i ONE full auertdffion cach modute, we * % Note: 1. An , Answer any FIVE, . Missi E full que 2. Missing data a all questions 1 a. Derive ane: , Me Af b. Draw aCe for drain cure Mostule=t AS) c. Imple JOS inverter cifcuit and e nd saturation region Implement 42:1 MUX usis nd explain its D.C. characterist ee using transmission gate. 7 ue Oster CG) (64 Marks) 2 a. Explain the nonfideal | OF the nonfidéal IV effect of MOSFET wit , edultion and'mnpBility degradation MOSFET with respect to CMOS channel lena E; in the cratic C ‘ f BE ¢ operation of nMOS transistor with IV charactersis tee ketch a static) MOS gate computing y= (A+B+C)D : enews ye +O. (04 Marks) = . _*Module-2 Oe Explain es nWell process with necessary diagrams.” (2 Marks) tMeatia BE ifferent types of MOSFET capacitances with necessary diagrams and equations also MOSFET. Capacitancesjin cut off, linear and saturation region” (08 Marks) | oR |y é 4 a. Define scaling. Explain constant field scaling and constant, voltage scaling and why constant voltage scaling_‘s usually preferred over full scaling. =<) (o7 Marks) plain the Lambda based design rules for to metal layers. (06 Marks) (07 Marks) b. With neat diagram, ex cc. Draw the layout for f = BC and estimate the cell area. Sy a) , om V9 : g ¢ Module-3 ¢ logic circuit and calculat e the delay (06 Marks) Acre oe, 5 a. Develop the RC delay model}to compute the delay of th of unit sized inverter driving another unit jn vertex. . give ouput oaet ind tpie for the 3 input NAND gate shown in Fig.Q.5(b) ifthe our b.“ Estimate thar 4 ‘with h identical NAND gates ak At A Fe & pat |=? 3 oy att | 4 ae) f" re) an example. lof? c. Explain evSt with— 4 6 a. Explain: i) Pseudo-nMOS ii) Ganged CMOS. with necessary circuit examples, (64, b. Ifa unit transistor has R = 10K and ¢ = 0:1 ina 65am process, COmPUtE the dM, picoseconds, of the inverter Fig.Q.6(b) with a fan out of h= 4, enh Kad ‘ Fig.Q.6(b) 6. Explain linear delay model compare the logical effort ofthe following gates withthe schematic diagrams: i) 3-input NAND gate ii) 3 input NOR'gate, ond < \ z ‘ Module-4 _ = 7 a. Explain Resettable latches dnd flipflops using CMOS transmission gate. b. ¢ (O6n,, 4 Explain Dynamic logic 6 gE Consider the two nFET ‘chain in Fig.Q.7(c),,The-power supply is set to a valu d Vpp = 3.3V and the nFET threshold voltage is Vr» = 0.55V. Find the output voltage y 2 the right side ofthe, chain for the following’values: i) Viy = 2.9V iii) Vin = 1.4V Oniv) Vin= 3.1V. OD ow ot fea ~s) Pe Ven OR — | ind waveforms, . (06M ivecthe gate of another-nFET as shown in FigQ, Assumé:that Vpp 5 3.3V and Vin F.0-5V. Find the output-Voltage Vou when the ig voltagés‘are at following values: *)\° i i) Vi=3.3Vand Vy»=3.3V ¢ ii) Vy=2.0V and Vy =2. 1 ‘or equations written eg, 4248 50, Am 8B oa Expleig yulsed latches with schematic a b. The otput of an nFET is used to di Fig. 806), > eX? , (08 Mar ¢. Explain Domino logic. , (06 Ma Oxy? » Module-5 9 a. With neat schematic diagram explain the operation of Full CMOS static RAM cell. Cy (10 Ma b. Explain the different fault models. (10 Ma _?¢ OR 10 a. With neat schematic)diagram explain the operation of three transistor DRAM cell. a (io Me b. Write short notes on: i) Built in Self Test ii) Scan Design. (10 Ms keke 2o0f2