19EEE357– Embedded
Systems Design
Sivraj P, Asst. Professor,
Dept. of EEE, Amrita School of Engineering
Amrita Vishwa Vidyapeetham
Embedded System - Recap
• Unit 1
―Embedded System - Components, Characteristics, Classification, Design & Applications
―Overview of Processors, Types, Architectures, ARM Architecture
―Cortex-M3 - Architecture, Programmer’s model, Instruction set & Addressing modes
• Unit 3
―Real Time Systems, RTOS – Introduction, Need, RTOS vs GPOS, Tasks – Structure,
States and Transitions, Types, concepts, RTOS – Types, Architecture, Kernel Services
(functionalities), Task Management – Scheduling, Inter task communication and
Synchronization, Timer Management, Memory Management, Interrupt & Exception
Handling, Selection of RTOS, Standards and Benchmarking, Commercial and Open
Source RTOSes
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16 bit Data Processing Instructions
Image Courtesy: Joseph Yu, “The Definitive Guide to ARM Cortex-M3”, Second Edition, Newness, 2009.
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32 bit Data Processing Instructions
Image Courtesy: Joseph Yu, “The Definitive Guide to ARM Cortex-M3”, Second Edition, Newness, 2009.
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32 bit Data Processing Instructions
Image Courtesy: Joseph Yu, “The Definitive Guide to ARM Cortex-M3”, Second Edition, Newness, 2009.
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ADD, ADC, SUB, SBC, and RSB
• op{S}{cond} {Rd,} Rn, Operand2;
• op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
• ADD - adds the value of Operand2 or imm12 to the value in Rn
• ADC - adds the values in Rn and Operand2, together with the carry flag
• SUB - subtracts the value of Operand2 or imm12 from the value in Rn
• SBC - subtracts the value of Operand2 from the value in Rn
―If the carry flag is clear, the result is reduced by one
• RSB - subtracts the value in Rn from the value of Operand2
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AND, ORR, EOR, BIC, and ORN
• op{S}{cond} {Rd,} Rn, Operand2 ;
• AND, EOR, ORR - bitwise AND, Exclusive OR, and OR operations
• BIC - AND operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2
• ORN - OR operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2
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ASR, LSL, LSR, ROR, and RRX
• op{S}{cond} Rd, Rm, Rs ;
• op{S}{cond} Rd, Rm, #n ;
• RRX{S}{cond} Rd, Rm ;
• ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or
right by the number of places specified by constant n or register Rs.
• RRX moves the bits in register Rm to the right by 1.
• n Specifies the shift length.
―ASR - 1 to 32; LSL - 0 to 31; LSR - 1 to 32; ROR - 1 to 31
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CLZ
• CLZ{cond} Rd, Rm ;
• CLZ - counts the number of leading zeroes in the value in Rm and
returns the result in Rd
―Result value is 32 if no bits are set and zero if bit[31] is set
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CMP and CMN
• CMP{cond} Rn, Operand2 ;
• CMN{cond} Rn, Operand2 ;
• CMP - subtracts the value of Operand2 from the value in Rn
• CMN - adds the value of Operand2 to the value in Rn
• Update the condition flags on the result, but the result is discarded
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MOV, MVN and MOVT
• MOV{S}{cond} Rd, Operand2 ;
• MOV{cond} Rd, #imm16 ;
• MVN{S}{cond} Rd, Operand2 ;
• MOVT{cond} Rd, #imm16 ;
• MOV - copies the value of Operand2 or #imm16 into Rd
• MVN - performs a bitwise logical NOT on the value of Operand2, and
places the result into Rd.
• MOVT - writes #imm16, to the top halfword, Rd[31:16]
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REV, REV16, REVSH, and RBIT
• op{cond} Rd, Rn ;
• REV - Converts 32-bit big-endian data into little-endian data or vice versa
• REV16 - Converts 16-bit big-endian data into little-endian or vice versa
• REVSH - Converts either:
―16-bit signed big-endian data into 32-bit signed little-endian data
―16-bit signed little-endian data into 32-bit signed big-endian data
• RBIT - Reverse bit order of value in Rn and write the result to Rd
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TST and TEQ
• TST{cond} Rn, Operand2 ;
• TEQ{cond} Rn, Operand2 ;
• TST - bitwise AND operation on the value in Rn and Operand2
• TEQ - bitwise Exclusive OR operation on the value in Rn and Operand2
• Update the condition flags based on the result, but do not write the
result to any register
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MUL, MLA, and MLS
• MUL{S}{cond} {Rd,} Rn, Rm ;
• MLA{cond} Rd, Rn, Rm, Ra ;
• MLS{cond} Rd, Rn, Rm, Ra ;
• MUL - multiplies the values from Rn and Rm, and places the least significant
32 bits of the result in Rd
• MLA - multiplies the values from Rn and Rm, adds the value from Ra, and
places the least significant 32 bits of the result in Rd
• MLS - multiplies the values from Rn and Rm, subtracts the product from the
value from Ra, and places the least significant 32 bits of the result in Rd
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UMULL, UMLAL, SMULL, and SMLAL
• op{cond} RdLo, RdHi, Rn, Rm ;
• UMULL - multiplies the unsigned integers from Rn and Rm and places the least
significant 32 bits of the result in RdLo, and the most significant 32 bits of the result
in RdHi
• UMLAL - multiplies the unsigned integers from Rn and Rm, adds the 64-bit result to
the 64-bit unsigned integer in RdHi and RdLo, and writes the result to RdHi and RdLo
• SMULL - multiplies the signed integers from Rn and Rm and places the least
significant 32 bits of the result in RdLo, and the most significant 32 bits of the result
in RdHi
• SMLAL - multiplies the signed integers from Rn and Rm, adds the 64-bit result to the
64-bit signed integer in RdHi and RdLo, and writes the result back to RdHi and RdLo
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SDIV and UDIV
• SDIV{cond} {Rd,} Rn, Rm ;
• UDIV{cond} {Rd,} Rn, Rm ;
• SDIV performs a signed integer division of the value in Rn by the
value in Rm
• UDIV performs an unsigned integer division of the value in Rn by the
value in Rm
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SSAT and USAT
• op{cond} Rd, #n, Rm {, shift #s} ;
• n specifies the bit position to saturate to:
―n ranges from 1 to 32 for SSAT ; and 0 to 31 for USAT
• shift #s Is an optional shift applied to Rm before saturating
―ASR #s where s is in the range 1 to 31; LSL #s where s is in the range 0 to 31
• SSAT - applies the specified shift,
―saturates to the signed range −2n–1 ≤ x ≤ 2n–1−1
• USAT - applies the specified shift
―saturates to the unsigned range 0 ≤ x ≤ 2n−1
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BFC and BFI
• BFC{cond} Rd, #lsb, #width ;
• BFI{cond} Rd, Rn, #lsb, #width ;
• lsb - Specifies the position of the least significant bit of the bitfield. lsb
must be in the range 0 to 31
• width - Specifies the width of the bitfield and must be in the range 1 to
32−lsb
• BFC clears width bits in Rd, starting at the low bit position lsb
• BFI replaces width bits in Rd starting at the low bit position lsb, with
width bits from Rn starting at bit[0]
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SBFX and UBFX
• SBFX{cond} Rd, Rn, #lsb, #width ;
• UBFX{cond} Rd, Rn, #lsb, #width ;
• lsb - Specifies the position of the least significant bit of the bitfield. lsb must be
in the range 0 to 31
• width - Specifies the width of the bitfield and must be in the range 1 to 32−lsb
• SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes
the result to the destination register
• UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes
the result to the destination register
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SXT and UXT
• SXTextend{cond} {Rd,} Rm {, ROR #n} ;
• UXTextend{cond} {Rd}, Rm {, ROR #n} ;
• extend - B/H
• #n - #8/16/24 Value from Rm is rotated right 8/16/24 bits
• Extends an 8-bit/16-bit value to a 32-bit value
―SXTB extracts bits[7:0] and sign extends to 32 bits
―UXTB extracts bits[7:0] and zero extends to 32 bits
―SXTH extracts bits[15:0] and sign extends to 32 bits
―UXTH extracts bits[15:0] and zero extends to 32 bits
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ADR
• ADR{cond} Rd, label ;
• label is a PC-relative expression
• ADR generates an address by adding an immediate value to the PC, and
writes the result to the destination register
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Thank You…
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