5/13/2025

EEE 4877 – Analog

Integrated Electronics

Summer Semester 2023 – 24 A.Y.

Lecture 2
MOS Small Signal Model & Layout

Small Signal Transistor Model

• The small-signal model is an approximation of the large-signal behavior around a fixed operating
point, used when signal variations are minor. It simplifies complex nonlinear MOSFET equations,
making it suitable for most analog circuit analyses, especially when the transistor is biased in the
saturation region.

• The main component of the small-signal model is a voltage-controlled current source, gmvGS,
which captures how small variations in gate-source voltage influence the drain current. This
reflects the intrinsic gain capability of the device.

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Small Signal Transistor Model : Adding ro

• Additional effects like channel-length modulation are accounted for by introducing an output
resistance ro, which models the dependency of the drain current on drain-source voltage. This
element becomes crucial in determining parameters like voltage gain.

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Small Signal Transistor Model : Adding gmb

• The bulk or body terminal also affects the small-signal behavior, since the bulk voltage alters the
threshold voltage and thereby the gate overdrive. This is modeled using a second current source
gmbvBS, treating the bulk as a secondary gate input.

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MOS Device Capacitance

In a MOSFET, capacitances exist between each pair of its four terminals, and their values vary with the
transistor's biasing conditions. Based on the device's physical structure, the key capacitances are:

1. Oxide Capacitance (C1):

• Exists between the gate and the channel.

• Given by C1 = WLCox, where W is the channel width, L is the channel length, and Cox is the oxide capacitance per unit area.

2. Depletion Capacitance (C₂):

• Between the channel and the substrate.

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MOS Device Capacitance

3. Overlap Capacitance (C3 and C4):
• Between the gate and the source/drain regions due to overlap of the gate poly.
• Influenced by fringing electric fields, so cannot be simplified as WLDCox.
• More accurately calculated and usually described by overlap capacitance per unit width, denoted
as Cov (unit – F/m)

4. Junction Capacitances:
• Occur between the source/drain and the substrate.
• Composed of two parts.
– Bottom-plate capacitance (Cj): related to the area at the base of the junction. Measured as
capacitance per unit area. (unit – F/m2)
– Sidewall capacitance (Cjsw): associated with the perimeter of the junction. Measured as
capacitance per unit length. (unit – F/m)
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MOS Device Capacitance With VGS Variation

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Example 1
Sketch the Gate-Source and Gate-Drain capacitances of M1 in the following Figure as Vx varies from zero to 3 V.
Assume VTH = 0.6V and 𝛾 = 𝜆 = 0.

Solution:

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Complete MOS Small Signal Transistor Model

with capacitance

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MOS Device Layout

The layout of a MOSFET depends on both circuit requirements (like
W/L ratio to set transconductance and other circuit parameters &
properties) and fabrication technology’s design rules (such as minimum
channel length L dictated by the process).

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MOS Device Layout

• A MOSFET consists of:
o Gate (polysilicon), which slightly overextends the channel for accurate edge
definition.
o Source and Drain regions, connected to metal (aluminum) wires through
contact windows which serve as interconnects with low resistance and
capacitance. To accomplish this, one or more "contact windows" must be
opened in each region, filled with metal, and connected to the upper metal
wires.

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MOS Device Layout

The source and drain junctions play an important role in the
performance. To minimize the capacitance of S and D –
o The source and drain junction areas should be minimized to reduce parasitic
capacitance.
o One dimension of the junction is 𝑊, the other is determined by design rules
to allow proper contact windows.

Bird’s eye view

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Example 2
Draw the layout of the circuit shown in the following figure.

Solution:

Noting that M1 and M2 share the same S/D junctions at node C and M2 and M3 also do so at node N.
Connecting the remaining terminals. we obtain the layout in figure above. Note that the gate polysilicon of M3
can not be directly tied to the source material of M1, thus, requiring a metal interconnect.

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Example 3
Draw the circuit diagram and calculate the source and drain junction capacitances
of the two structures shown in the following figure.
Solution:

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Example 4
Sketch gm and gmb of M1 in the figure aside as a function of the bias current I1.

Solution:

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Acknowledgement

Some parts of this slide is taken from Chapter 2, Design of Analog CMOS Integrated Circuits,
McGraw Hill International Edition 2001 by Behzad Razavi

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