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HCL Interview Questions

The document outlines a comprehensive interview process for a position at HCL Tech, detailing various stages including recruiter rounds, initial technical interviews, and multiple panel discussions. Each section covers specific topics related to physical design, synthesis, timing closure, and power management, along with common questions that candidates may encounter. The structure emphasizes both theoretical knowledge and practical applications in the field of electronic design automation.

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apoorva
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143 views2 pages

HCL Interview Questions

The document outlines a comprehensive interview process for a position at HCL Tech, detailing various stages including recruiter rounds, initial technical interviews, and multiple panel discussions. Each section covers specific topics related to physical design, synthesis, timing closure, and power management, along with common questions that candidates may encounter. The structure emphasizes both theoretical knowledge and practical applications in the field of electronic design automation.

Uploaded by

apoorva
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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𝐑𝐞𝐜𝐫𝐮𝐢𝐭𝐞𝐫 𝐑𝐨𝐮𝐧𝐝:

1. walk through your resume


2. physical design projects?
3. tools used?
4. full flow exposure?
5. preferred domains?
6. relocation & visa?
7. why HCL Tech?

𝐈𝐧𝐢𝐭𝐢𝐚𝐥 𝐓𝐞𝐜𝐡𝐧𝐢𝐜𝐚𝐥 𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 (𝐁𝐚𝐬𝐢𝐜𝐬):

1. what is STA?
2. setup/hold time violation?
3. what is OCV?
4. clock reconvergence pessimism?
5. LVT vs HVT cells?
6. what is IR drop?
7. antenna effect?
8. what is EM?
9. fixing congestion?
10. what is CDC?
11. skew vs jitter?
12. glitch handling?

𝐏𝐚𝐧𝐞𝐥 𝟏: 𝐒𝐓𝐀 𝐚𝐧𝐝 𝐒𝐜𝐫𝐢𝐩𝐭𝐢𝐧𝐠:

1. what is CRPR?
2. fixing crosstalk?
3. delay calc methods?
4. types of SDC constraints?
5. tcl to extract top 10 critical paths?
6. what is max\_transition?
7. python reusable script example?
8. false path in SDC?
9. early vs late mode?

𝐏𝐚𝐧𝐞𝐥 𝟐: 𝐒𝐲𝐧𝐭𝐡𝐞𝐬𝐢𝐬, 𝐃𝐅𝐓, 𝐌𝐞𝐦𝐨𝐫𝐲:

1. combinational vs sequential?
2. physical-aware synthesis?
3. floorplan effect on synthesis?
4. what is scan chain?
5. how is scan reordered?
6. SRAM vs regfile?
7. shift register use?
8. logic vs memory BIST?
9. ATPG use cases?
10. what is scan compression?

𝐏𝐚𝐧𝐞𝐥 𝟑: 𝐅𝐥𝐨𝐨𝐫𝐩𝐥𝐚𝐧 𝐭𝐨 𝐑𝐨𝐮𝐭𝐞:

1. floorplan steps?
2. macro placement tips?
3. halo vs blockage?
4. row utilization formula?
5. causes of congestion?
6. pin access issues?
7. global vs detailed route?
8. routing DRC examples?
9. tap cell?
10. abutment cell?
11. IR-aware floorplan?

𝐏𝐚𝐧𝐞𝐥 𝟒: 𝐂𝐥𝐨𝐜𝐤 𝐓𝐫𝐞𝐞 𝐒𝐲𝐧𝐭𝐡𝐞𝐬𝐢𝐬 (𝐂𝐓𝐒):

1. CTS flow steps?


2. latency vs skew?
3. useful skew use?
4. clock power reduction?
5. CTS in multiple domains?
6. clock gating techniques?
7. CTS-aware placement?
8. H-tree vs balanced tree?
9. what is clock mesh?

𝐏𝐚𝐧𝐞𝐥 𝟓: 𝐓𝐢𝐦𝐢𝐧𝐠 𝐂𝐥𝐨𝐬𝐮𝐫𝐞 𝐚𝐧𝐝 𝐌𝐂𝐌𝐌:

what is MCMM?
setup vs hold ECOs?
SI-aware timing closure?
derating vs margin?
path grouping?
clock uncertainty types?
mode merging?
buffer insertion vs resizing?
timing borrowing?

𝐏𝐚𝐧𝐞𝐥 𝟔: 𝐒𝐢𝐠𝐧𝐨𝐟𝐟 𝐚𝐧𝐝 𝐏𝐨𝐰𝐞𝐫:

1. Dynamic vs leakage power?


2. fixing IR drop?
3. metal fill purpose?
4 EM rules?
5. common DRC errors?
6. LVS check?
7. filler cells?
8. open/short fixes?
9. decap cells?
10. redundant via?

𝐄𝐱𝐭𝐫𝐚 𝐂𝐨𝐦𝐦𝐨𝐧 𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧𝐬:

what is cross-talk delay?


cell delay vs net delay?
RC extraction?
double patterning?
multi-Vt opt?
timing budgeting?
failing path debug steps?
what is a glitch?
process corner effect?
retiming logic?
dummy metal purpose?

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