BASICS OF

MEMORY DESIGN

Author: Ashish Verma

Basics of Memory Design: A 7-Day Journey

Author: Ashish Verma

July 13, 2025

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Contents

1 Memory Hierarchy 5
1.1 Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Levels of Memory Hierarchy: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 Main Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.4 Secondary Storage (Hard Disks, SSDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.5 Tertiary Storage (Magnetic Tapes, Optical Disks) . . . . . . . . . . . . . . . . . . . . . 6
1.3 Classification Of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Memory Architecture 9
2.1 Generic Memory Array Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Memory is build as 2D Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Memory Cells are Grouped in a Sub-Array . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Row & Column Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.4 How You Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5 Sub-Array Size Among Different Levels In The Memory Hierarchy . . . . . . . . . . . 11
2.2 Memory Cell Size and Equivalent Bit Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 What is Equivalent Bit Area? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Peripheral Circuits: Decoder, MUX, and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Row Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Column Decoder and MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 Transmission Gates in MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 Word Line (WL) Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Driver Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 SRAM 15
3.1 About Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 SRAM Cell Array & SRAM Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 6T SRAM Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 SRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 SRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 DRAM 21
4.1 DRAM – Introduction and Properties: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 DRAM Cell Array & DRAM Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.1 DRAM Array Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 DRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 DRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Current Trends in DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5.1 DDR Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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4.5.2 LPDDR (Low Power DDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5.3 HBM (High Bandwidth Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Non-Volatile Memory 27
5.1 Overview of Non-Volatile Memory (NVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.1 Key Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1.2 Common NVM Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.3 How Do They Retain Data? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.4 Typical Read/Write Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 Flash Memory : Theory, Architecture, and Read/Write . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 About Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2 Flash Cell Design – Floating Gate Transistor . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.3 Read Operation In Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.4 Write & Erase Operation In Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . 30

6 NVMs Types and Technologies 33

6.1 Common NVM Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.1 NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.2 NOR Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.3 Comparison of NAND and NOR Flash Memory . . . . . . . . . . . . . . . . . . . . . . 37
6.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.1 Why Was EEPROM Made . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.2 EEPROM Cell Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.3 Architechture of EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.4 Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4 MRAM - Magnetoresistive Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . 39
6.4.1 Basic Cell Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2 MRAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.3 Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7 Redundancy In Memory Design 43

7.1 Redundancy In Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2 Why Redundancy Is Needed? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3 Row and Column Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.1 Row Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.2 Column Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4 How Redundancy Logic Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.1 How Many Redundant Rows/Columns Are Added? . . . . . . . . . . . . . . . . . . . . 45
7.5 What Redundancy Solves? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 1

Memory Hierarchy

1.1 Memory Hierarchy

ˆ A memory hierarchy organizes different types of memory in a computer system based on access speed,
cost, and capacity.
ˆ It aims to balance speed and cost by providing fast but smaller memory closer to the CPU and slower
but larger memory further away.
ˆ This arrangement allows for efficient data access, as frequently used data can be stored in faster memory
levels, while less frequently used data can be stored in slower, larger, and more cost-effective levels.

1.2 Levels of Memory Hierarchy:

Figure 1.1: Memory Hierarchy Diagram (Source: GeeksforGeeks)

1.2.1 CPU Registers

The fastest and smallest memory, directly accessed by the CPU, often used for current operations and data.

1.2.2 Cache Memory

Faster than main memory but smaller in capacity, used to store frequently accessed data and instructions
for faster retrieval by the CPU.

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1.2.3 Main Memory (RAM)

Larger and slower than cache memory, the primary storage for active programs and data, readily accessible
by the CPU.

1.2.4 Secondary Storage (Hard Disks, SSDs)

Slower than main memory but with high capacity, used for storing data that is not currently in use but
needs to be preserved.

1.2.5 Tertiary Storage (Magnetic Tapes, Optical Disks)

The slowest and largest memory, used for archival storage of data that is rarely accessed.

1.3 Classification Of Memory

1.3.1 Volatile Memory
Loses data when power is off.

Why Does It Lose Data When Powered Off ?

ˆData is stored using electrical charges:
In most volatile memory (e.g., DRAM), data is stored in tiny capacitors that hold electrical charges
to represent bits (1s and 0s).
These capacitors constantly leak charge, so they need to be refreshed thousands of times per second
to retain data.
ˆ Power loss = no refresh:
When power is lost, the refresh process stops.
The stored charges quickly dissipate.
As a result, the information is lost.
ˆ No non-electrical backup:
Unlike non-volatile memory (like SSDs or flash drives), there’s no magnetic or physical mechanism to
retain the data without power.

Registers
ˆ Located inside the CPU
ˆ Store immediate data like operands, counters
ˆ Extremely fast (access time in nanoseconds)
ˆ Very limited in size (typically 8–32 general-purpose registers)
Cache Memory
ˆ Small memory between CPU and RAM
ˆ Stores frequently accessed data/instructions
ˆ Types:
L1 Cache: Closest to CPU, smallest and fastest
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L2 Cache: Slightly larger and slower

L3 Cache: Shared among CPU cores, larger but slower

RAM
Used for storing runtime data like variables, stack, heap, buffers.

1. SRAM (Static RAM)

2. DRAM (Dynamic RAM)

1.3.2 Non-Volatile Memory

Retains data without power, common types are:

1. ROM (Pre-programmed)
2. Flash Memory (USB,Microcontrollers)
3. Secondary Memory (HDD,SSD)

How Non-Volatile Memory Retains Data:

Flash Memory (used in SSDs, USB drives):

ˆ Uses floating-gate transistors to store data.
ˆ When you write data, electrons are trapped on an insulated gate.
ˆ These electrons stay in place even after power is removed, representing binary 1s and 0s.
ˆ Data is retained for years without power.
Magnetic Storage (like Hard Disk Drives)
ˆData is stored by magnetizing tiny regions of a spinning disk surface.
ˆ Each region points in a different direction to represent 0 or 1.
ˆ The magnetic state remains stable without any power.
Optical Storage (CDs, DVDs)
ˆData is written by burning microscopic pits into the disc with a laser.
ˆ These physical marks can be read with a laser, even after power loss.
ˆ Since the pits are physical, the data stays indefinitely unless damaged.
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Chapter 2

Memory Architecture

2.1 Generic Memory Array Diagram

Regardless of the types of semiconductor memory technologies, they are commonly organized into memory
sub-arrays. Following figure is the example of a generic memory sub-array diagram with 2D matrix. Let’s
understand:

Figure 2.1:

2.1.1 Memory is build as 2D Array

ˆ Rows are called Word Lines (WLs).
ˆ Columns are called Bit Lines (BLs).
ˆ Each cross-point of a WL and BL is a memory cell (this could be an SRAM, DRAM, Flash, etc.).
So you can imagine a grid:
ˆ If you activate a row (WL), you can access all the cells in that row.
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ˆ Each column line (BL) connects cells vertically.

2.1.2 Memory Cells are Grouped in a Sub-Array
ˆ Instead of one large array, the memory is broken into sub-arrays for better management and faster
access.
ˆ A sub-array = small block of memory cells, typically something like 64Ö64, 128Ö128, etc.
2.1.3 Row & Column Decoders
ˆ Row decoder: Selects one row (WL) out of 2 total rows using M address bits.
M

ˆ Column decoder: Selects one group out of 2 column groups using N bits via the column multiplexer
N

(MUX),the read sense amplifier, and the write driver.

ˆ One column group contains k columns, and there is no further decoding within one column group thus k
bits are transferred in parallel to the sense amplifier or from the write driver. Hence, the input/output

Ö Ö Ö
(I/O) width from the sub-array is k-bit.
In total, there are 2M rows and k 2N columns; thus, k 2M 2N cells.


Example: Let’s take:
22 =4 column groups.

N=2
23 =8 rows

M=5
K=2 Each column group has 2 columns

So total columns = k Ö2 N
=2 Ö 4 = 8 columns

Figure 2.2:

2.1.4 How You Read Data from Memory

k = number of bits you want to read/write in one access (parallelly)/
It is the I/O width of that column group in the sub-array.
k = 8 represent: 8 bits per column group.

Let say:
You want to read from row 5 (address 101)
You want to read column group 2 (address 10)

That means:
You enable Row 5.
You enable column group 2 (C4, C5 because k=2)
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So you get the 2 bits from (R5,C4) and (R5,C5)

2.1.5 Sub-Array Size Among Different Levels In The Memory Hierarchy

For fast access, the sub-array size is typically small. For instance,
ˆ SRAM sub-array size ranges from 32 Ö 32, 64 Ö 64, 128 Ö 128 to 256 Ö 256 for L1 to L3 caches.
ˆ DRAM sub-array size is moderately sized up (e.g., 512 Ö 512, 1024 Ö 1024).
ˆ On the other hand, for large-capacity storage, NAND Flash’s sub-array size could be as huge as 16k
Ö 64 to 128k Ö 64.

2.2 Memory Cell Size and Equivalent Bit Area

Depending on the specific type of the semiconductor memory technologies, the actual implementation of the
memory cell is different in the generic memory sub-array diagram.
ˆ The SRAM cell typically consists of six logic transistors
ˆ The DRAM cell typically consists of one access transistor and one capacitor.
ˆ The Flash memory cell typically consists of a single floating-gate transistor or charge-trap transistor.
2.2.1 What is Equivalent Bit Area?
ˆ It refers to how much silicon area is needed to store 1 bit.
ˆ Measured in units of F , where F = feature size of the technology (like 22 nm, 14 nm, etc.)
2

ˆ F is the minimum area that a single feature (like a wire or transistor) takes.
2

ˆ Lower F  Higher density  Cheaper memory  More bits in less space.

2

Figure 2.3: Equivalent Bit Area

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Figure 2.4: Memory Cell Composition

Visual Analogy: Think of memory as a parking lot:

SRAM: One car takes 6 spots = lots of space per car (fast but expensive)
DRAM: One car takes 1 spot and a post-it (capacitor)
NAND Flash: One car has 4 passengers (n = 4 bits), and the lot is multilevel

2.3 Peripheral Circuits: Decoder, MUX, and Driver

In a memory array, the memory cells don’t work alone. We need peripheral circuits to:
ˆ Select the right row/column
ˆ Read/write the correct data
ˆ Manage signal strength and timing
What Are Peripheral Circuits?
ˆRow decoder
ˆ Column decoder
ˆ Multiplexer (MUX)
ˆ Wordline (WL) driver
ˆ Sense amplifier and write driver.
Let’s deep dive into this:

2.3.1 Row Decoder

ˆ For decoding the bit address, the digital decoder is used. If the bit address is long(e.g., M > 5 bit),
it is not area-efficient to apply the direct decoding from M-bit to 2M rows. In this case, a two-stage
decoder is used.
ˆ Row decoder converts an M-bit address into one active row (wordline).
ˆ It selects 1 out of 2 rows.
M

ˆ Two-Stage Decoder (Area Optimization):

First stage: decode 4 bits  16 intermediate signals
If M = 8 (for 256 rows), we can do:
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Ö
Second stage: decode remaining 4 bits 16 rows per group
So: 16 16 = 256 rows are addressable.
This reduces wire lengths and transistor count.

Figure 2.5: Two-Stage Decoder

2.3.2 Column Decoder and MUX

The decoder design applies to both row decoding and column decoding.
The column selection needs a MUX that is controlled by the column decoder.
The MUX typically employs transmission gates.
Figure 6 shows an example of a 16-to-1 MUX that is controlled by a 4-to-16 decoder (which could be the
second stage of the two-stage decoder).

Figure 2.6: 16x1 Mux

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2.3.3 Transmission Gates in MUX

MUXes in memory use transmission gates (like analog switches).
Controlled by decoder outputs.
Transistor size is important – it must:
-Allow enough current for writing
-Not degrade the signal while reading

2.3.4 Word Line (WL) Driver

After the row decoder activates a row, WL driver actually drives the wordline.
This is needed because wordlines are long and capacitive (they behave like wires with resistance and
capacitance).

2.3.5 Driver Design Trade-Offs

Figure 7 illustrates a few design options for the WL driver with various optimization goals. In this example,
the lumped WL capacitance is assumed to be 4096 unit capacitance,9 thus the driver could be divided into
stages to trade-off between the latency and the area.

Figure 2.7: Design options for the WL driver with various optimization goals: (a) latency optimized; (b)
area optimized; (c) balance between latency and area.
Chapter 3

SRAM

3.1 About Static Random Access Memory

ˆ ”Static” means data is retained as long as power is supplied, without the need for refreshing.
ˆ “Random access” means that each bit of the data could be read/written independently.
ˆ Used for fast-access, low-latency applications.
ˆ Requires no refresh like DRAM because it uses flip-flop circuits.
ˆ Larger in size.(Low density device)
ˆ There are two kinds of power: Static and Dynamic Power. In SRAM:
Static power consumption = High (Due to leakage in the always-on transistors).
Dynamic power consumption = Low (There’s no refresh as DRAM)
ˆ Commonly used in:
CPU caches (L1, L2, L3)
Register files
On-chip buffers

3.2 SRAM Cell Array & SRAM Cell Design

ˆ In Figure-1 we see the component layout for a 8-location SRAM array where each location holds
6 bits of data.
ˆ The circuitry around the periphery is used to decode addresses and support read and write operations.
ˆ To access the SRAM, we need to provide enough address bits to uniquely specify the location. In this
case we need 3 address bits to select one of the 8 memory locations.
ˆ The address decoder logic sets one of the 8 wordlines (the horizontal wires in the array) high to enable
a particular row (location) for the upcoming access. The remaining wordlines are set low, disabling
the cells they control.
ˆ The active wordline enables each of the SRAM bit cells on the selected row, connecting each cell to a
pair of bit lines (the vertical wires in the array).
ˆ Read Operation: During read operations the bit lines carry the analog signals from the enabled bit
cells to the sense amplifiers, which convert the analog signals to digital data.
ˆ Write Operation: During write operations incoming data is driven onto the bit lines to be stored into
the enabled bit cells.

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Figure 3.1: SRAM Bit Cells (Source:MIT OCW 6.004 Computation Structures)

3.2.1 6T SRAM Cell Design

Figure 3.2: Circuit schematic of the 6T SRAM cell.

ˆ Figure-2 shows the circuit schematic of the commonly used 6-transistor (6T) SRAM cell.
ˆ The core of the 6T cell includes:
– INV1 and INV2: Two cross-coupled inverters l.e Complementary storage nodes.
– N1 and N2: These ate two storage nodes of the SRAM cell, as the data are stored at one
of these two nodes.
– BL and BL (Bit Lines): The storage nodes are connected to BL and BL through two
access transistors, whose gates are controlled by the same wordline (WL).
– WL (Word Line): Controls access to the cell.
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ˆ Figure-3 shows the two stable configurations.

In the top configuration, the cell is storing a 1 bit.
In the bottom configuration, it’s storing a 0 bit.

The cell provides stable storage in the sense that as long as there’s power, the noise immunity of
the inverters will ensure that the logic values will be maintained even if there’s electrical noise on
either inverter input.

Figure 3.3: Bistable element (two stable states), stores a single bit

ˆ If N1 stores “1” with a voltage at the power supply (VDD), then N2 must store “0” with a voltage at
the ground.
ˆ There is only 1-bit information is stored in the 6T cell, and it is typically regarded as being stored at
N1.

3.3 SRAM Read Operation

Assume ”0” at N1 and ”1” at N2.

Figure 3.4: SRAM read operation with major current flow path.

1. The drivers first recharge all the bitlines(BL and BL) to VDD (logical 1 value) and then disconnect,
leaving the bitlines floating at 1.

2. Then the address decoder sets one of the wordlines high, connecting a row of bit cells to their bitlines.
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3. Each cell in the selected row then pulls one of its two bitlines to GND. In this example, it’s the right
bitline that’s pulled low.
N1 = 0 and N2 = 1, BL start discharging and BL stay at high.

4. A small voltage difference (e.g., 100 mV) builds up between BL and BL.

5. Now sense amplifier comes in picture. A sense amplifier compares the two and rapidly drives the output


to logic level:


If BL > BL Output = 1
If BL < BL Output = 0

6. Word Line Deactivation: After sensing is done, WL is pulled low to turn off access transistors.
BL and BL go back to precharge phase for next operation.

Summary: Precharge  Activate WL  Bitline Discharge  Sense Amp Detects ∆V Output

3.4 SRAM Write Operation
Write operations start by driving the bitlines to the appropriate values.
Initially N1 = 0 and N2 = 1.
Change it N1 = 1 and N2 = 0.

Figure 3.5: (a) Principle of the SRAM write operation in the 1st phase that “1” to “0” transition is initiated.
(b) “0” to “1” transition is followed in the 2nd phase.

1. Bit Lines (BL and BL) are driven externally with the value to be written. Write drivers pull BL and
BL to the desired logic levels.

2. Word Line Activation :

The row decoder activates the Word Line (WL) for the target row.
WL goes high, turning ON access transistors.
This connects the internal cell nodes N1 and N2 to BL and BL

3. Cell Overwrite: The strong write drivers force the voltage onto N1 and N2.
If we are writing ‘1’: N1 = 1, N2 = 0
If we are writing ‘0’: N1 = 0, N2 = 1

The previous value stored is overwritten by overpowering the cross-coupled inverter.

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4. Word Line Deactivation: After a short write pulse ( a few ns), WL is pulled low.
Access transistors turn off.
The new value is now latched in the cross-coupled inverter.
5. Bit Line Released: BL and BL are disconnected by disabling the write drivers. They return to the
precharge phase for the next operation.
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Chapter 4

DRAM

4.1 DRAM – Introduction and Properties:

DRAM (Dynamic Random-Access Memory) is a volatile semiconductor memory used for temporary data
storage in most digital systems.
ˆ “Dynamic” refers to this need for periodic refresh to keep the data intact.
ˆ “Random access” means that each bit of the data could be read/written independently.
ˆ 1T1C design : It stores each bit of data using a single capacitor and one access transistor.
ˆ It uses charge-based storage, capacitor leaks charge, must be refreshed periodically (every 64 ms).
When there is Charge in capacitor = 1(High)
When there is NO Charge in capacitor = 0(LOW)
ˆ DRAM is denser, compact, and low-cost, ideal for large memories.
ˆ DRAM is 20-times less area/bit than an SRAM bit cell.
ˆ Static power consumption = Low
Dynamic power consumption = High (Due to refreshing)
ˆ Unlike SRAM, Reads are destruction. Hence after read we need to write data again.
ˆ Commonly used in:
Main RAM in laptops, desktops, servers
Works in modules: DDR4, DDR5
Graphics DRAM (GDDR)
Mobile DRAM (LPDDR)

Figure 4.1: DRAM ( Source : hp.com)

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4.2 DRAM Cell Array & DRAM Cell Design

Figure 4.2: DRAM 1T1C Cell Design

ˆ The basic DRAM memory cell consists of:

1 Transistor (Access switch) : To select which bits will be affected by read and write operations.
1 Capacitor (Storage element) : If the capacitor > threshold, we’re storing a 1 bit, otherwise 0.
ˆ We can increase the capacitance by increasing the dielectric constant of the insulating layer, increasing
the area of the plates, or by decreasing the the distance between the plates.
ˆ The resulting circuit is quite compact: about 20-times less area/bit than an SRAM bit cell.

Figure 4.3: Basic structure of a DRAM cell array (Source : medium.com)

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4.2.1 DRAM Array Architecture

ˆ DRAM is organized in a 2D array:
Rows = Wordlines, Columns = Bitlines.
Each cross-point has a 1T1C cell
ˆ Word Line (WL) : Selects a row (activates access transistor)
Bit Line (BL) : Transfers charge to/from the cell
Sense Amplifier : Detects small voltage change
Row Decoder : Selects 1 of 2M rows
Column Decoder : Selects 1 of 2N columns
Precharge Circuit : Resets BL to VDD/2 before next access

4.3 DRAM Write Operation

DRAM write operations are straightforward: simply turn on the access FET with the wordline and charge
or discharge the storage capacitor through the bitline.
Let say we want to write ’1’

Figure 4.4: DRAM Cell

1. Set Write Data on Bit Line:

Drive Bitline(BL) to VDD ot GND, for writing ’1’, Bit Line is driven to VDD (logic high).


2. Activate Word Line:
Row decoder selects the required row WL goes high.Access transistor (T) turns ON.
Bit Line and Capacitor are now connected.

 
3. Data Stored in Capacitor:

 
If BL = VDD capacitor charges up stores logic ‘1’
If BL = 0 capacitor discharges stores logic ‘0’
This state remains as long as leakage doesn’t drain the capacitor (hence refresh needed).


4. Deactivate Word Line:
WL is pulled low Access transistor turns OFF
Cell is isolated with data stored as charge or no charge
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4.4 DRAM Read Operation

Reads are bit more complicated. We want read the stored data (weathrer it’s charge or no charge) from a
DRAM cell without damaging the rest of the array. But as I said above, READS ARE DESTRUCTIVE.

Figure 4.5: DRAM Cell

1. Precharge Phase:
Bitline (BL) is precharged to VDD/2.
Then the precharge circuitry is disconnected.
This sets a reference voltage so the sense amplifier can detect small deviations
2. Activate Word Line:
The wordline is activated, connecting the storage capacitor of the selected cell to the bitline.
It further cause the charge on the capacitor to be shared with the charge stored by the capacitance of
the bitline.
3. As now capacitor and bitline share charge
If capacitor was discharged, bitline voltage decreases slightly.
If capacitor was charged, bitline voltage increases slightly.
4. Sense amplifiers are used to detect this small voltage change to produce a digital output value.
5. Since reading shares charge with BL, it disturbs the capacitor value, this means that read operations
wipe out the information stored in the bit cell, which must then be rewritten with the detected value
at the end of the read operation.
6. The sense amplifier restores the correct charge back into the cell immediately

4.5 Current Trends in DRAM

4.5.1 DDR Evolution
It transfers data on both rising and falling edges of the clock (hence ”double” data rate).
Used in: Desktops, laptops, servers, game consoles
DDR : Original double-data-rate memory
DDR2 : Better speed, lower voltage than DDR
DDR3 : Higher speed, 8-bit prefetch
DDR4 : Higher density, more banks
DDR5 : Double bandwidth, lower power, ECC
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4.5.2 LPDDR (Low Power DDR)

Optimized version of DDR for mobile and embedded systems.
Focuses on power saving features like:
Deep sleep
Partial array self-refresh
Low standby current

Used in: Smartphones, tablets, IoT devices, AI edge devices

4.5.3 HBM (High Bandwidth Memory)

3D-stacked DRAM technology with Through-Silicon Vias (TSVs).
Offers very high bandwidth and wide interface (e.g., 1024-bit).
Designed for massive parallelism.

Used in: GPUs, AI/ML accelerators, high-end FPGAs

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Chapter 5

Non-Volatile Memory

5.1 Overview of Non-Volatile Memory (NVM)

Non-Volatile Memory (NVM) is a type of memory that retains data even after power is turned off. Unlike
DRAM and SRAM, which are volatile, NVMs store data permanently or semi-permanently using mechanisms
like charge trapping, magnetic state, or resistance change.

5.1.1 Key Characteristics

Property Description
Data Retention Data is retained even without power
Speed Slower than SRAM/DRAM but improving
Durability (Write cycles) Limited for some types (e.g., EEPROM)
Density Higher than SRAM, lower than DRAM in some cases
Use Cases Storage (SSDs), firmware, configuration memory

Table 5.1: Overview of Memory Properties

Figure 5.1: Samsung SSD

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5.1.2 Common NVM Technologies

Type Description Used In

Flash Charge-trapping transistor, block erase SSDs, USB, microcontrollers
EEPROM Electrically erasable byte-wise Microcontroller configuration
NOR Flash Random access, code storage Firmware, bootloaders
NAND Flash Sequential access, higher density SSDs, USB drives
MRAM Magnetic-based, very fast Next-gen embedded memory, caching

Table 5.2: Types of Non-Volatile Memory and Their Applications

5.1.3 How Do They Retain Data?

Retention Mechanism Used In Principle

Charge trapping Flash, EEPROM Electrons trapped in floating gate
Magnetic polarity MRAM Stores bit as magnetization direction
Resistive state ReRAM, PCM Bit stored as high or low resistance

Table 5.3: Retention Mechanisms in Non-Volatile Memories

5.1.4 Typical Read/Write Tradeoffs

About Read Time:
Read access times for NOR flash memories are similar to that of DRAMs, several tens of nanoseconds. Read
times for NAND flash memories are much longer, on the order of 10 microseconds.
About Write Time:
Write times for all types of flash memories are quite long since high voltages have to be used to force electrons
to cross the insulating barrier surrounding the floating gate.

Operation Speed Energy Complexity Notes

Read Fast Low Simple Usually similar to DRAM read
Write Slower High Requires erase/prep (except MRAM)

Table 5.4: Comparison of Read and Write Operations in Non-Volatile Memory

Flash memories can only be written some number of times before the insulating layer is damaged to the
point that the floating gate will no longer reliably store charge.
Currently the number of guaranteed writes varies between 100,000 and 1,000,000. To work around this
limitation, flash chips contain clever address mapping algorithms so that writes to the same address actually
are mapped to different flash cells on each successive write.

5.2 Flash Memory : Theory, Architecture, and Read/Write

5.2.1 About Flash Memories
Flash memory is a type of electrically erasable non-volatile memory that stores data by trapping charge
in a special transistor structure. It can retain data without power, and supports block-based erase/write
operations.It is widely used in:
USB drives, SSDs, Microcontroller program memory (e.g., STM32, ATmega), Memory cards etc.
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5.2.2 Flash Cell Design – Floating Gate Transistor

Flash memory is made out of memory cells which are placed in an array. Every memory cell contains one
floating gate transistor allowing to store at least one bit (Fig. 2).

Single-Level Cells (SLCs), are able to store one bit of information, while Multi-Level Cells (MLCs) allow to
store more than one bit per cell, by choosing between multiple levels of electrical charge in the floating gate
of a cell.

Figure 5.2: Basic scheme of a flash memory cell.

Lets understand the Flash memory cell:

ˆ The floating gate is surrounded by insulating oxide layers.
ˆ In floating gate, charge is stored which remain stable for years.
ˆ These trapped electrons alter the threshold voltage (Vth) of the transistor.
ˆ When no charge stored on the floating gate:
The MOSFET can be turned on, i.e., be made to conduct, by placing a voltage V1 on the gate terminal,
creating an inversion layer that connects the MOSFET’s source and drain terminals.
ˆ When charge is stored on the floating gate:
Then a higher voltage V2 is required to turn on the MOSFET. By setting the gate terminal to a voltage
between V1 and V2, we can determine if the floating gate is charged by testing to see if the MOSFET
is conducting.
ˆ The presence of charge shifts the Vth higher  transistor doesn’t turn ON during read  logic ‘0’
If no charge, normal threshold  transistor turns ON  logic ‘1’
ˆ In fact, if we can measure the current flowing through the MOSFET, we can determine how much
charge is stored on the floating gate, making it possible to store multiple bits of information in one
flash cell by varying the amount of charge on its floating gate.

5.2.3 Read Operation In Flash Memory

Goal: Check whether the floating gate contains charge or not.
1. Apply read voltage (typically 2–5 V) to control gate.
2. Apply low voltage to source, sense current at drain.

  
3. Depending on the threshold voltage (Vth):

   
If no charge in floating gate transistor turns ON current flows logic 1
If charge is present Vth is high transistor stays OFF no current logic 0
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4. Read is non-destructive  floating gate charge remains unchanged.

Example:

Condition Vth (threshold) Output

No charge (erased) ∼1 V 1
Charge present ∼4–6 V 0

Table 5.5: Threshold Voltage and Output Relation in Flash Memory Cells

Figure 5.3: Basic scheme of a flash memory cell.

5.2.4 Write & Erase Operation In Flash Memory

 

Goal of Write: Trap electrons in the floating gate make transistor permanently OFF logic 0.
Goal of Erase: Remove the charge from the floating gate Transistor returns to normal behavior(read=1)

There are two common techniques:

A. Fowler–Nordheim Tunneling
Used in modern NAND Flash
Involves tunneling electrons through thin oxide into floating gate.

B. Hot Electron Injection

Used in NOR Flash
Electrons gain energy due to high drain voltage and are injected into floating gate.

1. Programming (Writing ’0’)

(a) Apply high voltage to control gate
(b) Set source to ground, and drain to intermediate voltage
(c) Electrons gain energy and are forced into the floating gate
(d) Once stored, electrons are trapped inside due to insulating oxide

 You must erase first.

(e) Now the cell is programmed to logic 0.
Flash memory cannot directly write a 1
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2. Erasing (Reset to ’1’)

(a) Apply high voltage to the source or substrate
(b) Apply 0 V to control gate
(c) Electrons tunnel out of the floating gate via Fowler–Nordheim tunneling
(d) Threshold voltage decreases  transistor turns ON  reads as logic 1
(e) Erase is block-wise, Cannot erase individual bits.
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Chapter 6

NVMs Types and Technologies

6.1 Common NVM Technologies

Today we are going to cover commonly used NVMs and their architecture. Let’s have a overview:

Type Description Used In

NAND Flash Sequential access, higher density SSDs, USB drives
NOR Flash Random access, code storage Firmware, bootloaders
EEPROM Electrically erasable byte-wise Microcontroller configuration
MRAM Magnetic-based, very fast Next-gen embedded memory, caching

Table 6.1: Types of Non-Volatile Memory and Their Applications

6.2 Flash Memories

Flash memory is a type of electrically erasable non-volatile memory that stores data by trapping charge in
Floating Gate Transistor. We already saw in previous chapter that how floating gate transistor are construed
and how can we read, erase and write data in it. Now let’s move to its types this section.

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6.2.1 NAND Flash Memory

Figure 6.1: NAND Flash Architecture

It gets its name from the way cells are connected, only if all word lines are pulled high (above the transistors
Vt ), the bit line is pulled low. This resembles a NAND gate.
Unlike NOR, which supports fast random access, NAND is optimized for block-based sequential access,
making it ideal for SSDs, USB drives, SD cards, and mobile storage.

Let’s understand NAND memories:

1. In NAND Flash,Memory Cells are arranged in series:
In Fig-1 shows a string, each transistor in string have a floating gate transistor, i.e., a memory cell.
Each cell stores a bit (or multiple bits with MLC/TLC)
Multiple strings share a bitline and wordlines.
2. Select transistor: We have two:
Ground select transistor (left):
Charge flows only when all transistors in the string are ON (except the selected wordline).
Connects the NAND string to ground (GND)
Controlled by a select line
Bit-line select transistor (right, for reading/writing):
Connects the string to the bitline (used for read/write)
Controlled by another select line
Together, they isolate or connect the string during read/write/erase operations.
3. Word Lines (WL0–WL7):
Control gates of memory cells
One NAND string typically contains 32–128 cells.
During read:
Apply Read voltage(4-5V) to unselected WLs to pass current through them.
Apply low voltage(0-0.5V) to the selected WL.
This lets you sense if floating-gate cell is conducting (i.e., storing ’0’) or blocked (i.e., storing ’1’).
During write:
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Apply high voltage (program voltage) to selected WL.

Apply low voltage (pass voltage) to unselected WLs (just enough to pass).
Access is block-based, not byte-by-byte:
Unlike NOR(which can access individual bytes), NAND can only read/write/erase in large chunks.

4. Bitline Role : Connects to bitline/sense amplifier

During Read:
The bitline at the right end is where the sense amplifier reads current during a read.
During write:


It can also serve as the programming path during write.


BL = 0V cell gets programmed (electrons injected).
BL = High (e.g., 5V) inhibits programming.

Unit Description
Cell Single floating gate transistor
Page Group of cells (e.g., 2–16 KB)
Block Set of pages (64–512 pages/block)
Plane Collection of blocks
Die One full chip (multiple planes)

Table 6.2: NAND Flash Array Hierarchy

6.2.2 NOR Flash Memory

NOR Flash is a type of non-volatile memory that uses floating gate transistors to store bits and allows
random access at byte-level, making it suitable for code storage and execution.
This flash type is called NOR flash, because it behaves like a NOR gate Fig. 2. If one of the word lines is
brought high, the related floating gate transistor pulls the output bit line low. SLC NOR flash cells are in
their default state logically equivalent to binary 1, because by applying a moderate voltage to the control
gate current will flow.

Figure 6.2: NOR Flash Architecture

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NOR Flash Cell Design

In figure-2, each memory cell is a floating gate MOSFET. Transistors are connected in parallel between the
bitline and ground. Each transistor’s gate is controlled by a dedicated wordline.


How it works?


If any one transistor conducts, current flows read logic ’1’
If all transistors are OFF, no current read logic ’0’

This resembles the behavior of a NOR logic gate.

NOR Flash Architecture

Element Description
Bit Line (BL) Vertical line shared by all transistors in a column
Word Line (WL) Each WL activates one cell in the row
P-type Substrate Channel layer for electron movement
N-well Source/drain diffusion regions
Floating Gate Transistor Traps charge to store bit (0 or 1)

Table 6.3: Description of Memory Cell Components

Bitlines
During read: Sense current at the bit line.


Apply small voltage to BL, source = ground


If current flows cell is erased = 1.
If no current cell is programmed = 0.

During write:
Selected BL (Drain): Apply program voltage (5V) and we have Source: Ground. we want to inject electrons.

WordLines(WL)
During read:
Apply 5Vto selected WL.
Unselected WLs = 0V.
During write:
Selected WL: Apply high voltage
Source: GND
During Erase:
WLs = 0V.
Source = High ( 12V).
BL (drain) = Floating.

The following steps are needed to write or program a NOR flash cell to 0:

1. Applying an elevated voltage to control gate (typically above 5 V)

2. Assuming an NMOS transistor, the channel is now turned on so electrons can flow from the source to
the drain

3. If the source to drain current is sufficiently high, there will be some high energy electrons able to jump
from the channel through the insulating layer into the floating gate. This process is called hot-electron
injection.
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4. Now there is charge trapped in the floating gate and thus the threshold voltage Vt is shifted due to the
partial cancelation of the electric field from the control gate.

6.2.3 Comparison of NAND and NOR Flash Memory

Feature NAND Flash NOR Flash

Cell Connection Series (like a chain) Parallel (like a grid)
Read Access Sequential (page-level) Random (byte-level)
Read Speed Slower Faster
Write (Program) Unit Page (usually 2–8 KB) Byte or Word (1–2 bytes)
Erase Unit Block (typically 128–256 KB) Sector (64–128 KB)
Density Higher (more compact) Lower (larger cell size)
Cost per Bit Lower Higher
Endurance Higher (with wear leveling) Lower (fewer cycles)
Reliability Lower (more bit errors) Higher
Use Cases SSDs, USB drives, memory cards Embedded code (e.g., firmware)
Select Transistors Required at string ends Not used
Write Mechanism Fowler-Nordheim tunneling Hot Electron Injection
Erase Mechanism Block-level FN tunneling Sector-level FN tunneling

Table 6.4: Comparison of NAND and NOR Flash Memory

6.3 EEPROM
EEPROM is a type of non-volatile memory, meaning it retains data even when power is turned off. It can
be electrically erased and reprogrammed, unlike earlier PROMs (Programmable ROMs), which could be
written only once or needed UV light to erase (UV EPROMs).

6.3.1 Why Was EEPROM Made

Before EEPROM:
ROM was fixed (data set at manufacturing).
PROM could be programmed once.
EPROM was erasable but needed UV light (slow and impractical in-circuit).

EEPROM solved these issues:

Byte-level erasing and writing (no need to erase the entire chip).
Electrical erasure = faster and programmable in-system.
Suitable for storing calibration data, configuration, or small firmware patches.

6.3.2 EEPROM Cell Construction

EEPROM cells are also based on floating-gate MOSFETs.A control gate and a floating gate. A thin oxide
layer separating the floating gate from the channel.Source and drain as in normal MOSFETs.
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Figure 6.3: Floating Gate Cell

6.3.3 Architechture of EEPROM

Structure:
ˆ Array of EEPROM cells organized in rows and columns.
ˆ Row = Word Line (WL)  connected to control gates.
ˆ Column = Bit Line (BL)  connected to drains.
ˆ Select transistors allow access to individual cells.
Key Components:
ˆ Row decoder (selects word lines).
ˆ Column decoder / Sense amplifier (reads bit line data).
ˆ Charge pump (generates high voltages for tunneling).
ˆ Control logic for timing and sequencing.

Figure 6.4: Architechture of EEPROM (Credit: Sergei P. Skorobogatov)

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6.3.4 Read and Write Operations

Read:

1. Word line selected.

2. Bit line precharged.

3. Sense amplifier detects if transistor conducts.

4. If floating gate has no charge  transistor conducts = ’1’.

5. If charged  high Vt  no conduction = ’0’.
Write:
1. High voltage applied between control gate and source.

2. Electrons tunnel into floating gate.

3. Cell now stores logic ’0’.

Erase:
1. High voltage in reverse direction.

2. Electrons tunnel out of the floating gate.

3. Cell returns to logic ’1’.

6.4 MRAM - Magnetoresistive Random Access Memory

MRAM was developed to combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash.
Unlike conventional RAM chip technologies, data in MRAM is not stored as electric charge or current flows,
but by magnetic storage elements. Its advantages include:

ˆ Non-volatility (data is not lost when power is off)

ˆ High speed (comparable to SRAM)
ˆ Endurance (can handle many read/write cycles)
ˆ Lower power consumption compared to Flash
It is considered a potential universal memory that could replace DRAM, SRAM, and Flash.
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6.4.1 Basic Cell Structure

Figure 6.5: MRAM Cell Structure

Each MRAM cell consists of:

1. Magnetic Tunnel Junction (MTJ): It is the core storage element.In MTJ, two ferromagnetic layers
separated by a thin insulating tunnel barrier.
ˆ One of the two plates is a permanent magnet set to a particular polarityr(Pinned layer).
ˆ The other layer’s magnetization can be changed (free layer).
2. Bit Line and Word Line: Used to select and access individual cells.

3. Transistor (1T-1MTJ): Controls access to the MTJ during read/write.

4. MTJ Working Principle:

ˆ Parallel orientation of magnetic layers  low resistance (represents 0).
ˆ Antiparallel orientation  high resistance (represents 1)
ˆ This change in resistance is due to the Tunnel Magnetoresistance (TMR) effect.
6.4.2 MRAM Architecture
ˆ Array-based architecture, similar to DRAM or Flash.
ˆ Organized in rows and columns.
ˆ Uses:
– Word lines to activate rows
– Bit lines to read/write to columns
ˆ Additional sense amplifiers to detect resistance (for read operations)
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6.4.3 Read and Write Operations

ˆ Read Operation:
– Activate the word line (transistor ON).
– Pass a small current through the MTJ.
– Measure the resistance.
– Resistance  logical state (0 or 1).
ˆ Write Operation (STT-MRAM type):
– Apply current through the MTJ in one direction or another.
– This spin-polarized current changes the orientation of the free layer:
* One direction aligns it parallel (write 0)
* Opposite direction aligns it antiparallel (write 1)
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Chapter 7

Redundancy In Memory Design

If one street is blocked, do you demolish the whole city?

7.1 Redundancy In Memory Design

In semiconductor memory design, redundancy refers to the inclusion of extra rows, columns, or blocks of
memory cells that can be used to replace faulty ones during manufacturing or later in the field. This helps
avoid discarding an entire memory chip due to minor defects, thereby increasing manufacturing yield and
system reliability.

7.2 Why Redundancy Is Needed?

In manufacturing, it’s extremely hard to fabricate perfect memory arrays:
ˆ Even tiny defects (dust particles, dopant variations) can cause stuck-at faults or open circuits.
ˆ Yield drops when a single faulty bit invalidates the entire chip.
ˆ Instead of discarding, we repair it using redundancy.
Let’s understand how defect affect the memory:
In memory, many contacts are shared: some across rows, some across columns, and some across both. Simi-
lar manufacturing defect at different location can result in a different outcomes. Let’s understand by example:

Figure 7.1: Defects in Memory due to Different Contacts

In above Figure-1,(Credit: Dr Anuj GROVER, IIITD)

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ˆ A failure in Contact No. 1 will result in the failure of one cell : Single bit Failure
ˆ A failure in Contact No. 2 will result in the failure of two cells: Double bit Failure
ˆ A failure in Contact No. 3 will result in the failure of four cells: Quad bit Failure
Hence, similar manufacturing defect at different location can result in a different outcomes.

Any single defect can be corrected by replacing two rows when a failure is observed. If we have two spare
rows, we can fix the issue.

By Built-in Self-Test (BIST), we can identify where is failure.

7.3 Row and Column Redundancy

In large memory arrays, rows and columns are where cells are grouped:
ˆ A row corresponds to a wordline (WL) : a horizontal set of memory cells accessed together.
ˆ A column corresponds to a bitline (BL) : a vertical path used to read/write bits in a given position
across rows.
When defects occur:
ˆIf a wordline (row) has one or more faulty cells  replace it with a redundant row.
ˆ If a bitline (column) is faulty  replace it with a redundant column.
7.3.1 Row Redundancy
Row redundancy replaces a faulty wordline with a spare (redundant) row during or after manufacturing test.
Spare rows are fabricated alongside the normal memory array.
ˆ During testing:
– Faulty row address is detected.
– A fuse or repair register stores this address.
ˆ During operation:
– A comparator checks each incoming row address.
– If a match is found, the address decoder redirects to the redundant row.

7.3.2 Column Redundancy

Column redundancy replaces a faulty bitline (or a set of bits across rows) with a spare column. Spare
columns are added with separate bitlines and sense amps.
ˆ During testing:
– Faulty column address is recorded.
ˆ During operation:
– Column decoder skips the faulty column and activates the redundant one instead.

7.4 How Redundancy Logic Works

ˆ Comparators: Match incoming addresses with known faulty ones.
ˆ Muxes: Switch access to spare rows or columns.
ˆ Fuse boxes or eFuse arrays: Store fault addresses permanently.
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ˆ Redundancy controller: Manages remapping logic at runtime.

Figure 7.2: How Redundancy Works (Credit: Dr Anuj GROVER, IIITD)

7.4.1 How Many Redundant Rows/Columns Are Added?

Designers estimate how many defects are likely per wafer and add redundancy accordingly:

Typical: 1 to 4 rows and columns per 1024 rows/columns

High-reliability designs (automotive, aerospace) may include more redundancy.

7.5 What Redundancy Solves?

ˆ Recover faulty dies by replacing defective rows or columns
ˆ Improve yield (more usable chips per wafer)
ˆ Reduce cost (especially critical in high-volume production)
ˆ Improve long-term reliability (self-repair after burn-in or aging)