Assembly Language for x86 Processors 7th

Edition, Global Edition

Kip Irvine

Chapter 2: x86 Processor

Architecture

Slides prepared by the author and

updated by the course instructor
Revision date: 1/21/2021

(c) Pearson Education, 2015. All rights reserved. You may modify and copy this slide show for your personal use, or for
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 Presentation Outline

❖ Basic Computer Organization

❖ Intel Microprocessors
❖ IA-32 Registers
❖ Instruction Execution Cycle
❖ IA-32 Memory Management
 Basic Computer Organization
❖ Since the 1940's, computers have 3 classic components:
◇ Processor, called also the CPU (Central Processing Unit)
◇ Memory and Storage Devices
◇ I/O Devices
❖ Interconnected with one or more buses
❖ Bus consists of data bus

◇ Data Bus
registers
◇ Address Bus
I/O I/O
Processor
◇ Control Bus
Memory Device Device
(CPU)
#1 #2

ALU CU clock

control bus

address bus
 Processor
❖ Processor consists of
◇ Datapath
▪ ALU
▪ Registers
◇ Control unit
❖ ALU
◇ Performs arithmetic
and logic instructions
❖ Control unit (CU)
◇ Generates the control signals required to execute instructions
❖ Implementation varies from one processor to another
 Clock
❖ Synchronizes Processor and Bus operations
❖ Clock cycle = Clock period = 1 / Clock rate

Cycle 1 Cycle 2 Cycle 3

❖ Clock rate = Clock frequency = Cycles per second

◇1 Hz = 1 cycle/sec 1 KHz = 103 cycles/sec
◇1 MHz = 106 cycles/sec 1 GHz = 109 cycles/sec
◇2 GHz clock has a cycle time = 1/(2×109) = 0.5 nanosecond (ns)

❖ Clock cycles measure the execution of instructions

 Memory
❖ Ordered sequence of bytes
◇ The sequence number is called the memory address

❖ Byte addressable memory

◇ Each byte has a unique address
◇ Supported by almost all processors

❖ Physical address space

◇ Determined by the address bus width
◇ Pentium has a 32-bit address bus
▪ Physical address space = 4GB = 232 bytes
◇ Itanium with a 64-bit address bus can support
▪ Up to 264 bytes of physical address space
Address Space

Address Space is
the set of memory
locations (bytes) that
can be addressed
 Memory Unit
❖ Address Bus ❖ Two Control Signals
◇ Address is placed on the address bus ◇ Read
◇ Address of location to be read/written ◇ Write

❖ Data Bus ◇ Control whether

memory should be
◇ Data is placed on the data bus read or written
 Memory Read and Write Cycles
❖ Read cycle
1. Processor places address on the address bus
2. Processor asserts the memory read control signal
3. Processor waits for memory to place the data on the data bus
4. Processor reads the data from the data bus
5. Processor drops the memory read signal
❖ Write cycle
1. Processor places address on the address bus
2. Processor asserts the memory write control signal
3. Processor places the data on the data bus
4. Wait for memory to store the data (wait states for slow memory)
5. Processor drops the memory write signal
 Reading from Memory
❖ Multiple clock cycles are required
❖ Memory responds much more slowly than the CPU
◇ Address is placed on address bus
◇ Read Line (RD) goes low, indicating that processor wants to read
◇ CPU waits (one or more cycles) for memory to respond
◇ Read Line (RD) goes high, indicating that data is on the data bus
Cycle 1 Cycle 2 Cycle 3 Cycle 4

CLK

Address
ADDR

RD

Data
DATA
 Memory Hierarchy
❖ Registers
◇ Fastest storage elements, stores most frequently used data
◇ General-purpose registers: accessible to the programmer
◇ Special-purpose registers: used internally by the microprocessor
❖ Cache Memory
◇ Fast SRAM that stores recently used instructions and data
◇ Recent processors have 2 levels

ize
registers

rs
❖ Main Memory (DRAM)

low
lle

er
ma
❖ Disk Storage cache memory

co
,s

st
ed

pe
◇ Permanent magnetic main memory

pe

rb
rs
storage for files

yte
he disk storage
hig
 Next ...

❖ Basic Computer Organization

❖ Intel Microprocessors
❖ IA-32 Registers
❖ Instruction Execution Cycle
❖ IA-32 Memory Management
 Intel Microprocessors
❖ Intel introduced the 8086 microprocessor in 1979
❖ 8086, 8087, 8088, and 80186 processors
◇ 16-bit processors with 16-bit registers
◇ 16-bit data bus and 20-bit address bus
▪ Physical address space = 220 bytes = 1 MB
◇ 8088 is a less expensive version of 8086
▪ Uses an 8-bit data bus
◇ 80186 is a faster version of 8086
 Intel 80286 and 80386 Processors
❖ 80286 was introduced in 1982
◇ 24-bit address bus ⇒ 224 bytes = 16 MB address space
◇ Introduced protected mode
▪ Segmentation in protected mode is different from the real mode

❖ 80386 was introduced in 1985

◇ First 32-bit processor with 32-bit general-purpose registers
◇ First processor to define the IA-32 architecture
◇ 32-bit data bus and 32-bit address bus
◇ 232 bytes ⇒ 4 GB address space
◇ Introduced paging, virtual memory, and the flat memory model
▪ Segmentation can be turned off
 Intel 80486 and Pentium Processors
❖ 80486 was introduced 1989
◇ Improved version of Intel 80386
◇ On-chip Floating-Point unit (DX versions)
◇ On-chip unified Instruction/Data Cache (8 KB)
◇ Uses Pipelining: can execute up to 1 instruction per clock cycle

❖ Pentium (80586) was introduced in 1993

◇ Wider 64-bit data bus, but address bus is still 32 bits
◇ Two execution pipelines: U-pipe and V-pipe
▪ Superscalar performance: can execute 2 instructions per clock cycle
◇ Separate 8 KB instruction and 8 KB data caches
◇ MMX instructions (later models) for multimedia applications
 Intel P6 Processor Family
❖ P6 Processor Family: Pentium Pro, Pentium II and III
❖ Pentium Pro was introduced in 1995
◇ Three-way superscalar: can execute 3 instructions per clock cycle
◇ 36-bit address bus ⇒ up to 64 GB of physical address space
◇ Introduced dynamic execution
▪ Out-of-order and speculative execution
◇ Integrates a 256 KB second level L2 cache on-chip
❖ Pentium II was introduced in 1997
◇ Added MMX instructions (already introduced on Pentium MMX)
❖ Pentium III was introduced in 1999
◇ Added SSE instructions and eight new 128-bit XMM registers
 Pentium 4 and Xeon Family
❖ Pentium 4 is a seventh-generation x86 architecture
◇ Introduced in 2000
◇ New micro-architecture design
◇ Very deep instruction pipeline, scaling to very high frequencies
◇ Introduced the SSE2 instruction set (extension to SSE)
▪ Tuned for multimedia and operating on the 128-bit XMM registers

❖ In 2002, Intel introduced Hyper-Threading technology

◇ Allowed 2 programs to run simultaneously, sharing resources

❖ Xeon is Intel's name for its server-class microprocessors

◇ Xeon chips generally have more cache
◇ Support larger multiprocessor configurations
 Next ...

❖ Basic Computer Organization

❖ Intel Microprocessors
❖ IA-32 Registers
❖ Instruction Execution Cycle
❖ IA-32 Memory Management
 Basic Program Execution Registers
❖ Registers are high speed memory inside the CPU
◇ Eight 32-bit general-purpose registers
◇ Six 16-bit segment registers
◇ Processor Status Flags (EFLAGS) and Instruction Pointer (EIP)

32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS
Registers
 General-Purpose Registers
❖ Used primarily for arithmetic and data movement
◇ mov eax, 10 move constant 10 into register eax
❖ Specialized uses of Registers
◇ EAX – Accumulator register
▪ Automatically used by multiplication and division instructions
◇ ECX – Counter register
▪ Automatically used by LOOP instructions
◇ ESP – Stack Pointer register
▪ Used by PUSH and POP instructions, points to top of stack
◇ ESI and EDI – Source Index and Destination Index register
▪ Used by string instructions
◇ EBP – Base Pointer register
▪ Used to reference parameters and local variables on the stack
 Accessing Parts of Registers
❖ EAX, EBX, ECX, and EDX are 32-bit Extended registers
◇ Programmers can access their 16-bit and 8-bit parts
◇ Lower 16-bit of EAX is named AX
◇ AX is further divided into 8 8

AH AL
▪ AL = lower 8 bits 8 bits + 8 bits

▪ AH = upper 8 bits AX 16 bits

❖ ESI, EDI, EBP, ESP have only

16-bit names for lower half EAX 32 bits
 Special-Purpose & Segment Registers
❖ EIP = Extended Instruction Pointer
◇ Contains address of next instruction to be executed
❖ EFLAGS = Extended Flags Register
◇ Contains status and control flags
◇ Each flag is a single binary bit
❖ Six 16-bit Segment Registers
◇ Support segmented memory
◇ Six segments accessible at a time
◇ Segments contain distinct contents
▪ Code
▪ Data
▪ Stack
 EFLAGS Register

❖ Status Flags
◇ Status of arithmetic and logical operations
❖ Control and System flags
◇ Control the CPU operation
❖ Programs can set and clear individual bits in the EFLAGS register
 Status Flags
❖ Carry Flag
◇ Set when unsigned arithmetic result is out of range
❖ Overflow Flag
◇ Set when signed arithmetic result is out of range
❖ Sign Flag
◇ Copy of sign bit, set when result is negative
❖ Zero Flag
◇ Set when result is zero
❖ Auxiliary Carry Flag
◇ Set when there is a carry from bit 3 to bit 4
❖ Parity Flag
◇ Set when parity is even
◇ Least-significant byte in result contains even number of 1s
 Floating-Point, MMX, XMM Registers
❖ Floating-point unit performs high speed FP operations
❖ Eight 80-bit floating-point data registers 80-bit Data Registers
48-bit
◇ ST(0), ST(1), . . . , ST(7) ST(0)
FPU In
◇ Arranged as a stack ST(1)

◇ Used for floating-point arithmetic ST(2) FPU

ST(3)
❖ Eight 64-bit MMX registers
ST(4) 16-bit C
◇ Used with MMX instructions ST(5) T
❖ Eight 128-bit XMM registers ST(6) Co
ST(7) Sta
◇ Used with SSE instructions

Opcode Register
 General-Purpose Registers (Pointer Registers)

The pointer registers are 32-bit EIP, ESP, and EBP registers and corresponding 16-bit right
portions IP, SP, and BP. There are three categories of pointer registers −
•Instruction Pointer (IP) − The 16-bit IP register stores the offset address of the next
instruction to be executed. IP in association with the CS register (as CS:IP) gives the
complete address of the current instruction in the code segment.
•Stack Pointer (SP) − The 16-bit SP register provides the offset value within the program
stack. SP in association with the SS register (SS:SP) refers to be current position of data
or address within the program stack.
•Base Pointer (BP) − The 16-bit BP register mainly helps in referencing the parameter
variables passed to a subroutine. The address in SS register is combined with the offset in
BP to get the location of the parameter. BP can also be combined with DI and SI as base
register for special addressing.
 General-Purpose Registers (Control Registers)

The 32-bit index registers, ESI and EDI, and their 16-bit rightmost portions. SI
and DI, are used for indexed addressing and sometimes used in addition and
subtraction. There are two sets of index pointers −
•Source Index (SI) − It is used as source index for string operations.
•Source index is use as a pointer to the current character being read in a
string instruction
•Destination Index (DI) − It is used as destination index for string operations.
•used as a pointer to the current character being written or compared in a
string instruction.
 Next ...

❖ Basic Computer Organization

❖ Intel Microprocessors
❖ IA-32 Registers
❖ Instruction Execution Cycle
❖ IA-32 Memory Management
 Instruction Execute Cycle

Instruction
Obtain instruction from program storage
Fetch

Instruction
Determine required actions and instruction size
Decode
Infinite Cycle

Operand
Locate and obtain operand data
Fetch

Execute Compute result value and status

Writeback
Deposit results in storage for later use
Result
 Instruction Execution Cycle – cont'd
PC program
❖ Instruction Fetch I1 I2 I3 I4 ...
memory fetch
❖ Instruction Decode op1
op2
read

registers registers
❖ Operand Fetch instruction
I1 register
❖ Execute

decode
❖ Result Writeback

write

write
flags ALU

execute
(output)
 Pipelined Execution
❖ Instruction execution can be divided into stages
❖ Pipelining makes it possible to start an instruction before
completing the execution of previous one

Stages For k stages and n instructions, the

S1 S2 S3 S4 S5 S6 number of required cycles is: k + n – 1
1 I-1
2 I-1
3 No I-1 Stages
4 n-p I-1
Wa ipe S1 S2 S3 S4 S5 S6
Cycles

5
ste line I-1
1 I-1
6 dc de I-1
2 I-2 I-1
7 I-2 loc xe
k c cut

Cycles
3 I-2 I-1
8 I-2
yc ion
9 I-2 les 4 I-2 I-1
10 I-2 5 Pipelined I-2 I-1
11 I-2 6 Execution I-2 I-1
12 I-2 7 I-2
 Next ...

❖ Basic Computer Organization

❖ Intel Microprocessors
❖ IA-32 Registers
❖ Instruction Execution Cycle
❖ IA-32 Memory Management
 Modes of Operation
❖ Real-Address mode (original mode provided by 8086)
◇ Only 1 MB of memory can be addressed, from 0 to FFFFF (hex)
◇ Programs can access any part of main memory
◇ MS-DOS runs in real-address mode
❖ Protected mode (introduced with the 80386 processor)
◇ Each program can address a maximum of 4 GB of memory
◇ The operating system assigns memory to each running program
◇ Programs are prevented from accessing each other’s memory
◇ Native mode used by Windows NT, 2000, XP, and Linux
❖ Virtual 8086 mode
◇ Processor runs in protected mode, and creates a virtual 8086
machine with 1 MB of address space for each running program
 Real Address Mode
❖ A program can access up to six segments at
any time
◇ Code segment
◇ Stack segment
◇ Data segment
◇ Extra segments (up to 3)
❖ Each segment is 64 KB
❖ Logical address
◇ Segment = 16 bits
◇ Offset = 16 bits
❖ Linear (physical) address = 20 bits
 Logical to Linear Address Translation
Linear address = Segment × 10 (hex) + Offset
Example:
segment = A1F0 (hex)
offset = 04C0 (hex)
logical address = A1F0:04C0 (hex)
what is the linear address?

Solution:
A1F00 (add 0 to segment in hex)
+ 04C0 (offset in hex)
A23C0 (20-bit linear address in hex)
 Your turn . . .
What linear address corresponds to logical address
028F:0030?

Solution: 028F0 + 0030 = 02920 (hex)

Always use hexadecimal notation for addresses

What logical address corresponds to the linear address

28F30h?

Many different segment:offset (logical) addresses can

produce the same linear address 28F30h. Examples:
28F3:0000, 28F2:0010, 28F0:0030, 28B0:0430, . . .
 Flat Memory Model
❖ Modern operating systems turn segmentation off
❖ Each program uses one 32-bit linear address space
◇ Up to 232 = 4 GB of memory can be addressed
◇ Segment registers are defined by the operating system
◇ All segments are mapped to the same linear address space

❖ In assembly language, we use .MODEL flat directive

◇ To indicate the Flat memory model

❖ A linear address is also called a virtual address

◇ Operating system maps virtual address onto physical addresses
◇ Using a technique called paging
 Programmer View of Flat Memory
❖ Same base address for all segments Linear address space of
◇ All segments are mapped to the same a program (up to 4 GB)
linear address space 32-bit address
ESI
❖ EIP Register DATA
EDI
◇ Points at next instruction 32-bit address
EIP
❖ ESI and EDI Registers CODE
◇ Contain data addresses 32-bit address
EBP STACK
◇ Used also to index arrays
ESP
❖ ESP and EBP Registers CS
DS Unused
◇ ESP points at top of stack
SS
◇ EBP is used to address parameters and ES
variables on the stack base address = 0
for all segments
 Protected Mode Architecture
❖ Logical address consists of
◇ 16-bit segment selector (CS, SS, DS, ES, FS, GS)
◇ 32-bit offset (EIP, ESP, EBP, ESI ,EDI, EAX, EBX, ECX, EDX)
❖ Segment unit translates logical address to linear address
◇ Using a segment descriptor table
◇ Linear address is 32 bits (called also a virtual address)
❖ Paging unit translates linear address to physical address
◇ Using a page directory and a page table
 Paging
❖ Paging divides the linear address space into …
◇ Fixed-sized blocks called pages, Intel IA-32 uses 4 KB pages
❖ Operating system allocates main memory for pages
◇ Pages can be spread all over main memory
◇ Pages in main memory can belong to different programs
◇ If main memory is full then pages are stored on the hard disk
❖ OS has a Virtual Memory Manager (VMM)
◇ Uses page tables to map the pages of each running program
◇ Manages the loading and unloading of pages
❖ As a program is running, CPU does address translation
❖ Page fault: issued by CPU when page is not in memory
 Paging – cont’d
Main Memory

The operating
system uses ...

linear virtual address

linear virtual address

Page m Page n

space of Program 1

space of Program 2
page tables to ... ...
map the pages
in the linear Page 2 Page 2
virtual address Page 1 Page 1
space onto Page 0 Page 0
main memory
Hard Disk
The operating
Each running Pages that cannot system swaps
program has fit in main memory pages between
its own page are stored on the memory and the
table hard disk hard disk

As a program is running, the processor translates the linear virtual addresses

onto real memory (called also physical) addresses