STM32U545xx

Ultra-low-power Arm® Cortex®-M33 MCU+TrustZone®+FPU,

240 DMIPS, 512 KB flash memory, 274 KB SRAM, crypto
Datasheet - production data

Features
Includes ST state-of-the-art patented
technology LQFP48 (7 x 7 mm) UFQFPN48 WLCSP56 UFBGA64
LQFP64 (10 x 10 mm) (7 x 7 mm) (3.38 x 3.38 mm) (5 x 5 mm)
LQFP100 (14 x 14 mm) WLCSP72 UFBGA100
Ultra-low-power with FlexPowerControl (3.38 x 3.38 mm) (7 x 7 mm)

• 1.71 V to 3.6 V power supply • 651 CoreMark® (4.07 CoreMark®/MHz)

• –40 °C to +85/125 °C temperature range • 464 ULPMark™-CP
• Low-power background-autonomous mode • 125 ULPMark™-PP
(LPBAM): autonomous peripherals with DMA,
functional down to Stop 2 mode • 54 ULPMark™-CM
• VBAT mode: supply for RTC, 32 x 32-bit backup • 137000 SecureMark™-TLS
registers and 2-Kbyte backup SRAM Memories
• 90 nA Shutdown mode (23 wake-up pins) • 512-Kbyte flash memory with ECC, 2 banks
• 200 nA Standby mode (23 wake-up pins) read-while-write, and 100 kcycles
• 370 nA Standby mode with RTC • 274-Kbyte SRAM including up to 64-Kbyte
SRAM with ECC ON
• 1.4 μA Stop 3 mode with 16-Kbyte SRAM
• 1 Octo-SPI memory interface
• 2.2 µA Stop 3 mode with full SRAM
• 3.0 µA Stop 2 mode with 16-Kbyte SRAM Security and cryptography
• 4.6 µA Stop 2 mode with full SRAM • SESIP3 and PSA Level 3 Certified Assurance
• 16.3 μA/MHz Run mode @ 3.3 V Target
• Arm® TrustZone® and securable I/Os,
Core memories and peripherals
• Arm® 32-bit Cortex®-M33 CPU with • Flexible life cycle scheme with RDP and
TrustZone®, MPU, DSP, and FPU password protected debug
• Root of trust thanks to unique boot entry and
ART Accelerator secure hide protection area (HDP)
• 8-Kbyte instruction cache allowing 0-wait-state • Secure firmware installation (SFI) thanks to
execution from flash and external memories: embedded root-secure services (RSS)
up to 160 MHz, 240 DMIPS
• Secure data storage with hardware-unique key
• 4-Kbyte data cache for external memories (HUK)
Power management • Secure firmware upgrade support with TF-M
• Embedded regulator (LDO) and SMPS Product label
step-down converter supporting switch
on-the-fly and voltage scaling

Benchmarks
• 1.5 DMIPS/MHz (Dhrystone 2.1)

May 2025 DS14216 Rev 5 1/307

This is information on a product in full production. www.st.com
 STM32U545xx

• 2 AES coprocessors including one with • Parallel synchronous slave interface

DPA resistance
16- and 4-channel DMA controllers,
• Public key accelerator, DPA resistant
functional in Stop mode
• On-the-fly decryption of Octo-SPI external
memories Graphic features
• HASH hardware accelerator • 1 digital camera interface
• True random number generator, NIST
SP800-90B compliant Mathematical co-processor
• 96-bit unique ID • CORDIC for trigonometric functions
acceleration
• 512-byte OTP (one-time programmable)
• Filter mathematical accelerator (FMAC)
• Active tampers
Up to 20 capacitive sensing channels
Clock management
• Support touch key, linear and rotary touch
• 4 to 50 MHz crystal oscillator sensors
• 32 kHz crystal oscillator for RTC (LSE)
Rich analog peripherals (independent
• Internal 16 MHz factory-trimmed RC (±1%)
supply)
• Internal low-power 32 kHz RC (±5%)
• 14-bit ADC 2.5-Msps with hardware
• 2 internal multispeed 100 kHz to 48 MHz oversampling
oscillators, including one auto-trimmed by LSE
(better than ±0.25% accuracy) • 12-bit ADC 2.5-Msps, with hardware
oversampling, autonomous in Stop 2 mode
• Internal 48 MHz with clock recovery
• 2 12-bit DAC, low-power sample and hold
• 3 PLL for system clock, USB, audio, ADC
• 1 operational amplifier with built-in PGA
General-purpose input/outputs • 1 ultra-low-power comparator
• Up to 82 fast I/Os with interrupt capability most
5V-tolerant and up to 14 I/Os with independent CRC calculation unit
supply down to 1.08 V
Debug
Up to 17 timers and 2 watchdogs
• Development support: serial-wire debug
• 2 16-bit advanced motor-control, 4 32-bit, (SWD), JTAG, Embedded Trace Macrocell™
5 16-bit, 4 low-power 16-bit (available in Stop (ETM)
mode), 2 SysTick timers and 2 watchdogs
• RTC with hardware calendar and calibration ECOPACK2 compliant packages

Up to 19 communication peripherals s

Table 1. Device summary

• 1 USB full-speed selectable host or device Reference Part numbers
controller
STM32U545CE, STM32U545JE,
• 1 SAI (serial-audio interface) STM32U545xx STM32U545NE, STM32U545RE,
STM32U545VE
• 4 I2C FM+(1 Mbit/s), SMBus/PMBus®
• 5 USART/UART/LPUART (SPI, ISO 7816, LIN,
IrDA, modem)
• 3 SPI (+1 with OCTOSPI +2 with USART)
• 1 CAN FD controller
• 1 SDMMC interface
• 1 multi-function digital filter (2 filters) + 1 audio
digital filter with sound-activity detection

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 20
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.2 Additional flash memory protections when TrustZone activated . . . . . . 25
3.4.3 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.9.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9.4 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.9.5 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.9.6 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.13.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.14 Low-power general-purpose inputs/outputs (LPGPIO) . . . . . . . . . . . . . . 48
3.14.1 LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.16 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 49
3.17 General purpose direct memory access controller (GPDMA) . . . . . . . . . 49
3.18 Low-power direct memory access controller (LPDMA) . . . . . . . . . . . . . . 51
3.19 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.19.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 53
3.19.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 53
3.20 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 54
3.21 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.22 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.23 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.23.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.24 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.25 Analog-to-digital converter (ADC1 and ADC4) . . . . . . . . . . . . . . . . . . . . . 56
3.25.1 Analog-to-digital converter 1 (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.25.2 Analog-to-digital converter 4 (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.25.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.25.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.25.5 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.26 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.27 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.28 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.29 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.30 Multi-function digital filter (MDF) and audio digital filter (ADF) . . . . . . . . . 63
3.30.1 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.30.2 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.32 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 67
3.33 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.34 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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3.35 Secure advanced encryption standard hardware accelerator (SAES)

and encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . 69
3.36 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.37 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.38 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.39 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.39.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.39.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,
TIM16,TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.39.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.39.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 75
3.39.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.39.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.39.7 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.39.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.40 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 76
3.40.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.40.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.41 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.42 Universal synchronous/asynchronous receiver transmitter (USART/UART)
and low-power universal asynchronous receiver transmitter (LPUART) . 80
3.42.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.42.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 82
3.43 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.44 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.45 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 85
3.46 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.47 USB full speed (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.48 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.48.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.48.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4 Pinout, pin description, and alternate functions . . . . . . . . . . . . . . . . . 89

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 138
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 138
5.3.4 SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.7 Wake-up time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.3.8 External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.3.9 Internal clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 217
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5.3.19 14-bit analog-to-digital converter (ADC1) characteristics . . . . . . . . . . 218
5.3.20 12-bit analog-to-digital converter (ADC4) characteristics . . . . . . . . . . 224
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.3.22 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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5.3.24 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 230

5.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 234
5.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
5.3.27 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.3.28 Temperature and backup domain supply thresholds monitoring . . . . . 241
5.3.29 ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
5.3.30 DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
5.3.31 PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3.32 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
5.3.33 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.3.34 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics . . . . 255
5.3.35 Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.3.36 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.3.37 USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.3.38 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.3.39 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.3.40 USB_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.3.41 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 267

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

6.1 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.2 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . 273
6.3 WLCSP56 package information (B0H4) . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.4 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
6.5 UFBGA64 package information (A019) . . . . . . . . . . . . . . . . . . . . . . . . . 284
6.6 WLCSP72 package information (B0HK) . . . . . . . . . . . . . . . . . . . . . . . . 288
6.7 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
6.8 UFBGA100 package information (A0C2) . . . . . . . . . . . . . . . . . . . . . . . . 296
6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32U545xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 23
Table 4. Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 24
Table 5. Example of memory map security attribution versus SAU configuration regions . . . . . . . . 27
Table 6. Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. STM32U545xx mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 12. GPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 51
Table 13. LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 14. LPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 53
Table 15. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 16. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 19. AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 20. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 21. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 22. USART, UART, and LPUART features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 24. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 25. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 26. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 27. STM32U545xx pin/ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 28. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 29. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 30. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 31. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 32. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 33. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 34. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 35. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 36. SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 37. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 38. Current consumption in Run mode on LDO, code with data processing
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 143
Table 39. Current consumption in Run mode on SMPS, code with data processing
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 144
Table 40. Current consumption in Run mode on SMPS, code with data processing
running from flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V . . . . . . . . . 145
Table 41. Typical current consumption in Run mode on LDO, with different codes
running from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . . 146
Table 42. Typical current consumption in Run mode on LDO, with different codes
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 146
Table 43. Typical current consumption in Run mode on SMPS, with different codes

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running from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON . . . . 148
Table 44. Typical current consumption in Run mode on SMPS, with different codes
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 148
Table 45. Current consumption in Sleep mode on LDO, flash memory in power down . . . . . . . . . . 150
Table 46. Current consumption in Sleep mode on SMPS, flash memory in power down. . . . . . . . . 151
Table 47. Current consumption in Sleep mode on SMPS,
flash memory in power down, VDD = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 48. SRAM1 current consumption in Run/Sleep mode with LDO and SMPS . . . . . . . . . . . . . 153
Table 49. Static power consumption of flash banks, when supplied by LDO/SMPS . . . . . . . . . . . . 154
Table 50. Current consumption in Stop 0 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 51. Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 52. Current consumption in Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 53. Current consumption during wake-up from Stop 1 mode on LDO . . . . . . . . . . . . . . . . . . 157
Table 54. Current consumption in Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 55. Current consumption during wake-up from Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . 159
Table 56. Current consumption in Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 57. SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 161
Table 58. Current consumption during wake-up from Stop 2 mode on LDO . . . . . . . . . . . . . . . . . . 161
Table 59. Current consumption in Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 60. SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 164
Table 61. Current consumption during wake-up from Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . 165
Table 62. Current consumption in Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 63. SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 167
Table 64. Current consumption during wake-up from Stop 3 mode on LDO . . . . . . . . . . . . . . . . . . 168
Table 65. Current consumption in Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 66. SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 170
Table 67. Current consumption during wake-up from Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . 171
Table 68. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 69. Current consumption during wake-up from Standby mode. . . . . . . . . . . . . . . . . . . . . . . . 175
Table 70. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 71. Current consumption during wake-up from Shutdown mode . . . . . . . . . . . . . . . . . . . . . . 176
Table 72. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 73. Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 74. Low-power mode wake-up timings on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 75. Low-power mode wake-up timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 76. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 77. Wake-up time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 78. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 79. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 80. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 81. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 82. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 83. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 84. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 85. SHSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 86. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 87. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 88. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 89. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 90. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 91. EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz. . . . . . . . . . . . . . . . . . . . . . . 205
Table 92. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

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Table 93. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 94. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 95. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 96. Output voltage characteristics (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 97. Output voltage characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os . . . . . . . . 210
Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 99. Output AC characteristics, HSLV ON (all I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . 213
Table 100. Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 101. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os . . . . . . . . . . . . 215
Table 102. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 103. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 104. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 105. 14-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 106. Maximum RAIN for 14-bit ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 107. 14-bit ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 108. 12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 109. Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 110. 12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 111. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 112. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 113. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 114. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 115. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 116. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 117. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 118. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 119. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 120. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 121. MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 122. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 123. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 124. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 125. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 126. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 127. WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 128. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 129. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 130. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 252
Table 131. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 132. e•MMC characteristics (VDD = 1.71 V to 1.9 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 133. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 134. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 135. USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 136. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 137. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 138. USB_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 139. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 140. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 141. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 142. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

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Table 143. WLCSP56 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 144. WLCSP56 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 145. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 146. UFBGA64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 147. UFBGA64 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 286
Table 148. WLCSP72 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 149. WLCSP72 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 150. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 151. UFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 152. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 298
Table 153. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 154. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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List of figures STM32U545xx

List of figures

Figure 1. STM32U545xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. STM32U545xxxxQ power supply overview (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3. STM32U545xx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4. Power-up / down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6. VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7. LQFP48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 8. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 9. UFQFPN48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 10. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 11. LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 12. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 13. UFBGA64_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 14. UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 15. WLCSP56_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 16. WLCSP72_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 17. LQFP100_SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 18. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 19. UFBGA100_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 20. UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 21. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 22. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 23. STM32U545xx power supply scheme (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 24. STM32U545xQ power supply scheme (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 25. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 26. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 27. AC timing diagram for high-speed external clock source (digital mode). . . . . . . . . . . . . . 190
Figure 28. AC timing diagram for high-speed external clock source (analog mode) . . . . . . . . . . . . . 191
Figure 29. AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 191
Figure 30. AC timing diagram for low-speed external sinusoidal clock source . . . . . . . . . . . . . . . . . 192
Figure 31. Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 33. HSI16 frequency versus temperature and VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 34. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 35. I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 209
Figure 36. Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 38. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 39. Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 40. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 41. VREFBUF_OUT versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 42. VREFBUF_OUT versus temperature (VRS = 001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 43. VREFBUF_OUT versus temperature (VRS = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 44. VREFBUF_OUT versus temperature (VRS = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 45. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ . . . . . . . . . . . . . . . . . . . . 241
Figure 46. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ . . . . . . . . . . . . . . . . . . 241
Figure 47. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

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Figure 48. MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 49. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 50. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 51. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 52. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 53. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 54. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 55. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 56. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 57. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 58. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 59. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 60. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 61. USART timing diagram in SPI master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 62. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 63. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 64. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 65. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 66. SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 67. SAI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 68. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 69. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 70. LQFP48 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 71. LQFP48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 72. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 73. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 74. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 75. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 76. WLCSP56 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 77. WLCSP56 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 78. WLCSP56 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 79. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 80. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 81. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 82. UFBGA64 – Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 83. UFBGA64 – Footprint example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 84. UFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 85. WLCSP72 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 86. WLCSP72 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 87. WLCSP72 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 88. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 89. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 90. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 91. UFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 92. UFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 93. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

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13
Introduction STM32U545xx

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32U545xx microcontrollers.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33
Technical Reference Manual, available from the www.arm.com website.

For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32U535xx and STM32U545xx errata sheet (ES0587).

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32U545xx Description

2 Description

The STM32U545xx devices belong to an ultra-low-power microcontrollers family

(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a MPU (memory protection unit) that enhances the application security.
The devices embed high-speed memories (512-Kbyte flash memory and 274-Kbyte SRAM),
one Octo-SPI flash memory interface, an extensive range of enhanced I/Os, peripherals
connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the TBSA (trusted-based security
architecture) requirements from Arm®. It embeds the necessary security features to
implement a secure boot, secure data storage and secure firmware update. Besides these
capabilities, the devices incorporate a secure firmware installation feature, that allows the
customer to secure the provisioning of the code during its production. A flexible lifecycle is
managed thanks to multiple levels of readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and
I/Os, and privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, secure and hide protection areas.
The devices embed several peripherals reinforcing security: a fast AES coprocessor,
a secure AES coprocessor with DPA resistance and hardware unique key that can be
shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance,
an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware
accelerator, and a true random number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps), one
comparator, one operational amplifier, two DAC channels, an internal voltage reference
buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and
four 16-bit low-power timers.
The devices support a MDF (multi-function digital filter) with two filters dedicated to the
connection of external sigma-delta modulators. Another low-power digital filter dedicated to
audio signals is embedded (ADF), with one filter supporting sound-activity detection. The
devices embed also mathematical accelerators (a trigonometric functions accelerator plus a
filter mathematical accelerator). In addition, up to 20 capacitive sensing channels are
available.
The devices also feature standard and advanced communication interfaces such as:
four I2Cs, three SPIs, two USARTs, two UARTs, one low-power UART, one SAI, one digital
camera interface (DCMI), one SDMMC, one FDCAN, one USB host and device capable

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Description STM32U545xx

full-speed, and one generic synchronous 8-/16-bit PSSI (parallel data input/output slave
interface).
The devices operate in the –40 to +85 °C (+105 °C junction) and –40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Many peripherals (including communication, analog, timers and audio peripherals) can be
functional and autonomous down to Stop mode with direct memory access, thanks to
LPBAM support (low-power background autonomous mode).
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and
up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available
for connecting a backup battery in order to preserve the RTC functionality and to backup
32 × 32-bit registers and 2-Kbyte SRAM.
The devices offer eight packages from 48 to 100 pins.

Table 2. STM32U545xx features and peripheral counts

STM32U545CE

STM32U545RE

STM32U545NE

STM32U545VE
STM32U545JE
Peripherals

Flash memory (Kbytes) 512

System (Kbytes) 272 (192+64+16)
SRAM (274 Kbytes)
Backup (bytes) 2048 backup SRAM + 128 backup registers
OCTOSPI 1(1)
Advanced control 2 (16 bits)
General purpose 4 (32 bits) and 3 (16 bits)
Basic 2 (16 bits)

Timers Low power 4 (16 bits)

SysTick timer 2
Watchdog timers
(independent, 2
window)

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STM32U545xx Description

Table 2. STM32U545xx features and peripheral counts (continued)

STM32U545CE

STM32U545RE

STM32U545NE

STM32U545VE
STM32U545JE
Peripherals

SPI 3
I2C 4
USART 2
(2)
UART 1 2 1(2) 2
LPUART 1
Communication
SAI 1
interfaces
FDCAN 1
USB (host/device) Yes
SDMMC 0 1 0 1
Camera interface No Yes(3)
PSSI No Yes(4)
MDF (multi-function digital filter) Yes (2 filters)
ADF (audio digital filter) Yes
CORDIC co-processor Yes
FMAC (filter mathematical accelerator) Yes
RTC (real-time clock) Yes
Tamper pins (without SMPS / 3/3 4/3 6 3 8/7
with SMPS)
Active tampers (without SMPS /
2/2 3/2 5 2 7/6
with SMPS)(5)
True random number generator Yes
SAES, AES Yes
PKA (public key accelerator) Yes
HASH (SHA-256) Yes
On-the-fly decryption for OCTOSPI Yes

GPIOs (without SMPS / with SMPS) 37 / 33 51 / 47 39 50 82 / 79

Wake-up pins (without SMPS /
with SMPS) 17 / 15 18 / 17 18 17 23 / 22
Number of I/Os down to 1.08 V (without
SMPS / with SMPS) 0/0 0/0 0 14 0/0

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19
Description STM32U545xx

Table 2. STM32U545xx features and peripheral counts (continued)

STM32U545CE

STM32U545RE

STM32U545NE

STM32U545VE
STM32U545JE
Peripherals

Capacitive sensing
Number of channels (without SMPS / 5/4 11 / 10 7 4 20 / 19
with SMPS)
12-bit ADC 1
14-bit ADC 1
ADC Number of
channels (without
11 / 10 17 / 15 11 12 20 / 18
SMPS /
with SMPS)
Number of 12-bit
DAC 2
D-to-A converters
Internal voltage reference buffer No Yes
Analog comparator 1
Operational amplifier 1
Maximum CPU frequency 160 MHz
Operating voltage 1.71 to 3.6 V
Ambient operating temperature: –40 to +85 °C / –40 to +125 °C
Operating temperature
Junction temperature: –40 to +105 °C / –40 to +130 °C
LQFP48, LQFP64, LQFP100,
Package WLCSP56 WLCSP72
UFQFPN48 UFBGA64 UFBGA100
1. HyperBus differential mode with CLK/NCLK is supported only in LQFP100 and BGA100 packages.
2. UART4
3. Up to 12 bits.
4. 8 bits only.
5. Active tampers in output sharing mode (one output shared by all inputs).

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Figure 1. STM32U545xx block diagram

NJTRST, JTDI, JTCK/SWCLK, JTAG/ SW MPU

JTMS/SWDIO, JTDO
ETM NVIC IO[7:0], CLK, NCLK, NCS.
OTFDEC1 and Octo-SPI1 memory interface DQS as AF

(8 Kbytes)
TRACECLK,

ICACHE
TRACED[3:0] Arm Cortex-M33
160 MHz C-BUS Flash memory RNG
TrustZone FPU AES

AHB bus-matrix
(up to 512 Kbytes)
HASH

DCACHE1
S-BUS

(4 Kbytes)
SAES
SRAM1 (192 Kbytes)
@VDDUSB
SRAM2 (64 Kbytes) PKA
D[7:0], D[3:1]dir

FIFO

PHY
DP
FIFO

CMD, CMDdir,CK, CKin SDMMC1 USB

DM
D0dir, D2dir

DCMI/PSSI D[15:0], CK, CMD as AF

AHB2 160 MHz

@VDD
@VDD
VDD Power management
SHSI
GPDMA1
Voltage regulator LDO VDD = 1.71 to 3.6 V
HSI48 and SMPS VSS
7 groups of 4 channels max TSC
as AF MSI @VDD
SDIN[1:0], CKIN[1:0], CCK0, Reset Supply supervision
CCK1 as AF MDF1 HSI16 BOR
@VSW VDDIO, VDDUSB, VDDA,
PA[15:0] GPIO port A Int PVD, PVM
LSI VSSA, VDD, VSS, NRST
BKPSRAM
PB[15:0] GPIO port B (2 Kbytes)
PLL 1, 2, 3 @VDD
PC[15:13]
AHB1 160 MHz

GPIO port C XTAL OSC

PC[12:0] OSC_IN
4- 50 MHz OSC_OUT
PD[15:0] GPIO port D
IWDG
PE[15:0] GPIO port E

PG[15:2] GPIO port G Reset and clock control

Standby
PH[1:0] GTZC1 WKUPx (x=1 to 8)
GPIO port H interface
PH[3] FCLK

HCLKx

PCLKx
CRC TIM2 32b 4 channels, ETR as AF
97 AF EXT IT. WKP
CORDIC TIM3 32b 4 channels, ETR as AF

@VDDA FMAC CRS TIM4 32b 4 channels, ETR as AF

17xIN
ADC1 ITF
TIM5 32b 4 channels

smcard
AHB/APB2 AHB/APB1 RX, TX, CK, CTS, RTS as AF
USART3 irDA
3 compl. channels

APB1 160 MHz (max)

(TIM1_CH[1:3]N), TIM1/PWM 16b
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF UART4 RX, TX, CTS, RTS as AF

3 compl. channels
UART5 RX, TX, CTS, RTS as AF
(TIM1_CH[1:3]N), TIM8/PWM 16b
4 channels (TIM1_CH[1:4]),
SYSCFG
ETR, BKIN, BKIN2 as AF
MOSI, MISO, SCK, NSS as
APB2 160 MHz

SPI2
2 channels, AF
TIM15 16b
1 compl. channel, BKIN as AF

1 channel, I2C1/SMBUS SCL, SDA, SMBA as AF

TIM16 16b
1 compl. channel, BKIN as AF
I2C2/SMBUS SCL, SDA, SMBA as AF
1 channel, TIM17 16b
1 compl. channel, BKIN as AF
smcard I2C4/SMBUS SCL, SDA, SMBA as AF
RX, TX, CK,CTS, RTS as AF USART1 WWDG
irDA
FIFO

MOSI, MISO, SCK, NSS as SPI1 FDCAN1 TX, RX as AF

SRAM4
AF LPDMA1
(16 Kbytes)
MCLK_A, SD_A, FS_A,
AHB bus-matrix

SCK_A, MCLK_B, SD_B, SAI1 TIM6 16b

FS_B, SCK_B as AF
AUDIOCLK as AF TIM7 16b
IN1, IN2, CH1, CH2,
LPTIM2
Temperature ETR as AF
monitoring
@VSW
RTC_OUT1, RTC_OUT2, XTAL 32k @VDDA
RTC_REFIN, RTC_TS DAC1_OUT1
RTC D/A converter 1
ITF
TAMP_OUT[8:1],
TAMP
TAMP_IN[8:1] D/A converter 2 DAC1_OUT2
@VDDA AHB/APB3
VREF+
VREF buffer @VDDA
APB3 160 MHz

AHB3 160 MHz

@VDDA ITF ADC4 15xIN

INP, INN, OUT COMP1

@VDDA LPGPIO IO[15:0] as AF

INP, INN, OUT OpAmp1
SDIN0, CKIN0, CCK0,
ADF1
CCK1 as AF
IN1, IN2, CH1, CH2,
LPTIM1
ETR as AF
IN1, IN2, CH1, CH2, LPTIM3 GTZC2
ETR as AF

IN1, OUT, ETR as AF LPTIM4

SCL, SDA, SMBA as AF I2C3/SMBUS VDD power VDDUSB power VSW power VDDIO2 power VDDA power
MOSI, MISO, SCK, NSS as
domain domain domain domain domain
SPI3
AF
RX, TX, CTS, RTS_DE as
LPUART1 Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
AF
MSv70510V1

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Functional overview STM32U545xx

3 Functional overview

3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
nonsecure states
• MPUs (memory protection units), supporting up to 16 regions for secure and
nonsecure applications
• Configurable SAU (secure attribute unit) supporting up to eight memory regions as
secure or nonsecure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The S-AHB (system AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The C-AHB (code AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32U545xx devices.

3.2 ART Accelerator (ICACHE and DCACHE)

3.2.1 Instruction cache (ICACHE)

The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve
performance when fetching instruction (or data) from both internal and external memories.
ICACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– Master1 port performing refill requests to internal memories (flash memory and
SRAMs)
– Master2 port performing refill requests to external memories (external flash
memory and RAMs through Octo-SPI)
– Second slave port dedicated to ICACHE registers access

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• Close to zero wait-states instructions/data access performance:

– 0 wait-state on cache hit
– Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy, minimizing processor stalls on cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Dual master ports allowing to decouple internal and external memory traffics, on
fast and slow buses, respectively; also minimizing impact on interrupt latency
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising

3.2.2 Data cache (DCACHE)

The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the
performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– Master port performing refill requests to external memories (external flash memory
and RAMs through Octo-SPI)
– Second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– Zero wait-states on cache hit
– Hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)

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Functional overview STM32U545xx

• Supported cache accesses:

– Both write-back and write-through policies supported (selectable with AHB
bufferable attribute)
– Read and write-back always allocated
– Write-through always non-allocated (write-around)
– Byte, half-word and word writes supported
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– Full cache invalidation (non interruptible)
– Address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising

3.3 Memory protection unit

The MPU (memory protection unit) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 16 protected areas.
The MPU regions and registers are banked across secure and nonsecure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by a RTOS
(real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In a RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.4 Embedded flash memory

The devices feature 512-Kbyte embedded flash memory that is available for storing
programs and data. The flash memory supports up to 100 000 cycles.
A 128-bit instruction prefetch is implemented and can optionally be enabled.
The flash memory interface features:
• Dual-bank operating modes
• Read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. The dual-bank boot is also supported. Each bank
contains 32 pages of 8 Kbytes. The flash memory also embeds 512-byte OTP (one-time
programmable) for user data.
The whole non-volatile memory embeds the ECC (error correction code) feature supporting:
• single-error detection and correction
• double-error detection
• ECC fail address report

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3.4.1 Flash memory protection

The option bytes allow the configuration of flexible protections:
• write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• RDP (readout protection) to protect the whole memory, has four levels of protection
available (see Table 3 and Table 4):
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the nonsecure flash
memory are possible. The debug access to secure area is prohibited.
Debug access to nonsecure area remains possible.
– Level 1: memory readout protection
The flash memory cannot be read from or written to if either the debug features
are connected or the boot in RAM or bootloader are selected. If TrustZone is
enabled, the nonsecure debug is possible and the boot in SRAM is not possible.
Regressions from Level 1 to lower levels can be protected by password
authentication.
– Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled.
A secure secret key can be configured in the secure options to allow the
regression capability from Level 2 to Level 1. By default (key not configured), this
Level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the
secret key was previously configured in lower RDP levels, the device enables the
RDP regression from Level 2 to Level 1 after password authentication through
JTAG/SWD interface.
Note: In order to reach the best protection level, it is recommended to activate TrustZone and to
set the RDP Level 2 with password authentication regression enabled.

Table 3. Access status versus protection level and execution modes when TZEN = 0
User execution
RDP Debug/boot from RAM/ bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase

1 Yes Yes Yes No No No(4)

Flash main memory
2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No
System memory (2)
2 Yes No No N/A N/A N/A

1 Yes Yes(4) N/A Yes Yes(4) N/A

Option bytes(3)
2 Yes No(5) N/A N/A N/A N/A

1 Yes Yes(6) N/A Yes Yes(6) N/A

OTP
2 Yes Yes(6) N/A N/A N/A N/A

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Functional overview STM32U545xx

Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)
User execution
RDP Debug/boot from RAM/ bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase

1 Yes Yes N/A No No N/A(7)

Backup registers
2 Yes Yes N/A N/A N/A N/A

1 Yes Yes N/A No No N/A(8)

SRAM2/backup
RAM
2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes No(9) Yes Yes

OTFDEC regions
(Octo-SPI)
2 Yes Yes Yes N/A N/A N/A

1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are only accessible through the flash memory registers and OPSTRT bit.
4. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.
5. SWAP_BANK option bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

Table 4. Access status versus protection level and execution modes when TZEN = 1
User execution
RDP Debug/ bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase

0.5 Yes Yes Yes Yes(2) Yes(2) Yes(2)

Flash main memory 1 Yes Yes Yes No No No(5)

2 Yes Yes Yes N/A N/A N/A

0.5 Yes No No Yes No No

System memory (3) 1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

0.5 Yes Yes(5) N/A Yes Yes (5) N/A

Option bytes(4) 1 Yes Yes(5) N/A Yes Yes(5) N/A

2 Yes No(6) N/A N/A N/A N/A

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Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
User execution
RDP Debug/ bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase

0.5 Yes Yes(7) N/A Yes Yes(7) N/A

OTP 1 Yes Yes(7) N/A Yes Yes(7) N/A

2 Yes Yes(7) N/A N/A N/A N/A

0.5 Yes Yes N/A Yes(2) Yes(2) N/A(8)

Backup registers 1 Yes Yes N/A No No N/A(8)

2 Yes Yes N/A N/A N/A N/A

0.5 Yes Yes N/A Yes(2) Yes(2) N/A(9)

SRAM2/backup
1 Yes Yes N/A No No N/A(9)
RAM
2 Yes Yes N/A N/A N/A N/A

0.5 Yes Yes Yes No(10) Yes Yes

OTFDEC regions
1 Yes Yes Yes No(10) Yes Yes
(Octo-SPI)
2 Yes Yes Yes N/A N/A N/A

1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends on TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the flash memory registers and OPSTRT bit.
5. The flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. SWAP_BANK option bit can be modified.
7. OTP can only be written once.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

3.4.2 Additional flash memory protections when TrustZone activated

When the TrustZone security is enabled through option bytes, the whole flash memory is
secure after reset and the following protections are available:
• non-volatile watermark-based secure flash memory area
The secure area can be accessed only in Secure mode. One area per bank can be
selected with a page granularity.
• secure HDP (hide protection area)
It is part of the flash memory secure area and can be protected to deny an access to
this area by any data read, write and instruction fetch. For example, a software code in
the secure flash memory hide protection area can be executed only once and deny any

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Functional overview STM32U545xx

further access to this area until next system reset. One area per bank can be selected
at the beginning of the secure area.
• volatile block-based secure flash memory area
Each page can be programmed on-the-fly as secure or nonsecure.

3.4.3 FLASH privilege protection

Each flash memory page can be programmed on-the-fly as privileged or unprivileged.

3.5 Embedded SRAMs

Five SRAMs are embedded in the STM32U545xx devices, each with specific features.
SRAM1 and SRAM2 are the main SRAMs. SRAM4 is in the SRAM used for peripherals
LPBAM (low-power background autonomous mode) in Stop 2 mode.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: three 64-Kbyte blocks (total 192 Kbytes)
• SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition
SRAM2 blocks can be retained in Standby mode.
• SRAM4: 16 Kbytes
• BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode, but not in
Shutdown mode.

3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset.
The SRAM1, SRAM2, and SRAM4 can be programmed as secure or nonsecure by blocks,
using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).

3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, and SRAM4 can be programmed as privileged or unprivileged
by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page
of 512 bytes. Backup SRAM regions can be programmed as privileged or unprivileged
with watermark, using the TZSC (TrustZone security controller) in the GTZC (global
TrustZone controller).

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3.6 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and nonsecure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as nonsecure or nonsecure callable
attributes. It is then combined with the results from the SAU security attribution and
the higher security state is selected.
Based on IDAU security attribution, the flash memory, system SRAM and peripheral
memory space is aliased twice for secure and nonsecure states. However, the external
memory space is not aliased.
The table below shows an example of typical SAU region configuration based on IDAU
regions. The user can split and choose the secure, nonsecure or NSC regions for external
memories as needed.
Table 5. Example of memory map security attribution versus SAU configuration regions
SAU security
Region IDAU security Final security
Address range attribution typical
description attribution attribution
configuration

0x0000 0000 Secure or Secure or

Code - external memories Nonsecure
0x07FF FFFF nonsecure or NSC(1) nonsecure or NSC

0x0800 0000
Nonsecure Nonsecure Nonsecure
0x0BFF FFFF
Code - Flash and SRAM
0x0C00 0000
NSC Secure or NSC Secure or NSC
0x0FFF FFFF
0x1000 0000
0x17FF FFFF
Code - external memories Nonsecure
0x1800 0000
Nonsecure
0x1FFF FFFF
0x2000 0000
Nonsecure
0x2FFF FFFF
SRAM
0x3000 0000
NSC Secure or NSC Secure or NSC
0x3FFF FFFF
0x4000 0000
Nonsecure Nonsecure Nonsecure
0x4FFF FFFF
Peripherals
0x5000 0000
NSC Secure or NSC Secure or NSC
0x5FFF FFFF
0x6000 0000 Secure or Secure or
External memories Nonsecure
0xDFFF FFFF nonsecure or NSC nonsecure or NSC
1. NSC = nonsecure callable.

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3.6.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure

3.6.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure.
Up to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
– Flash memory block based area is nonsecure after reset.
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– OCTOSPI banks are secure after reset. MPCWMx (memory protection watermark
based controller) is secure.
• Peripherals
– Securable peripherals are nonsecure after reset.
– TrustZone-aware peripherals are nonsecure after reset. Their secure configuration
registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and
nonsecure state.
• TZIC: All illegal access interrupts are disabled after reset.

3.7 Boot modes

At startup, a BOOT0 pin, NBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that
includes:
• Boot from any address in user flash memory.
• Boot from system memory bootloader.
• Boot from any address in embedded SRAM.
• Boot from RSS (root security services).

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The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during production.
The bootloader is used to reprogram the flash memory by using USART, I2C, SPI, FDCAN
or USB in device mode through the DFU (device firmware upgrade).
The bootloader is available on all devices. Refer to the application note
STM32 microcontroller system memory boot mode (AN2606) for more details.
The RSS are embedded in a flash memory area named secure information block,
programmed during ST production.
For example, the RSS enable the SFI (secure firmware installation), thanks to the RSSe SFI
(RSS extension firmware).
This feature allows customer to produce the confidentiality of the firmware to be provisioned
into the STM32, when production is sub-contracted to untrusted third party.
The RSS are available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to the application note Overview secure firmware install (SFI) (AN4992)
for more details.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and
enabled respectively.

Table 6. Boot modes when TrustZone is disabled (TZEN = 0)

NBOOT0 NSWBOOT0 Boot address
BOOT0 ST programmed
FLASH_ FLASH_ option-byte Boot area
pin PH3 default value
OPTR[27] OPTR[26] selection

Boot address defined by

- 0 1 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
Bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
Boot address defined by
1 - 0 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
Bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.

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Table 7. Boot modes when TrustZone is enabled (TZEN = 1)

NBOOT0 BOOT0 NSWBOOT0 RSS Boot address ST pro-
BOOT_
FLASH_ pin FLASH_ com- option-bytes Boot area grammed
LOCK
OPTR[27] PH3 OPTR[26] mand selection default value

Secure boot address

SECBOOTADD0 defined by user Flash:
- 0 1 0
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS
0x0FF8 0000
Secure boot address
0
SECBOOTADD0 defined by user Flash:
1 - 0 0
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
0 - 0 0 N/A RSS
0x0FF8 0000
RSS:
- - - ≠0 N/A RSS
0x0FF8 0000
Secure boot address
SECBOOTADD0 defined by user Flash:
1 - - - -
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]

The boot address option bytes allow any boot memory address to be programmed.
However, the allowed address space depends on the flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot address is forced either in secure flash memory or
nonsecure flash memory, depending on TrustZone security option as described in the table
below.

Table 8. Boot space versus RDP protection

RDP TZEN = 1 TZEN = 0

0 Any boot address Any boot address

0.5 N/A
1 Boot address only in RSS or secure flash memory: Any boot address
0x0C00 0000 - 0x0C07 FFFF Boot address only in flash memory
2 Otherwise, forced boot address is 0x0FF8 0000. 0x0800 0000 - 0x0807 FFFF
Otherwise, forced boot address is 0x0800 0000.

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3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the nonsecure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates
a secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• Secure and nonsecure access supported for privileged/unprivileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters

3.9 Power supply management

The PWR (power controller) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
• Power supply supervision
– BOR monitor
– PVD monitor
– PVM monitor (VDDA, VDDUSB, VDDIO2)

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• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection

3.9.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx min value)
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) /
1.8 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, voltage reference buffer,
operational amplifiers and comparators. The VDDA voltage level is independent from
the VDD voltage and must be connected to VDD or VSS pin (preferably to VDD) when
these peripherals are not used.
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply
than VDD.
• VLXSMPS is the switched SMPS step down converter output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. VDDUSB
voltage level is independent from the VDD voltage and must be connected to VDD or
VSS pin (preferably to VDD) when the USB is not used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and must be connected to VDD or VSS pin
(preferably to VDD) when PG[15:2] are not used.
• VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT min value)
VBAT is the power supply for RTC, TAMP, external and internal clocks 32 kHz
oscillators and backup registers (through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports four outputs:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
– VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.

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– VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.

– VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The STM32U545xx devices embed two regulators: one LDO and one SMPS in parallel to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, and SRAM4 and
embedded flash memory. The SMPS generates this voltage on VDD11 (two pins), with
a total external capacitor of 4.7 μF typical. SMPS requires an external coil of 2.2 μH typical.
The LDO generates this voltage on VCAP pin connected to an external capacitor of 4.7 μF
typical.
Both regulators can provide four different voltages (voltage scaling) and can operate in
Stop modes.
It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly.

Figure 2. STM32U545xxxxQ power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1 I/O ring

Reset block
Temperature sensor
3 x PLL
VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wake-up logic, IWDG)
SRAM1
VDD SRAM2
Voltage regulator SRAM4
LDO regulator VCORE Digital
2x VDD11 peripherals
VLXSMPS SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector

Backup domain
VSW LSE crystal 32 kHz oscillator
VBAT LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
MSv70511V2

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Figure 3. STM32U545xx power supply overview (without SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]

VDD domain
VDDIO1
I/O ring
VCORE domain
Reset block
Temperature sensor
3 x PLL Core
VSS Internal RC oscillators
SRAM1
SRAM2
Standby circuitry
SRAM4
VDD (Wake-up logic, IWDG)
VCORE Digital
VCAP peripherals
LDO regulator

Flash memory
Low-voltage detector

Backup domain
LSE crystal 32 kHz oscillator
VBAT VSW LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM MSv70512V2

In this document, VDDIOx refers to the I/O power supply. VDDIOx can be VDDIO1 (which is
supplied by VDD), VDDIO2 (independent power supply for PG[15:2]), or VSW (supplying
PC13, PC14, PC15, and all FT_t I/Os in VBAT mode).
VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the
power-down transient phase.

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Figure 4. Power-up / down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.

3.9.2 Power supply supervisor

The devices have an integrated ultra-low-power BOR (Brownout reset) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power
on and during power down. The device remains in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded PVD (programmable voltage
detector) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 160 MHz
• Range 2 (VCORE = 1.1 V) with CPU and peripherals running at up to 110 MHz
• Range 3 (VCORE = 1.0 V) with CPU and peripherals running at up to 55 MHz
• Range 4 (VCORE = 0.9 V) with CPU and peripherals running at up to 25 MHz

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3.9.3 Low-power modes

The ultra-low-power STM32U545xx devices support seven low-power modes to achieve the
best compromise between low-power consumption, short startup time, available peripherals
and available wake-up sources.
The table below details the related low-power modes.

Table 9. STM32U545xx mode overview

(1)
Mode Regulator CPU Flash SRAM Clocks DMA and peripherals(2) Wake-up source

Range 1
Range 2 All
Run Yes ON(3) ON Any N/A
Range 3
Range 4 All except USB
Range 1
Range 2 All Any interrupt or
Sleep No ON ON(4) Any
Range 3 event

Range 4 All except USB

Range 1 BOR, PVD, PVM,
Reset pin, all I/Os,
Range 2 RTC, TAMP, IWDG,
BOR, PVD, PVM,
Stop 0 TEMP (temp. sensor),
Range 3 VREFBUF, RTC, TAMP, IWDG,
ADC4(7), TEMP,
Range 4
DAC1 (2 channels)(8), ADC4,
COMP1, DAC1 (2 channels),
OPAMP1, COMP1,
LSE USARTx
USARTx (x = 1, 3, 4, 5)(9),
No OFF ON(5) LSI (x = 1, 3, 4, 5),
(6)
LPUART1,
LPUART1,
SPIx (x = 1...3)(10),
SPIx (x = 1...3),
Stop 1 LPR I2Cx (x = 1...4)(11),
I2Cx (x = 1...4),
LPTIMx (x = 1...4)(12),
LPTIMx (x = 1...4),
MDF1(13), ADF1,
MDF1, ADF1,
GPIO, LPGPIO,
GPDMA1,
GPDMA1(14), LPDMA1
LPDMA1,
USB
All other peripherals are frozen.

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Table 9. STM32U545xx mode overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA and peripherals(2) Wake-up source

BOR, PVD, PVM, Reset pin, all I/Os,

RTC, TAMP, IWDG, BOR, PVD, PVM,
TEMP, VREFBUF, RTC, TAMP, IWDG,
ADC4, TEMP,
DAC1 (2 channels), ADC4,
COMP1, COMP1,
OPAMP1, LPUART1,
LSE LPUART1, SPI3,
Stop 2 LPR No OFF ON(5)
LSI SPI3, I2C3,
I2C3, LPTIMx (x = 1,3,4),
LPTIMx (x = 1, 3, 4), ADF1,
ADF1, LPDMA1
LPGPIO,
LPDMA1

All other peripherals are frozen.

BOR, Reset pin,
RTC, TAMP, IWDG, 24 I/Os (WKUPx),
DAC1 (2 static channels), BOR, RTC, TAMP,
OPAMP1 IWDG
LSE
Stop 3 LPR No OFF ON(5)
LSI
All other peripherals are frozen.

I/O configuration can be floating,

pull-up or pull-down.
all other SRAMs powered off

Reset pin,
64-, 56- or 8-Kbyte SRAM2

BOR, RTC, TAMP, IWDG

2-Kbyte BKPSRAM(5)

24 I/Os (WKUPx),
All other peripherals are BOR, RTC, TAMP,
powered off. IWDG
LPR
Powered off

LSE I/O configuration can be floating,

Standby OFF pull-up or pull-down.
LSI
Powered

OFF
off

RTC, TAMP Reset pin,

24 I/Os (WKUPx),
Powered off

Powered

All other peripherals are RTC, TAMP

Shutdown OFF OFF LSE powered off.
off

I/O configuration can be floating,

pull-up or pull-down(15).

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1. LPR means that the main regulator is OFF and the low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can
also be put in power-down mode.
4. The SRAM1, SRAM2, SRAM4 and BKPSRAM clocks can be gated on or off independently.
5. The SRAM can be individually powered off to save power consumption.
6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from
Stop event detections.
7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on
conversion events.
8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also
called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.
9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can
generate a wake-up interrupt on transfer events.
10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up
interrupt on transfer events.
11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up
interrupt on transfer events.
12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on all events.
13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on events.
14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wake-up interrupt on events.
15. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop 0, Stop 1, Stop 2, and Stop 3 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. The SRAMs can be totally or partially switched off to further
reduce consumption. All clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is
still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting their
kernel clock and their bus (APB or AHB) when needed, in order to transfer data with
DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2
modes). Refer to Low-power background autonomous mode (LPBAM) for more details.
LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage mode.
Stop 0 and Stop 1 modes offer the largest number of active peripherals and wake-up
sources, a smaller wake-up time but a higher consumption than Stop 2 mode.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time but
with much higher consumption.
Stop 3 is the lowest power mode with full retention, but the functional peripherals and
sources of wake-up are reduced to the same ones than in Standby mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI
up to 24 MHz or HSI16, depending on software configuration.

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• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI, the HSI16, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the backup domain and Standby circuitry. Optionally, the full
SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby mode, supplied by the
low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power
consumption during Standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wake-up, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wake-up is MSI up to 4 MHz.
• Shutdown mode
The lowest power consumption is achieved in Shutdown mode. The internal regulator
is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the HSI48, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to backup domain is not supported (VBAT mode is not
supported).
SRAMs and register contents are lost except for registers in the backup domain as long
as VDD is present.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wake-up, timestamp), or a tamper detection.
The system clock after wake-up is MSI at 4 MHz.

Low-power background autonomous mode (LPBAM)

The ultra-low-power STM32U545xx devices support LPBAM (low-power background
autonomous mode) that allows peripherals to be functional and autonomous in Stop mode
(Stop 0, Stop 1 and Stop 2 modes), so without any software running.
In Stop 0 and Stop 1 modes, the autonomous peripherals are the following: ADC4, DAC1,
LPTIMx (x = 1 to 4), USARTx (x = 1, 3, 4, 5), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 4),
MDF1, ADF1, GPDMA1 and LPDMA1. In these modes, SRAM1, SRAM2, and SRAM4 can
be accessed by the GPDMA1, and SRAM4 can be accessed by the LPDMA1.
In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1, LPTIM1,
LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1 and LPDMA1. In this mode, the SRAM4
can be accessed by the LPDMA1.

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Those peripherals support the features detailed below:

• Functionality in Stop mode thanks to its own independent clock (named kernel clock)
request capability: the peripheral kernel clock is automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it.
• DMA transfers supported in Stop mode thanks to system clock request capability: the
system clock (MSI or HSI16) automatically switched on when requested by
a peripheral, and automatically switched off when no peripheral requests it. When the
system clock is requested by an autonomous peripheral, the system clock is woken up
and distributed to all peripherals enabled in the RCC. This allows the DMA to access
the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO
registers).
• Automatic start of the peripheral thanks to hardware synchronous or asynchronous
triggers (such as I/Os edge detection and low-power timer event).
• Wake-up from Stop mode with peripheral interrupt.
The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode,
allowing the different DMA transfers to be linked without any CPU wake-up. This can be
used to chain different peripherals transfers, or to write peripherals registers in order to
change their configuration while remaining in Stop mode.
The DMA transfers from memory to memory can be started by hardware synchronous or
asynchronous triggers, and the DMA transfers between peripherals and memories can also
be gated by those triggers.
Here below some use-cases that can be done while remaining in Stop mode:
• A/D or D/A conversion triggered by a low-power timer (or any other trigger)
– wake-up from Stop mode on analog watchdog if the A/D conversion result is out of
programmed thresholds
– wake-up from Stop mode on DMA buffer event
• Audio digital filter data transfer into SRAM
– wake-up from Stop on sound-activity detection
• I2C slave reception or transmission, SPI reception, UART/LPUART reception
– wake-up at the end of peripheral transfer or on DMA buffer event
2
• I C master transfer, SPI transmission, UART/LPUART transmission, triggered by
a low-power timer (or any other trigger):
– example: sensor periodic read
– wake-up at the end of peripheral transfer or on DMA buffer event
• Bridges between peripherals
– example: ADC converted data transferred by communication peripherals
• Data transfer from/to GPIO/LPGPIO to/from SRAM for:
– controlling external components
– implementing data transmission and reception protocols

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Table 10. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wake-up

Wake-up

Wake-up

Wake-up

Wake-up
Peripheral Run Sleep VBAT
- - - - -

CPU Y - - - - - - - - - - - -
Flash memory
O(2) O(2) - - - - - - - - - - -
(512 Kbytes)
SRAM1 (192 Kbytes) Y(3)(4) Y(3)(4) O(5) - O(5) - O(5) - - - - - -
O
SRAM2 (64 Kbytes) Y(3)(4) Y(3)(4) O(5) O(6) O(5) - O(5) - (7) - - - -

SRAM4 (16 Kbytes) Y(3)(4) Y(3)(4) O(5) - O(5) - O(5) - - - - - -

(4) O(4) O(6)
BKPSRAM O O O O O - O
OCTOSPI1 O O - - - - - - - - - - -
Backup registers Y Y Y - Y - Y - Y - Y - Y
BOR (Brownout reset) Y Y Y Y Y Y Y Y Y Y - - -
PVD (programmable
O O O O O O - - - - - - -
voltage detector)
Peripheral voltage
O O O O O O - - - - - - -
monitor
GPDMA1 O O O O(8) - - - - - - - - -
LPDMA1 O O O O(9) O O(9) - - - - - - -
HSI16 (high-speed (10) (10)
O O - - - - - - - - -
internal)
HSI48 oscillator O O - - - - - - - - - - -
HSE (high-speed
O O - - - - - - - - - - -
external)
LSI (low-speed
O O O - O - O - O - - - O
internal)
LSE (low-speed
O O O - O - O - O - O - O
external)
MSIS and MSIK (10) (10)
O O - - - - - - - - -
(multi-speed internal)
CSS (clock security
O O - - - - - - - - - - -
system)
Clock security system
O O O O O O O O O O O O O
on LSE
Backup domain
voltage and
O O O O O O O O O O - - O
temperature
monitoring

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Table 10. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wake-up

Wake-up

Wake-up

Wake-up

Wake-up
Peripheral Run Sleep VBAT
- - - - -

RTC/TAMP O O O O O O O O O O O O O
Number of RTC
8 8 8 O 8 O 8 O 8 O 8 O 8
tamper pins
USB O(11) O(11) - O - - - - - - - - -
USARTx (x = 1,3,4,5) O O O(12) O (12)
- - - - - - - - -
Low-power UART
O O O(12) O(12) O(12) O(12) - - - - - - -
(LPUART1)
I2Cx (x = 1, 2, 4) O O O(13) O(13) - - - - - - - - -
I2C3 O O O(13) O(13) O(13) O(13) - - - - - - -
(14) (14)
SPIx (x = 1, 2) O O O O - - - - - - - - -
SPI3 O O O(14) O(14) O(14) O(14)
FDCAN1 O O - - - - - - - - - - -
SDMMC1 O O - - - - - - - - - - -
SAI1 O O - - - - - - - - - - -
ADC1 O O - - - - - - - - - - -
(15) O(15) O(15) O(15)
ADC4 O O O - - - - - - -
DAC1 (2 converters) O O O - O - - - - - - - -
VREFBUF O O O - O - - - - - - - -
OPAMP1 O O O - O - - - - - - - -
COMP1 O O O O O O - - - - - - -
Timers (TIMx) O O - - - - - - - - - - -

LPTIMx (x = 1, 3, 4) O O O(16) O(16) O(16) O(16) - - - - - - -

LPTIM2 O O O(16) O(16) - - - - - - - - -

IWDG (independent
O O O O O O O O O O - - -
watchdog)
WWDG (window
O O - - - - - - - - - - -
watchdog)
SysTick timer O O - - - - - - - - - - -
MDF1 (multi-function
O O O(17) O(17) - - - - - - - - -
digital filter)
ADF1 (audio digital
O O O(17) O(17) O(17) O(17) - - - - - - -
filter)

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Table 10. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown

capability

capability

capability

capability

capability
Wake-up

Wake-up

Wake-up

Wake-up

Wake-up
Peripheral Run Sleep VBAT
- - - - -

DCMI (digital camera

O O - - - - - - - - - - -
interface)
PSSI (paral. synch.
O O - - - - - - - - - - -
slave interface)
CORDIC coprocessor O O - - - - - - - - - - -
FMAC (filter
mathematical O O - - - - - - - - - - -
accelerator)
TSC (touch sensing
O O - - - - - - - - - - -
controller)
RNG (true random
O O - - - - - - - - - - -
number generator)
AES and secure AES O O - - - - - - - - - - -
PKA (public key
O O - - - - - - - - - - -
accelerator)
OTFDEC (on-the-fly
O O - - - - - - - - - - -
decryption)
HASH accelerator O O - - - - - - - - - - -
CRC calculation unit O O - - - - - - - - - - -
- 24 - 24 - 24
GPIOs O O O O O O (18) -
pins (18) pins (19) pins
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.
Gray cells highlight the wake-up capability in each mode.
2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. Sub-blocks or full SRAM1, full SRAM2 and SRAM4 can be powered-off to save power consumption. SRAM1, SRAM2, and
SRAM4 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be accessed by LPDMA1 in Stop 0,
Stop 1 and Stop 2 modes.
6. ECC error interrupt or NMI wake-up from Stop mode.
7. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.
8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.
9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.
10. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16, MSIS or MSIK to be
enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
11. USB is functional in voltage scaling range 1, 2 and 3.
12. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and
in SPI master modes, and generate a wake-up interrupt on transfer events.
13. I2C reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt
on transfer events.

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14. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt
on transfer events.
15. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.
16. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.
17. MDF and ADF are functional and autonomous in Stop mode, and generate a wake-up interrupt on events.
18. I/Os can be configured with internal pull-up, pull-down or floating in Stop 3 and Standby modes.
19. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

3.9.4 Reset mode

In order to improve the consumption under reset, the I/O state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.9.5 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or
an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal
VBAT battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC/TAMP
alarm/events exit the microcontroller from the VBAT operation.

3.9.6 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• low-power mode
• WKUP (wake-up) pins
• voltage detection and monitoring
• VBAT mode
Some of the PWR configuration bits security is defined by the security of other peripherals:
• The VOS (voltage scaling) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.

3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.

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Depending on the peripherals, these interconnections can operate in Run, Sleep, Stop 0,
Stop 1, and Stop 2 modes.

3.11 Reset and clock controller (RCC)

The RCC (reset and clock control) manages the different reset types, and generates all
clocks for the bus and peripherals.
The RCC distributes the clocks coming from the different oscillators to the core and to
the peripherals. It also manages the clock gating for low-power modes and ensures the
clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by
a programmable prescaler.
• Clock security system: clock sources can be changed safely on-the-fly in Run mode
through a configuration register.
• Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that can
supply a PLL.
– MSI (multispeed internal RC oscillator) trimmable by software, that can generate
16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device, saving the need of an external high-speed crystal (HSE). The MSI
can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 160 MHz.
• HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be
used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output
on the MCO.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– LSE (32.768 kHz low-speed external crystal), supporting three drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– LSI (32 kHz low-speed internal RC), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPI and SAI.

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• Startup clock: after reset, the microcontroller restarts by default with MSI. The prescaler
ratio and clock source can be changed by the application program as soon as the code
execution starts.
• CSS (clock security system): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and generates
an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 160 MHz.

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Figure 5. Clock tree

LSI RC
LSCO 32 kHz or 250 Hz LSI To IWDG

LSE OSC
OSC32_OUT 32.768 kHz
To RTC
Clock LSI
detector LSE
OSC32_IN /32 MSIK x2
HSI16 To LPTIM1, LPTIM3, LPTIM4
LSE
LSI To PWR
MSIS To AHB bus, core, memory and DMA
MCO HSI16
ĺ HSE
SYSCLK AHB HCLK FCLK Cortex free running clock
PRESC
pll1_r_ck /1,2,..512 LSE
HSI48 LSI To Cortex system timer
MSIK /8
Clock
source
OSC_OUT HSE OSC control APB1 PCLK1
4-50 MHz PRESC
HSE To APB1 peripherals
/1,2,4,8,16
OSC_IN Clock
detector x1 or x2
SYSCLK To TIMx
(x = 2 to 7)
HSI RC 16 MHz HSI16 LSE
HSI16 x4
To USARTx
SYSCLK
MSI RC (x = 3, 4, 5)
MSIS
MSIS 100 kHz – 48 MHz MSIK
MSIK HSI16 To SPI2
MSIK 100 kHz – 48 MHz
SYSCLK

HSI48
HSI48 RC 48 MHz HSI16 x3
SYSCLK To I2Cx
MSIK (X = 1,2,4)
MSIS
PLL1 /M HSI16
pll1_p_ck HSE LSI
VCO /P LSE To LPTIM2
pll1_q_ck HSI16
/Q
pll1_r_ck HSE
/N /R pll1_q_ck
pll2_p_ck To FDCAN1

MSIS CRS clock

PLL2 /M HSI16 SYSCLK
HSE MSIK
pll2_p_ck pll1_q_ck
VCO /P
pll2_q_ck To OCTOSPI1
pll2_q_ck
/Q
pll2_r_ck PCLK2 To SAES
/N /R
APB2
PRESC
To APB2 peripherals
/1,2,4,8,16
MSIS x1 or x2
PLL3 /M HSI16 To TIMx
pll3_p_ck HSE (x = 1,8,15,16,17)
VCO /P
pll3_q_ck
/Q
pll3_r_ck LSE
/N /R HSI16 To USART1
SYSCLK

SHSI RC MSIK
/2 HSI16
SYSCLK To SPI1
pll1_p_ck
pll3_q_ck x2
MSIK To ADF1 and MDF1
AUDIOCLK
pll1_p_ck
pll2_p_ck x2
pll3_p_ck
To SAI1
pll1_p_ck HSI16

To SDMMC1
MSIK ICLK
HSI48
pll1_q_ck 48 MHz clock to USB
pll2_q_ck HSI16
/2
To RNG

PCLK3
APB3
PRESC To APB3 peripherals
/1,2,4,8,16

MSIK To I2C3
HSI16

MSIK To SPI3
HSI16

MSIK
HSI16 To LPUART1
LSE
pll2_r_ck
HSE To ADC1, ADC4 and DAC1
HSI16 LSI
MSIK
LSE
DAC1 sample and hold clock
MSv70513V1

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3.11.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by nonsecure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.

3.12 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, that is either derived
from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin
or generated by user software. For faster lock-in during startup, automatic trimming and
manual trimming action can be combined.

3.13 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

3.13.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a nonsecure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.14 Low-power general-purpose inputs/outputs (LPGPIO)

The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os
can be configured and controlled as input or output (open-drain or push-pull depending on
GPIO configuration).

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3.14.1 LPGPIO TrustZone security

Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is
configured as secure in the GPIO.

3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all master (CPU, GPDMA1, SDMMC1) and
slave (flash memory, RAM, OCTOSPI, SRAMs, AHB and APB) peripherals. It also ensures
a seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave
port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and
AHB/APB peripherals functional in Stop 2 mode).

3.16 System configuration controller (SYSCFG)

The STM32U545xx devices feature a set of configuration registers. The main purposes of
the system configuration controller are the following:
• Managing robustness feature
• Configuring FPU interrupts
• Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os
analog switches
• Managing the I/O compensation cell
• Configuring register security access

3.17 General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a four-grade programmed priority at a channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)

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• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event
• 16 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and nonsecure DMA transfers, independently at a first channel
level, and independently at a source/destination and link sub-levels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port

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Table 11. GPDMA1 channels implementation and usage

Hardware parameters
Channel
Features
x dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 11) is implemented with:

– a FIFO of 8 bytes, 2 words
x = 0 to 11 2 0 – fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers, between an APB
or AHB peripheral and SRAM.
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 32 bytes, 8 words
x = 12 to – 2D addressing
4 1
15 These channels may be also used for GPDMA transfers, between
a demanding AHB peripheral and SRAM, or for transfers from/to external
memories.

Table 12. GPDMA1 autonomous mode and wake-up in low-power modes

Feature Low-power modes

Autonomous mode and wake-up GPDMA1 in Sleep, Stop 0 and Stop 1 modes

3.18 Low-power direct memory access controller (LPDMA)

The LPDMA controller is a bus master and system peripheral. The LPDMA is used to
perform programmable data transfers between memory-mapped peripherals and/or
memories via linked-lists, upon the control of an off-loaded CPU.
The LPDMA main features are:
• Single bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a 4-grade programmed priority at channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, or
half-transfer complete, or data transfer error, or user setting error, and/or update
linked-list item error, or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event

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• Four concurrent DMA channels:

– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
padding or truncation, sign extension and left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive
single transfers
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting and event flags
• TrustZone support
– Support for secure and nonsecure DMA transfers, independently at a first channel
level, and independently at a source/destination and link sub-levels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port

Table 13. LPDMA1 channels implementation and usage

Hardware parameters
Channel
Features
x dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 3) is implemented with:

x = 0 to 3 0 0 – no FIFO. Only a single source transfer cell is internally registered.
– fixed/contiguously incremented addressing

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Table 14. LPDMA1 autonomous mode and wake-up in low-power modes

Feature Low-power modes

Autonomous mode and wake-up LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes

3.19 Interrupts and events

3.19.1 Nested vectored interrupt controller (NVIC)

The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 114
maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and nonsecure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.19.2 Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event
inputs. It provides wake-up requests to the power control, and generates an interrupt
request to the CPU NVIC and events to the CPU event input. For the CPU an additional
event generation block (EVG) is needed to generate the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI multiplexer I/O port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI I/O port selection

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3.20 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.

3.21 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
The CORDIC main features are:
• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root,
natural logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA

3.22 Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a MAC
(multiplier/accumulator) unit, together with address generation logic that allows it to index
vector elements held in local memory.
The unit includes support for circular buffers on input and output, that allows digital filters to
be implemented. Both finite and infinite impulse response filters can be done.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
• 16 x 16-bit multiplier
• 24 + 2-bit accumulator with addition and subtraction
• 16-bit input and output data

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• 256 x 16-bit local memory

• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output buffers can be circular
• Filter functions: FIR, IIR (direct form 1)
• Vector functions: dot product, convolution, correlation
• AHB slave interface
• DMA read and write data channels

3.23 Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with
the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and
an interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error

3.23.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two nonsecure area can be configured thought the TZSC MPCWM1 controller with
a granularity of 64 Kbytes.

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The OCTOSPI registers can be configured as secure through the TZSC controller.

3.24 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as
a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may
require the application to re-configure and recenter the output clock phase with the received
data.
The delay block main features are:
• Input clock frequency ranging from 25 to 160 MHz
• Up to 12 oversampling phases

3.25 Analog-to-digital converter (ADC1 and ADC4)

The devices embed two successive approximation analog-to-digital converters.

Table 15. ADC features

ADC modes/features(1) ADC1 ADC4

Resolution 14 bits 12 bits

Maximum sampling speed for maximum resolution 2.5 Msps 2.5 Msps
Hardware offset calibration X X
Hardware linearity calibration X -
Single-ended inputs X X
Differential inputs X -
Injected channel conversion X -
Oversampling up to x1024 up to x256
Data register 32 bits 16 bits
DMA support X X
Parallel data output to MDF X -
Autonomous mode - X
Offset compensation X -
Gain compensation X -
Number of analog watchdogs 3 3
Wake-up from Stop mode - X(2)
1. X = supported.
2. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

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3.25.1 Analog-to-digital converter 1 (ADC1)

The ADC1 is a 14-bit ADC successive approximation analog-to-digital converter.
This ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 32-bit data register.
This ADC is mapped on the AHB bus to allow fast data handling. The analog watchdog
features allow the application to detect if the input voltage goes outside the user-defined
high or low thresholds.
A built-in hardware over sampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
The ADC1 main features are:
• High-performance features
– 14-, 12-, 10- or 8-bit configurable resolution
– A/D conversion time independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Management of single-ended or differential inputs (programmable per channels)
– Fast data handling thanks to the AHB slave bus interface
– Self-calibration (both offset and linearity)
– Channel-wise programmable sampling time
– Flexible sampling time control
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Fast context switching thanks to the hardware assistant that prepares the context
of the injected channels
– Data alignment with in-built data coherency
– Data can be managed by GPDMA for regular channel conversions with FIFO
– Data can be routed to MDF for post processing
– Four dedicated data registers for the injected channels
• Oversampler
– 32-bit data register
– Oversampling ratio adjustable from 2 to 1024
– Programmable data right and left shift
• Data preconditioning
– Gain compensation
– Offset compensation
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Slow bus frequency application while keeping optimum ADC performance
– Automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)

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• ADC features an external analog input channel:

– Up to 17 channels from dedicated GPIO pads
• Three additional internal dedicated channels:
– One channel for internal reference voltage (VREFINT)
– One channel for internal temperature sensor (VSENSE)
– One channel for VBAT monitoring channel (VBAT/4)
• Start-of-conversion can be initiated:
– by software for both regular and injected conversions
– by hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions
• Conversion modes
– Single mode: the ADC converts a single channel. The conversion is triggered by
a special event.
– Scan mode: the ADC scans and converts a sequence of channels.
– Continuous mode: the ADC converts continuously selected inputs.
– Discontinuous mode: the ADC converts a subset of the conversion sequence.
• Interrupt generation when the ADC is ready, at end of sampling, end of conversion
(regular or injected), end of sequence conversion (regular or injected), analog
watchdog 1, 2 or 3 or when an overrun event occurs
• Three analog watchdogs
– Filtering to ignore out-of-range data
• ADC input range: VSSA < VIN < VREF+
Note: The ADC1 analog block clock frequency must be between 5 MHz and 55 MHz.

3.25.2 Analog-to-digital converter 4 (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to
21 multiplexed channels allowing it to measure signals from 15 external and six internal
sources. A/D conversion of the various channels can be performed in Single, Continuous,
Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or
right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.
A built-in hardware oversampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
The ADC4 main features are:
• High performance
– 12-, 10-, 8- or 6-bit configurable resolution
– A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion
times obtained by lowering resolution
– Self-calibration
– Programmable sampling time

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– Data alignment with built-in data coherency

– DMA support
• Low-power
– HCLK frequency reduced for low-power operation while still keeping optimum
ADC performance
– Wait mode: ADC overrun prevented in applications with low frequency HCLK
– Auto-off mode: ADC automatically powered off except during the active
conversion phase, dramatically reducing the ADC power consumption
– Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is
automatically switched on when a trigger occurs to start conversion, and it is
automatically switched off after conversion. Data are transfered in SRAM
with DMA.
– ADC4 interrupts wake up the device from Stop 0, Stop 1 and Stop 2 modes.
• Analog input channels
– Up to 19 external analog inputs
– One channel for the internal temperature sensor (VSENSE)
– One channel for the internal reference voltage (VREFINT)
– One channel for the internal digital core voltage (VCORE)
– One channel for monitoring the external VBAT power supply pin
– Connection to two DAC internal channels
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)
• Conversion modes
– Conversion of a single channel or scan of a sequence of channels
– Selected inputs converted once per trigger in Single mode
– Selected inputs converted continuously in Continuous mode
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events, with wake-up from Stop
capability
• Analog watchdog
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256
– Programmable data shift up to 8 bits
• ADC supply requirements: 1.62 to 3.6 V
• ADC input range: VSSA < VIN < VREF+
Note: The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.

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3.25.3 Temperature sensor

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC1 and ADC4 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.

Table 16. Temperature sensor calibration values

Calibration
Description Memory address
value name

Temperature sensor 14-bit raw data acquired by ADC1

TS_CAL1 0x0BFA 0710 - 0x0BFA 0711
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
Temperature sensor 14-bit raw data acquired by ADC1
TS_CAL2 0x0BFA 0742 - 0x0BFA 0743
at 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

3.25.4 Internal voltage reference (VREFINT)

The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparators.
The VREFINT is internally connected to ADC1 and ADC4 input channels.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.

Table 17. Internal voltage reference calibration values

Calibration value name Description Memory address

14-bit raw data acquired by ADC1

VREFINT_CAL 0x0BFA 07A5 - 0x0BFA 07A6
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)

3.25.5 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC1 or ADC4 input channel. As the VBAT voltage may be higher than the VDDA, and thus
outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
four. As a consequence, the converted digital value is a quarter of the VBAT voltage.

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3.26 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low-power mode, the sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Autonomous mode to reduce the power consumption for the system
• Voltage reference input

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3.27 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the
VREF+ pin.

Figure 6. VREFBUF block diagram

VREFINT +
VREF+

VSSA
MSv64430V2

The internal voltage reference buffer supports four voltages: 1.5 V, 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.

3.28 Comparator (COMP)

The devices embed one rail-to-rail comparator with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low power) and with selectable
output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4)
The comparator can wake up from Stop 0, Stop 1 and Stop 2 modes, generate interrupts
and breaks for the timers.

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3.29 Operational amplifier (OPAMP)

The devices embed one operational amplifier with external or internal follower routing and
PGA capability.
The operational amplifier features:
• Low-input bias current
• Low-offset voltage
• Low-power mode
• Rail-to-rail input

3.30 Multi-function digital filter (MDF) and audio digital filter (ADF)
The table below lists the set of features implemented into the MDF and the ADF.

Table 18. MDF features

MDF modes/features(1) ADF1 MDF1
Number of filters (DFLTx) and serial interfaces (SITFx) 1 2
ADF_CKI0 / MDF_CKIy connected to pins - X
Sound activity detection (SAD) X -
RXFIFO depth (number of 24-bit words) 4 4
ADC connected to ADCITF1 - ADC1
ADC connected to ADCITF2 - -
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break) - X
Main path with CIC4, CIC5 X X
Main path with CIC1,2, 3 or FastSinc - X
RSFLT, HPF, SAT, SCALE, DLY, Discard functions X X
Autonomous in Stop mode X(2) X(3)
1. X = supported.
2. Stop 0, Stop 1 and Stop 2 modes only.
3. Stop 0 and Stop 1 modes only.

3.30.1 Multi-function digital filter (MDF)

The MDF is a high-performance module dedicated to the connection of external sigma-delta
(Σ∆) modulators. It is mainly targeted for the following applications:
• audio capture signals
• motor control
• metering
The MDF features two digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible
digital processing options to offer up to 24-bit final resolution.
The DFLTx of the MDF also include the filters of the ADF (audio digital filter).
The MDF can receive, via its serial interfaces, streams coming from various digital sensors.

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The MDF supports the following standards allowing the connection of various ΣΔ modulator
sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX (bitstream matrix) allows the connection of any incoming bitstream to any
filter.
The MDF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks.In addition it is
possible to insert a high-pass filter or DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio, integrator length. The
maximum output data resolution is up to 24 bits. There are two conversion modes: single
conversion and continuous modes. The data can be automatically stored in a system RAM
buffer through DMA, thus reducing the software overhead.
A flexible trigger interface can be used to control the conversion start. This timing control
can trigger simultaneous conversions or insert a programmable delay between conversions.
The MDF features an OLD (out-off limit detectors) function. There is one OLD for each
digital filter chain. Independent programmable thresholds are available for each OLD,
making it very suitable for over-current detection.
A SCD (short circuit detector) is also available for every selected bitstream. The SCD is able
to detect a short-circuit condition with a very short latency. Independent programmable
thresholds are offered in order to define the short circuit condition.
All the digital processing is performed using only the kernel clock. The MDF requests the
bus interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The MDF main features are:
• AHB interface
• Two serial digital inputs:
– configurable SPI interface to connect various digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
• Two common clock input/output for Σ∆ modulators
• Flexible BSMX for connection between filters and digital inputs
• Two inputs to connect the internal ADCs
• Two flexible digital filter paths, including:
– A configurable CIC filter:
- Can be split into two CIC filters: high-resolution filter and out-off limit detector
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset

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– An offset error cancellation

– Gain control
– Saturation blocks
– An out-off limit detector
• Short-circuit detector
• Clock absence detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Break generation on out-of limit or short-circuit detector events
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services

3.30.2 Audio digital filter (ADF)

The ADF is a high-performance module dedicated to the connection of external Σ∆
modulators. It is mainly targeted for the following applications:
• audio capture signals
• metering
The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with
flexible digital processing options to offer up to 24-bit final resolution.
The DLFT0 of the ADF is a subset of the digital filters included into the MDF.
The ADF serial interface supports several standards allowing the connection of various Σ∆
modulator sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX allows the connection of any incoming bitstream to any filter.
The ADF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is
possible to insert a high-pass filter or a DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio. The maximum output data
resolution is up to 24 bits. There are two conversion modes: single conversion and
continuous modes. The data can be automatically stored in a system RAM buffer through
DMA, thus reducing the software overhead.
A SAD (sound activity detector) is available for the detection of “speech-like” signals. The
SAD is connected at the output of DFLT0. Several parameters can be programmed to adjust
properly the SAD to the sound environment. The SAD can strongly reduce the power
consumption by preventing the storage of samples into the system memory as long as the
observed signal does not match the programmed criteria.
A flexible trigger interface can be used to control the start of conversion of the ADF.

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All the digital processing is performed using only the kernel clock. The ADF requests the bus
interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The ADF main features are:
• AHB interface
• One serial digital input:
– Configurable SPI interface to connect various digital sensors
– Configurable Manchester coded interface support
– Compatible with PDM interface to support digital microphones
• Two common clocks input/output for Σ∆ modulators
• Flexible BSMX for connection between filters and digital inputs
• One flexible digital filter path, including:
– A configurable CIC filter:
- Can be configured in Sinc4 filter
- Can be configured in Sinc5 filter
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– Gain control
– Saturation blocks
• Clock absence detector
• Sound activity detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Autonomous mode in Stop 0, Stop 1 and Stop 2 modes
• Wake-up from Stop with all interrupts
• DMA can be used to read the conversion data
• Interrupts services

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3.31 Digital camera interface (DCMI)

The DCMI is a synchronous parallel interface able to receive a high-speed data flow from
an external 8-, 10-, 12-, or 14-bit CMOS camera module. It supports different data formats:
YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black and white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing such as resizing is performed in the camera module.
The DCMI features are:
• 8-, 10-, 12-, or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw Bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG

3.32 Parallel synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the
same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.33 Touch sensing controller (TSC)

The TSC provides a simple solution to add capacitive sensing functionality to any
application. A capacitive sensing technology is able to detect finger presence near
an electrode that is protected from direct touch by a dielectric (such as glass or plastic). The
capacitive variation introduced by the finger (or any conductive object) is measured using
a proven implementation based on a surface charge transfer acquisition principle.

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The TSC is fully supported by the STMTouch touch sensing firmware library that is free to
use and allows touch sensing functionality to be implemented reliably in the end application.
The TSC main features are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 20 capacitive sensing channels
• Up to eight capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.

3.34 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and
an internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct
a non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)

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3.35 Secure advanced encryption standard hardware accelerator

(SAES)
and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197,
Nov 2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB and CBC
chaining is supported by both SAES and AES, while CTR, CCM, GCM and GMAC chaining
is only supported by the AES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
• 256-bit software key, written by the application in the key registers (write only)
• 256-bit derived hardware unique key (DHUK), computed inside the SAES engine from
a non-volatile OTP based root hardware unique key (RHUK)
• 256-bit boot hardware key (BHK), stored in tamper-resistant secure backup registers,
written by a secure code during boot. Once written, this key cannot be read or write by
any application until the next product reset.
• XOR of DHUK (provisioned chip secret) and BHK (software secret)
DHUK, BHK and their XOR are not visible by any software (even secure).
Note: 128-bit key size can also be selected.
BHK key is cleared in case of tamper or RDP regression.
When the SAES is secure (respectively nonsecure), DHUK secure (respectively nonsecure)
is used.
The SAES peripheral is connected by hardware to the true random number generator RNG
(for side-channel resistance).
The SAES and AES peripherals support:
• Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
• 128-bit data block processing
• Support for cipher keys length of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode

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• Additional chaining modes supported by AES only:

– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128-bit or 256-bit key
• 51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128-bit or 256-bit key
• Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
• 256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
• 128-bit registers for storing initialization vectors (four 32-bit registers)
• One 32-bit input buffer and one 32-bit output buffer
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data swapping logic to support 1-, 8-, 16- or 32-bit data
• Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)
• SAES additional features:
– Security context enforcement for keys
– Hardware secret key encryption/ decryption (wrapped key mode) and sharing with
faster AES peripheral (Shared key mode)
– Protection against differential power analysis (DPA) and related side-channel
attacks
– Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be
XORed together
On top of standard AES encryption and decryption with a key loaded by software, SAES
peripheral allows the following advanced use cases:
• Allow or deny the sharing of a key between a secure and a nonsecure application,
enforced by hardware
• Encrypt once a key using side-channel resistant AES, then share it to a faster AES
engine by decrypting it (Shared key mode)
• On-chip encrypted storage using chip-unique secret DHUK
• Transport key generation by encrypting the device public unique ID with the application
secret BHK
• Binding of device secure storage keys, using the silicon unique secret key (DHUK)
XORed with the boot secret key (BHK). If BHK is lost, the whole device secure storage
is lost.
Note: Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore
when a security breach is detected.

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Table 19. AES/SAES features

AES/SAES modes/features(1) AES SAES

ECB, CBC chaining X X

CTR, CCM, GCM chaining X -
AES 128-bit ECB encryption in cycles 51 528
DHUK and BHK key selection - X
Side-channel attacks resistance - X
Shared key between SAES and AES X
1. X = supported.

3.36 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits
digests for the MD5 algorithm.
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 66 clock cycles for processing one 512-bit block of data using MD5 algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message:
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)

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• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA

3.37 On-the-fly decryption engine (OTFDEC)

The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request
address information, for example execute-in-place of a code stored encrypted. Four
independent and non-overlapping encrypted regions can be defined in OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency.
As consequence, each time the content of one encrypted region is changed the entire
region must be re-encrypted with a different cryptographic context (key or initialization
vector). This constraint makes OTFDEC suitable to decrypt read-only data or code, stored in
external NOR Flash.
Note: When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the Flash
memory using the Memory-mapped mode of the Flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by
a secure host.
The OTFDEC main features are the following:
• On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations
(single or multiple)
– Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
– Support for any read size
– Physical address of the reads is used for the encryption/decryption
• Up to 4 independent encrypted regions
– Granularity of the region definition: 4096 bytes
– Region configuration write locking mechanism
– Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time
an encryption is performed by the application.
• Encryption keys confidentiality and integrity protection
– Write-only registers, with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for OCTOSPI prefetching mechanism
• Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)

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• AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
• Secure only programming if TrustZone security is enabled
• Encryption mode

3.38 Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically
those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
– RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• Protection against differential power analysis (DPA) and related side-channel attacks.

3.39 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, four low-power timers, two watchdog timers and two SysTick timers.
The table below compares the features of the advanced control, general-purpose and basic
timers.

Table 20. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels

Any integer
Advanced Up, down,
TIM1, TIM8 16 bits between 1 and Yes 4 3
control Up/down
65536
Any integer
General- TIM2, TIM3, Up, down,
32 bits between 1 and Yes 4 No
purpose TIM4, TIM5 Up/down
65536

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Table 20. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels

Any integer
General-
TIM15 16 bits Up between 1 and Yes 2 1
purpose
65536
Any integer
General- TIM16,
16 bits Up between 1 and Yes 1 1
purpose TIM17
65536
Any integer
Basic TIM6, TIM7 16 bits Up between 1 and Yes 0 No
65536

3.39.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100%)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.

3.39.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,

TIM16,TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32U545xx devices (see Table 20 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
• TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other
general-purpose timers via the Timer Link feature for synchronization or event
chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.

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• TIM15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has two channels and one complementary channel
– TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.

3.39.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.

3.39.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4)

The devices embed four low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by HSI16, MSI, LSE, LSI or an external clock. They
are able to wake up the system from Stop mode.
LPTIM1, LPTIM3, and LPTIM4 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI16, MSIK (LPTIM1, LPTIM3, LPTIM4 only) or
APB clock (LPTIM2 only)
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to 2 independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on 10 events

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• DMA request generation on the following events:

– Update event
– Input capture

3.39.5 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions. It uses internal connections with
TIM16 and TIM17.

3.39.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as
a watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.

3.39.7 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen
in Debug mode.

3.39.8 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, nonsecure instance
When TrustZone is disabled, only one SysTick timer is available. This timer (secure or
non-secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

3.40 Real-time clock (RTC), tamper and backup registers

3.40.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter

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• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure
configuration
– Alarm A, alarm B, wake-up timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake-up
the device from the low-power modes.

3.40.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and eleven internal tampers. The external tamper
pins can be configured for edge detection, or level detection with or without filtering, or
active tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the backup domain that
remains powered-on by VBAT when the VDD power is switched off.

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• Up to 8 tamper pins for 8 external tamper detection events:

– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
• 11 internal tamper events to protect against transient or environmental perturbation
attacks:
– Backup domain voltage monitoring
– Temperature monitoring
– LSE monitoring
– RTC calendar overflow
– JTAG/SWD access if RDP different from 0
– Monotonic counter overflow
– Cryptographic peripherals fault (RNG, SAES, AES, PKA)
– Independent watchdog reset when tamper flag is already set
– 3 ADC4 watchdogs
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate a RTC time stamp event.
• TrustZone support:
– Tamper secure or nonsecure configuration
– Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read nonsecure area
- 1 read/write nonsecure area
– Boot secret key (BHK) only usable by secure AES peripheral, stored in backup
registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter

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3.41 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Table 21 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with
ACK control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Autonomous functionality in Stop modes with wake-up from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 21. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 Kbit/s) X X X X

Fast-mode (up to 400 Kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Autonomous in Stop 0, Stop 1 mode with wake-up capability X X X X
Autonomous in Stop 2 mode with wake-up capability - - X -
1. X: supported

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3.42 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed two universal synchronous receiver transmitters (USART1, USART3),
two universal asynchronous receiver transmitters (UART4, UART5) and one low-power
universal asynchronous receiver transmitter (LPUART1).

Table 22. USART, UART, and LPUART features

USART modes/features(1) USART1/3 UART4/5 LPUART1

Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous SPI mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
(2)
Dual-clock domain and wake-up from Stop mode X X(2) X(3)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
Autonomous mode X X X
1. X = supported.
2. Wake-up supported from Stop 0 and Stop 1 modes.
3. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

3.42.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.

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High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous SPI master/slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode
• Smartcard mode
– Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation

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• Support for Modbus communication

– Timeout feature
– CR/LF character recognition

3.42.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for
FIFO states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte

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• Four error detection flags:

– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from Stop capability

3.43 Serial peripheral interface (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex and simplex synchronous, serial communication
with external devices.
The interface can be configured as master or slave and can operate in multi-slave or
multi-master configurations. The device configured as master provides communication
clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be
applied optionally just to setup communication with concrete slave and to assure it handles
the data flow properly. The Motorola® data format is used by default, but some other specific
modes are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola® and Texas Instruments® formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode

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• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Autonomous functionality in Stop modes (handling of the transaction flow and required
clock distribution) with wake-up from stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.

Table 23. SPI features

SPI1, SPI2 SPI3
SPI feature
(full feature set instances) (limited feature set instance)

Data size Configurable from 4 to 32-bit 8/16-bit

CRC polynomial length CRC polynomial length
CRC computation
configurable from 5 to 33-bit configurable from 9 to 17-bit
Size of FIFOs 16x 8-bit 8x 8-bit
Number of transfered data Unlimited, expandable Up to 1024, no data counter
Autonomous in Stop 0, Stop 1 mode
Yes Yes
with wake-up capability
Autonomous in Stop 2 mode with
No Yes
wake-up capability

3.44 Serial audio interfaces (SAI)

The devices embed one SAI. Refer to Table 24: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and
SPDIF out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable

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• Frame synchronization active level configurable (offset, bit length, level)

• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
– Codec not ready for the AC’97 mode in reception
• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.

Table 24. SAI implementation

SAI features(1) SAI1

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X
Stereo/mono audio frame capability. X
16 slots X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X
FIFO size X (8 words)
SPDIF X
PDM X
1. X: supported

3.45 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SDMMC (SD/SDIO embedded MultiMediaCard e•MMC™ host interface) provides
an interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.

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The SDMMC features include the following:

• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.

Table 25. SDMMC features

SDMMC modes/features(1) SDMMC1

Variable delay (SDR104, HS200) X

SDMMC_CKIN X
SDMMC_CDIR, SDMMC_D0DIR X
SDMMC_D123DIR X
1. X = supported.

3.46 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support

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• Improved acceptance filtering

• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support

3.47 USB full speed (USB)

USB main features
• USB specification version 2.0 full-speed compliant
• Host and device functions
• 2048 bytes of dedicated SRAM data buffer memory with 32-bit access
• USB clock recovery
• Configurable number of endpoints from 1 to 8
• Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted
(NRZI) encoding/decoding, and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB suspend/resume operations
• Frame-locked clock pulse generation
• USB 2.0 Link power management support
• Battery charging specification revision 1.2 support in device

3.48 Development support

3.48.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.48.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.

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Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.

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4 Pinout, pin description, and alternate functions

4.1 Pinout/ballout schematics

Figure 7. LQFP48_SMPS pinout

PH3-BOOT0
VDD11

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 VDD
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS

VSS
PA3
PA4
PA5
PA6
PA7

VDD11

MSv62928V1

1. The above figure shows the package top view.

Figure 8. LQFP48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7

MSv62922V1

1. The above figure shows the package top view.

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Figure 9. UFQFPN48_SMPS pinout

PH3-BOOT0
VDD11

PA15
PA14
VDD
VSS

PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 VDD
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
VLXSMPS
VDDSMPS
VSSSMPS

VSS
PA3
PA4
PA5
PA6
PA7

VDD11
MSv63695V3

1. The above figure shows the package top view.

Figure 10. UFQFPN48 pinout

PH3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDD
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PH0-OSC_IN 5 32 PA11
PH1-OSC_OUT 6 31 PA10
NRST 7
UFQFPN48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2

VSS
PB10
VCAP

VDD
PA3
PA4
PA5
PA6
PA7

MSv63696V2

1. The above figure shows the package top view.

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Figure 11. LQFP64_SMPS pinout

PH3-BOOT0
VDD11

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS

VLXSMPS

VSS
VDD

PB0
PB1
PB2
PB10

VDDSMPS
VSSSMPS
PA3

PA4
PA5
PA6
PA7

VDD11
MSv62929V1

1. The above figure shows the package top view.

Figure 12. LQFP64 pinout

PH3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3

PA4
PA5
PA6
PA7

MSv62923V1

1. The above figure shows the package top view.

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Figure 13. UFBGA64_SMPS ballout

1 2 3 4 5 6 7 8

A VDD VDD11 PH3-BOOT0 PB6 PB3 PD2 PC10 VDD

B VBAT VSS PC13 PB4 PC11 PC12 VSS VDDUSB

PC14- PC15-
C OSC32_IN OSC32_OUT
PB8 PA15 PA14 PA13 PA12 PA11

PH1-
D PH0-OSC_IN
OSC_OUT
PB7 PB5 PA10 PA9 PA8 PC9

E NRST PC0 PC1 PC2 PA0 PB14 PC7 PC8

F VSSA PC3 PA1 PA4 PA6 PB10 PB15 PC6

G VDDA PA2 PA5 PB2 PB1 VSSSMPS VSS PB13

H VDD PA3 PA7 PB0 VLXSMPS VDDSMPS VDD11 VDD

MSv70560V1

1. The above figure shows the package top view.

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Figure 14. UFBGA64 ballout

1 2 3 4 5 6 7 8

PC14-
A OSC32_IN
PC13 PB9 PB4 PB3 PA15 PA14 PA13

PC15-
B OSC32_OUT
VBAT PB8 PH3-BOOT0 PD2 PC11 PC10 PA12

C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11

PH1-
D OSC_OUT
VDD PB6 VSS VSS VSS PA8 PC9

E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8

F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14

G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13

H VDDA PA1 PA4 PA7 PC4 PC5 VCAP PB12

MSv70559V1

1. The above figure shows the package top view.

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Figure 15. WLCSP56_SMPS ballout

1 3 5 7 9 11 13
2 4 6 8 10 12 14

A VDD PA15 PA14 PB5 PB8 VDD11 VDD

B VSS PB3 PB4 PH3-BOOT0 VSS PE4 VBAT

C PA11 PA12 PA13 PB6 PB9 PE3 PC14-OSC32_IN

PC15-
D PA9 PA10 PA3 PB7 PE5 PC13
OSC32_OUT

E PB14 PB12 PA8 PA2 NRST PH1-OSC_OUT PH0-OSC_IN

F PB15 PB1 PB0 PA5 PA0 VDDA VSSA

G PB13 VSS VSSSMPS PB2 PA6 PA4 PA1

H VDD VDD11 VDDSMPS VLXSMPS PA7 VDD VSS

MSv70557V2

1. The above figure shows the package top view.

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Figure 16. WLCSP72_SMPS ballout

2 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15

PH3-
A VDD PG10 PG14 VDDIO2 PB4
BOOT0
VDD11 VDD

B VDDUSB VSS PG9 VSS PG15 PB6 VSS VBAT

PC14-
C PA11 PA12 PG11 PG13 PB3 PB8 PC13
OSC32_IN

PC15-
D VDDIO2 VSS PA13 PA15 PG12 PB5 PB7 OSC32_
OUT

PH0-
E PG8 PA8 PA10 PA14 PA5 PA1 NRST
OSC_IN

PH1-
F PG4 PG5 PG6 PG7 PA9 PA2 PC1
OSC_OUT

G PB14 PB13 PG2 PB1 PB0 PA3 VDDA VSSA

H PB15 VSS VSSSMPS PG3 PB10 PA6 PA4 PA0

J VDD VDD11 VDDSMPS VLXSMPS PB2 PA7 VDD VSS

MSv70558V1

1. The above figure shows the package top view.

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Figure 17. LQFP100_SMPS ballout

PH3-BOOT0
VDD11

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD3
PD2
PD4
PD6
PD5
PD7
PB4
PB3
PB6
PB5
PB7
PB9
PB8
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSSSMPS
VDDSMPS
VLXSMPS
PB10
PE14
PE15
PE13
PE12
PE10
PE8
PE9
PE7
PB2
PB1
PB0
VDD
VSS

VDD11
PB11
PE11
PA7
PA6
PA5
PA4

MSv62930V1

1. The above figure shows the package top view.

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Figure 18. LQFP100 pinout

PH3-BOOT0

PC10
PC12
PC11

PA14
PA15
VDD
VSS

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
VCAP
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PC4
VDD
VSS

PE11
PA7
PA6
PA5
PA4
PA3

MSv62924V1

1. The above figure shows the package top view.

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Figure 19. UFBGA100_SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12

PH3-
A PB9 PE0
BOOT0
PB7 PB6 PB4 PD7 PD5 PD4 PD2 PD0 PC10

B PE2 PE3 PE4 PB8 PB5 PB3 VDD PD6 PD3 PD1 PC11 PA15

C VBAT PE6 VDD VSS VDD11 VSS PC12 VDD PA14 PA13

PC14- PC15-
D OSC32_ OSC32_ PE5 VSS PA12 PA11
IN OUT

PH1-
PH0-
E OSC_IN
OSC_ PC13 VDDUSB PA9 PA10
OUT

F NRST PC0 PC9 PA8

G PC1 PC2 PC7 PC8

H VREF+ VSSA PC3 PD12 PD15 PC6

J VDDA PA1 PA0 PD8 PD13 PD14

K PA2 PA3 VSS VDD PE7 PB11 VDD11 VDD PD9 PD11

VSS
L PA4 PA5 PB0 PB2 PE9 PE11 PE13 PE15
SMPS
VSS PB13 PD10

VLX VDD
M PA6 PA7 PB1 PE8 PE10 PE12 PE14 PB10
SMPS SMPS
PB14 PB15

MSv70561V1

1. The above figure shows the package top view.

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Figure 20. UFBGA100 ballout

1 2 3 4 5 6 7 8 9 10 11 12

PH3-
A PE3 PE1 PB8
BOOT0
PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

C PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDDUSB PA10

PC14-
D OSC32_ PE6 VSS PA9 PA8 PC9
IN

PC15-
E OSC32_ VBAT VSS PC8 PC7 PC6
OUT

PH0-
F OSC_IN
VSS VSS VSS

PH1-
G OSC_ VDD VDD VDD
OUT

H PC0 NRST VDD PD15 PD14 PD13

J VSSA PC1 PC2 PD12 PD11 PD10

K VREF- PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13

L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 VCAP PB12

M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

MSv70562V1

1. The above figure shows the package top view.

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4.2 Pin description

Table 26. Legend/abbreviations used in the pinout table
Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
Bidirectional reset pin with embedded weak pull-up
RST
resistor
Option for TT or FT I/Os(1)
_a I/O with analog switch function supplied by VDDA

I/O structure _f I/O Fm+ capable

_h I/O with high-speed low-voltage mode
_o I/O with OSC32_IN/OSC32_OUT capability
_s I/O supplied only by VDDIO2
_t I/O with tamper function supplied by VSW
_u I/O with USB function supplied by VDDUSB
_v I/O very high-speed capable
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

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Table 27. STM32U545xx pin/ball definitions(1)
Pin number

UFBGA100 SMPS
UFQFPN48 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFBGA100
UFQFPN48

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

TRACECLK, TIM3_ETR,
SAI1_CK1, TSC_G7_IO1,
- - - - - 1 B1 - - - 1 B2 PE2 I/O FT_ha - -
LPGPIO1_P14, SAI1_MCLK_A,
EVENTOUT
TRACED0, TIM3_CH1,
OCTOSPI1_DQS, TSC_G7_IO2, TAMP_IN6/
- C11 - - - 2 B2 - - - 2 A1 PE3 I/O FT_hat -
DS14216 Rev 5

LPGPIO1_P15, SAI1_SD_B, TAMP_OUT3

EVENTOUT
TRACED1, TIM3_CH2, SAI1_D2,
WKUP1,

Pinout, pin description, and alternate functions

TSC_G7_IO3,
- B12 - - - 3 B3 - - - 3 B1 PE4 I/O FT_hat - TAMP_IN7/
DCMI_D4/PSSI_D4, SAI1_FS_A,
TAMP_OUT8
EVENTOUT
TRACED2, TIM3_CH3, SAI1_CK2,
WKUP2,
TSC_G7_IO4,
- D10 - - - 4 D3 - - - 4 C2 PE5 I/O FT_hat - TAMP_IN8/
DCMI_D6/PSSI_D6, SAI1_SCK_A,
TAMP_OUT7
EVENTOUT
TRACED3, TIM3_CH4, SAI1_D1, WKUP3,
- - - - - 5 C2 - - - 5 D2 PE6 I/O FT_ht - DCMI_D7/PSSI_D7, SAI1_SD_A, TAMP_IN3/
EVENTOUT TAMP_OUT6
1 B14 1 B1 B15 6 C1 1 1 B2 6 E2 VBAT S - - - VBAT
WKUP2,
(2) RTC_TS/
2 D12 2 B3 C14 7 E3 2 2 A2 7 C1 PC13 I/O FT (3) EVENTOUT RTC_OUT1,
TAMP_IN1/
101/307

TAMP_OUT2
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
102/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

PC14- (2)
3 C13 3 C1 C16 8 D1 3 3 A1 8 D1 OSC32_IN I/O FT_o (3) EVENTOUT OSC32_IN
(PC14)
PC15- (2)
4 D14 4 C2 D15 9 D2 4 4 B1 9 E1 OSC32_OUT I/O FT_o (3) EVENTOUT OSC32_OUT
(PC15)
- - - - - 10 L10 - - - 10 D3 VSS S - - - -
DS14216 Rev 5

- - - - - 11 B7 - - - 11 C4 VDD S - - - -
PH0-
5 E13 5 D1 E16 12 E1 5 5 C1 12 F1 OSC_IN I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-
6 E11 6 D2 F15 13 E2 6 6 D1 13 G1 OSC_OUT I/O FT - EVENTOUT OSC_OUT
(PH1)
7 E9 7 E1 E14 14 F1 7 7 E1 14 H2 NRST I/O RST - - NRST
LPTIM1_IN1, OCTOSPI1_IO7,
I2C3_SCL(boot), SPI2_RDY, ADC1_IN1,
- - 8 E2 - 15 F2 - 8 E3 15 H1 PC0 I/O FT_fha -
LPUART1_RX, SDMMC1_D5, ADC4_IN1
LPTIM2_IN1, EVENTOUT
TRACED0, LPTIM1_CH1,
SPI2_MOSI, I2C3_SDA(boot), ADC1_IN2,
- - 9 E3 F13 16 G1 - 9 E2 16 J2 PC1 I/O FT_fhav -

STM32U545xx
LPUART1_TX, OCTOSPI1_IO4, ADC4_IN2
SAI1_SD_A, EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

LPTIM1_IN2, SPI2_MISO,
ADC1_IN3,
- - 10 E4 - 17 G2 - 10 F2 17 J3 PC2 I/O FT_ha - MDF1_CCK1, OCTOSPI1_IO5,
ADC4_IN3
LPGPIO1_P5, EVENTOUT
LPTIM1_ETR, LPTIM3_CH1,
SAI1_D1, SPI2_MOSI, ADC1_IN4,
- - 11 F2 - 18 H3 - 11 G1 18 K2 PC3 I/O FT_ha -
OCTOSPI1_IO6, SAI1_SD_A, ADC4_IN4
LPTIM2_ETR, EVENTOUT
DS14216 Rev 5

8 F14 12 F1 G16 19 H2 8 12 F1 19 J1 VSSA S - - - -

- - - - - - - - - - 20 K1 VREF- S - - - -

Pinout, pin description, and alternate functions

- - - - - 20 H1 - - - 21 L1 VREF+ S - - - VREFBUF_OUT
9 F12 13 G1 G14 21 J1 9 13 H1 22 M1 VDDA S - - - -
TIM2_CH1, TIM5_CH1, OPAMP1_VINP,
TIM8_ETR, SPI3_RDY, ADC1_IN5,
10 F10 14 E5 H15 22 J3 10 14 G2 23 L2 PA0 I/O FT_hat - UART4_TX, OCTOSPI1_NCS, WKUP1,
AUDIOCLK, TIM2_ETR, TAMP_IN2/
EVENTOUT TAMP_OUT1
LPTIM1_CH2, TIM2_CH2, OPAMP1_VINM
TIM5_CH2, I2C1_SMBA, , ADC1_IN6,
11 G13 15 F3 E12 23 J2 11 15 H2 24 M2 PA1 I/O FT_hat - SPI1_SCK, UART4_RX, WKUP3,
OCTOSPI1_DQS, LPGPIO1_P0, TAMP_IN5/
TIM15_CH1N, EVENTOUT TAMP_OUT4
TIM2_CH3, TIM5_CH3,
COMP1_INP3,
SPI1_RDY, LPUART1_TX,
12 E7 16 G2 F11 24 K1 12 16 F3 25 K3 PA2 I/O FT_ha - ADC1_IN7,
OCTOSPI1_NCS, TIM15_CH1,
WKUP4/LSCO
103/307

EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
104/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

TIM2_CH4, TIM5_CH4,
SAI1_CK1, LPUART1_RX, OPAMP1_VOU
13 D6 17 H2 G12 25 K2 13 17 G3 26 L3 PA3 I/O TT_hav - OCTOSPI1_CLK, LPGPIO1_P1, T, ADC1_IN8,
SAI1_MCLK_A, TIM15_CH2, WKUP5
EVENTOUT
- H14 18 - J16 26 K3 - 18 C2 27 E3 VSS S - - - -
- H12 19 H1 J14 27 C3 - 19 E6 28 G11 VDD S - - - -
DS14216 Rev 5

OCTOSPI1_NCS,
ADC1_IN9,
SPI1_NSS(boot), SPI3_NSS,
ADC4_IN9,
14 G11 20 F4 H13 28 L1 14 20 H3 29 M3 PA4 I/O TT_ha - DCMI_HSYNC/PSSI_DE,
DAC1_OUT1,
SAI1_FS_B, LPTIM2_CH1,
WKUP2
EVENTOUT
CSLEEP, TIM2_CH1, TIM2_ETR, ADC1_IN10,
TIM8_CH1N, PSSI_D14, ADC4_IN10,
15 F8 21 G3 E10 29 L2 15 21 F4 30 K4 PA5 I/O TT_a -
SPI1_SCK(boot), USART3_RX, DAC1_OUT2,
LPTIM2_ETR, EVENTOUT WKUP6
CDSTOP, TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
DCMI_PIXCLK/PSSI_PDCK, ADC1_IN11,
16 G9 22 F5 H11 30 M1 16 22 G4 31 L4 PA6 I/O FT_ha - SPI1_MISO(boot), USART3_CTS, ADC4_IN11,
LPUART1_CTS, OCTOSPI1_IO3, WKUP7
LPGPIO1_P2, TIM16_CH1,
EVENTOUT

STM32U545xx
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

SRDSTOP, TIM1_CH1N,
TIM3_CH2, TIM8_CH1N,
ADC1_IN12,
I2C3_SCL, SPI1_MOSI(boot),
17 H10 23 H3 J12 31 M2 17 23 H4 32 M4 PA7 I/O FT_fha - ADC4_IN20,
USART3_TX, OCTOSPI1_IO2,
WKUP8
LPTIM2_CH2, TIM17_CH1,
EVENTOUT
COMP1_INM2,
USART3_TX, OCTOSPI1_IO7,
DS14216 Rev 5

- - - - - - - - 24 H5 33 K5 PC4 I/O FT_ha - ADC1_IN13,

EVENTOUT
ADC4_IN22
COMP1_INP1,

Pinout, pin description, and alternate functions

ADC1_IN14,
TIM1_CH4N, SAI1_D3, PSSI_D15, ADC4_IN23,
- - - - - - - - 25 H6 34 L5 PC5 I/O FT_at -
USART3_RX, EVENTOUT WKUP5,
TAMP_IN4/
TAMP_OUT5
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LPTIM3_CH1,
SPI1_NSS, USART3_CK, ADC1_IN15,
18 F6 24 H4 G10 32 L3 18 26 F5 35 M5 PB0 I/O TT_ha -
OCTOSPI1_IO1, LPGPIO1_P9, ADC4_IN18
COMP1_OUT, AUDIOCLK,
EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LPTIM3_CH2, COMP1_INM1,
MDF1_SDI0, USART3_RTS_DE, ADC1_IN16,
19 F4 25 G5 G8 33 M3 19 27 G5 36 M6 PB1 I/O FT_ha -
LPUART1_RTS_DE, ADC4_IN19,
OCTOSPI1_IO0, LPGPIO1_P3, WKUP4
105/307

LPTIM2_IN1, EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
106/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

LPTIM1_CH1, TIM8_CH4N, COMP1_INP2,

I2C3_SMBA, SPI1_RDY, ADC1_IN17,
- G7 26 G4 J10 34 L4 20 28 G6 37 L6 PB2 I/O FT_hat -
MDF1_CKI0, OCTOSPI1_DQS, WKUP1,
EVENTOUT RTC_OUT2
TIM1_ETR, SAI1_SD_B,
- - - - - 35 K5 - - - 38 M7 PE7 I/O FT_h - WKUP6
EVENTOUT
TIM1_CH1N, SAI1_SCK_B,
DS14216 Rev 5

- - - - - 36 M4 - - - 39 L7 PE8 I/O FT_h - WKUP7

EVENTOUT
TIM1_CH1, ADF1_CCK0,
- - - - - 37 L5 - - - 40 M8 PE9 I/O FT_hv - MDF1_CCK0, OCTOSPI1_NCLK, -
SAI1_FS_B, EVENTOUT
TIM1_CH2N, ADF1_SDI0,
- - - - - 38 M5 - - - 41 L8 PE10 I/O FT_hav - TSC_G5_IO1, OCTOSPI1_CLK, -
SAI1_MCLK_B, EVENTOUT
TIM1_CH2, SPI1_RDY,
- - - - - 39 L6 - - - 42 M9 PE11 I/O FT_ha - TSC_G5_IO2, OCTOSPI1_NCS, -
EVENTOUT
TIM1_CH3N, SPI1_NSS,
- - - - - 40 M6 - - - 43 L9 PE12 I/O FT_ha - TSC_G5_IO3, OCTOSPI1_IO0, -
EVENTOUT
TIM1_CH3, SPI1_SCK,
- - - - - 41 L7 - - - 44 M10 PE13 I/O FT_ha - TSC_G5_IO4, OCTOSPI1_IO1, -

STM32U545xx
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
- - - - - 42 M7 - - - 45 M11 PE14 I/O FT_h - SPI1_MISO, OCTOSPI1_IO2, -
EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

TIM1_BKIN, TIM1_CH4N,
- - - - - 43 L8 - - - 46 M12 PE15 I/O FT_h - SPI1_MOSI, OCTOSPI1_IO3, -
EVENTOUT
TIM2_CH3, LPTIM3_CH1,
I2C4_SCL, I2C2_SCL(boot),
SPI2_SCK, USART3_TX,
- - 27 F6 H9 44 M8 21 29 G7 47 L10 PB10 I/O FT_fhv - LPUART1_RX, TSC_SYNC, WKUP8
DS14216 Rev 5

OCTOSPI1_CLK, LPGPIO1_P4,
COMP1_OUT, SAI1_SCK_A,
EVENTOUT

Pinout, pin description, and alternate functions

TIM2_CH4, I2C4_SDA,
I2C2_SDA(boot), SPI2_RDY,
- - - - - 45 K8 - - - - - PB11 I/O FT_fh - -
USART3_RX, LPUART1_TX,
OCTOSPI1_NCS, EVENTOUT
20 H8 28 H5 J8 46 M9 - - - - - VLXSMPS S - - - -
21 H6 29 H6 J6 47 M10 - - - - - VDDSMPS S - - - -
22 G5 30 G6 H5 48 L9 - - - - - VSSSMPS S - - - -
- - - - - - - 22 30 H7 48 L11 VCAP S - - - -
23 H4 31 H7 J4 49 K9 - - - - - VDD11 S - - - -
24 G3 32 B2 H3 50 C4 23 31 D4 49 F11 VSS S - - - -
25 H2 33 A1 J2 51 K10 24 32 D2 50 G12 VDD S - - - -
107/307
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
108/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

TIM1_BKIN, I2C2_SMBA,
SPI2_NSS(boot), MDF1_SDI1,
USART3_CK,
- E3 - - - - - 25 33 H8 51 L12 PB12 I/O FT_hav - -
LPUART1_RTS_DE,
TSC_G1_IO1, OCTOSPI1_NCLK,
TIM15_BKIN, EVENTOUT
TIM1_CH1N, LPTIM3_IN1,
DS14216 Rev 5

I2C2_SCL, SPI2_SCK(boot),
26 G1 34 G8 G4 52 L11 26 34 G8 52 K12 PB13 I/O FT_fa - MDF1_CKI1, USART3_CTS, -
LPUART1_CTS, TSC_G1_IO2,
TIM15_CH1N, EVENTOUT
TIM1_CH2N, LPTIM3_ETR,
TIM8_CH2N, I2C2_SDA,
27 E1 35 E6 G2 53 M11 27 35 F8 53 K11 PB14 I/O FT_fa - SPI2_MISO(boot), -
USART3_RTS_DE, TSC_G1_IO3,
TIM15_CH1, EVENTOUT
RTC_REFIN, TIM1_CH3N,
LPTIM2_IN2, TIM8_CH3N,
28 F2 36 F7 H1 54 M12 28 36 F7 54 K10 PB15 I/O FT - WKUP7
SPI2_MOSI(boot), TIM15_CH2,
EVENTOUT
USART3_TX,
- - - - - 55 J10 - - - 55 K9 PD8 I/O FT_h - DCMI_HSYNC/PSSI_DE, -
EVENTOUT

STM32U545xx
LPTIM2_IN2, USART3_RX,
- - - - - 56 K11 - - - 56 K8 PD9 I/O FT_h - DCMI_PIXCLK/PSSI_PDCK, -
LPTIM3_IN1, EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

LPTIM2_CH2, USART3_CK,
- - - - - 57 L12 - - - 57 J12 PD10 I/O FT_ha - TSC_G6_IO1, LPTIM3_ETR, -
EVENTOUT
I2C4_SMBA, USART3_CTS,
- - - - - 58 K12 - - - 58 J11 PD11 I/O FT_ha - TSC_G6_IO2, LPTIM2_ETR, ADC4_IN15
EVENTOUT
TIM4_CH1, I2C4_SCL,
DS14216 Rev 5

- - - - - 59 H10 - - - 59 J10 PD12 I/O FT_fha - USART3_RTS_DE, TSC_G6_IO3, ADC4_IN16

LPTIM2_IN1, EVENTOUT

Pinout, pin description, and alternate functions

TIM4_CH2, I2C4_SDA,
TSC_G6_IO4, LPGPIO1_P6,
- - - - - 60 J11 - - - 60 H12 PD13 I/O FT_fha - ADC4_IN17
LPTIM4_IN1, LPTIM2_CH1,
EVENTOUT
TIM4_CH3, LPTIM3_CH1,
- - - - - 61 J12 - - - 61 H11 PD14 I/O FT_h - -
EVENTOUT
TIM4_CH4, LPTIM3_CH2,
- - - - - 62 H11 - - - 62 H10 PD15 I/O FT_h - -
EVENTOUT
(5)
- - - - G6 - - - - - - - PG2 I/O FT_hs SPI1_SCK, EVENTOUT -
(5)
- - - - H7 - - - - - - - PG3 I/O FT_hs SPI1_MISO, EVENTOUT -
- - - - F1 - - - - - - - PG4 I/O FT_hs (5)
SPI1_MOSI, EVENTOUT -

(5) SPI1_NSS, LPUART1_CTS,

- - - - F3 - - - - - - - PG5 I/O FT_hs -
EVENTOUT
OCTOSPI1_DQS, I2C3_SMBA,
109/307

(5)
- - - - F5 - - - - - - - PG6 I/O FT_hs SPI1_RDY, LPUART1_RTS_DE, -
EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
110/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

SAI1_CK1, I2C3_SCL,
(5) OCTOSPI1_DQS, MDF1_CCK0,
- - - - F7 - - - - - - - PG7 I/O FT_fhs -
LPUART1_TX, SAI1_MCLK_A,
EVENTOUT

(5) I2C3_SDA, LPUART1_RX,

- - - - E2 - - - - - - - PG8 I/O FT_fs -
EVENTOUT
- - - - D3 - - - - - - - VSS S - - - -
DS14216 Rev 5

- - - - D1 - - - - - - - VDDIO2 S - - - -
CSLEEP, TIM3_CH1, TIM8_CH1,
SDMMC1_D0DIR, TSC_G4_IO1,
- - 37 F8 - 63 H12 - 37 F6 63 E12 PC6 I/O FT_ha - -
DCMI_D0/PSSI_D0,
SDMMC1_D6, EVENTOUT
CDSTOP, TIM3_CH2, TIM8_CH2,
SDMMC1_D123DIR,
TSC_G4_IO2,
- - 38 E7 - 64 G11 - 38 E7 64 E11 PC7 I/O FT_ha - -
DCMI_D1/PSSI_D1,
SDMMC1_D7, LPTIM2_CH2,
EVENTOUT
SRDSTOP, TIM3_CH3,
TIM8_CH3, TSC_G4_IO3,
- - 39 E8 - 65 G12 - 39 E8 65 E10 PC8 I/O FT_ha - DCMI_D2/PSSI_D2, -
SDMMC1_D0, LPTIM3_CH1,

STM32U545xx
EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

TRACED0, TIM8_BKIN2,
TIM3_CH4, TIM8_CH4,
DCMI_D3/PSSI_D3,
- - 40 D8 - 66 F11 - 40 D8 66 D12 PC9 I/O FT_ha - -
TSC_G4_IO4, USB_NOE,
SDMMC1_D1, LPTIM3_CH2,
EVENTOUT
MCO, TIM1_CH1, SAI1_CK2,
DS14216 Rev 5

SPI1_RDY, USART1_CK,
29 E5 41 D7 E4 67 F12 29 41 D7 67 D11 PA8 I/O FT_hv - USB_SOF, TRACECLK, -
SAI1_SCK_A, LPTIM2_CH1,
EVENTOUT

Pinout, pin description, and alternate functions

TIM1_CH2, SPI2_SCK,
DCMI_D0/PSSI_D0,
30 D2 42 D6 F9 68 E11 30 42 C7 68 D10 PA9 I/O FT - -
USART1_TX(boot), SAI1_FS_A,
TIM15_BKIN, EVENTOUT
CRS_SYNC, TIM1_CH3,
LPTIM2_IN2, SAI1_D1,
31 D4 43 D5 E6 69 E12 31 43 C6 69 C12 PA10 I/O FT - DCMI_D1/PSSI_D1, -
USART1_RX(boot), SAI1_SD_A,
TIM17_BKIN, EVENTOUT
TIM1_CH4, TIM1_BKIN2,
32 C1 44 C8 C2 70 D12 32 44 C8 70 B12 PA11 I/O FT_u - SPI1_MISO, USART1_CTS, USB_DM(boot)
FDCAN1_RX, EVENTOUT
TIM1_ETR, SPI1_MOSI,
OCTOSPI1_NCS,
33 C3 45 C7 C4 71 D11 33 45 B8 71 A12 PA12 I/O FT_u - USB_DP(boot)
USART1_RTS_DE, FDCAN1_TX,
111/307

EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
112/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

PA13 JTMS/SWDIO, IR_OUT,

(4)
34 C5 46 C6 D5 72 C12 34 46 A8 72 A11 (JTMS/ I/O FT USB_NOE, SAI1_SD_B, -
SWDIO) EVENTOUT
- B2 47 G7 B3 - - - 47 D5 - - VSS S - - - -
- - 48 B8 B1 73 E10 - 48 E5 73 C11 VDDUSB S - - - -
35 - - - - 74 C8 35 - - 74 F12 VSS S - - - -
DS14216 Rev 5

36 A1 - H8 A2 75 C10 36 - - 75 G2 VDD S - - - -
JTCK/SWCLK, LPTIM1_CH1,
PA14
(4) I2C1_SMBA, I2C4_SMBA,
37 A5 49 C5 E8 76 C11 37 49 A7 76 A10 (JTCK/ I/O FT -
USB_SOF, SAI1_FS_B,
SWCLK)
EVENTOUT
JTDI, TIM2_CH1, TIM2_ETR,
PA15 (4) SPI1_NSS, SPI3_NSS,
38 A3 50 C4 D7 77 B12 38 50 A6 77 A9 I/O FT -
(JTDI) USART3_RTS_DE,
UART4_RTS_DE, EVENTOUT
TRACED1, LPTIM3_ETR,
ADF1_CCK1, SPI3_SCK,
USART3_TX(boot), UART4_TX,
- - 51 A7 - 78 A12 - 51 B7 78 B11 PC10 I/O FT_ha - TSC_G3_IO2, -
DCMI_D8/PSSI_D8,
LPGPIO1_P8, SDMMC1_D2,
EVENTOUT

STM32U545xx
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

LPTIM3_IN1, ADF1_SDI0,
DCMI_D2/PSSI_D2,
OCTOSPI1_NCS, SPI3_MISO,
- - 52 B5 - 79 B11 - 52 B6 79 C10 PC11 I/O FT_ha - USART3_RX(boot), UART4_RX, -
TSC_G3_IO3,
DCMI_D4/PSSI_D4,
SDMMC1_D3, EVENTOUT
DS14216 Rev 5

TRACED3, SPI3_MOSI,
USART3_CK, UART5_TX,
TSC_G3_IO4,
- - 53 B6 - 80 C9 - 53 C5 80 B10 PC12 I/O FT_hav - -
DCMI_D9/PSSI_D9,

Pinout, pin description, and alternate functions

LPGPIO1_P10, SDMMC1_CK,
EVENTOUT
TIM8_CH4N, SPI2_NSS,
- - - - - 81 A11 - - - 81 C9 PD0 I/O FT_h - -
FDCAN1_RX, EVENTOUT
SPI2_SCK, FDCAN1_TX,
- - - - - 82 B10 - - - 82 B9 PD1 I/O FT_h - -
EVENTOUT
TRACED2, TIM3_ETR,
USART3_RTS_DE, UART5_RX,
TSC_SYNC,
- - 54 A6 - 83 A10 - 54 B5 83 C8 PD2 I/O FT_h - -
DCMI_D11/PSSI_D11,
LPGPIO1_P7, SDMMC1_CMD,
LPTIM4_ETR, EVENTOUT
SPI2_SCK, DCMI_D5/PSSI_D5,
- - - - - 84 B9 - - - 84 B8 PD3 I/O FT_hv - SPI2_MISO, MDF1_SDI0, -
OCTOSPI1_NCS, EVENTOUT
113/307
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
114/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

SPI2_MOSI, MDF1_CKI0,
- - - - - 85 A9 - - - 85 B7 PD4 I/O FT_h - -
OCTOSPI1_IO4, EVENTOUT
SPI2_RDY, OCTOSPI1_IO5,
- - - - - 86 A8 - - - 86 A6 PD5 I/O FT_h - -
EVENTOUT
SAI1_D1, DCMI_D10/PSSI_D10,
SPI3_MOSI, MDF1_SDI1,
- - - - - 87 B8 - - - 87 B6 PD6 I/O FT_hv - -
OCTOSPI1_IO6, SAI1_SD_A,
DS14216 Rev 5

EVENTOUT
MDF1_CKI1, OCTOSPI1_IO7,
- - - - - 88 A7 - - - 88 A5 PD7 I/O FT_h - -
LPTIM4_OUT, EVENTOUT
OCTOSPI1_IO6, SPI3_SCK(boot),
(5)
- - - - B5 - - - - - - - PG9 I/O FT_hs USART1_TX, TIM15_CH1N, -
EVENTOUT
LPTIM1_IN1, OCTOSPI1_IO7,
- - - - A4 - - - - - - - PG10 I/O FT_hs (5)
SPI3_MISO(boot), USART1_RX, -
TIM15_CH1, EVENTOUT
LPTIM1_IN2, OCTOSPI1_IO5,
- - - - C6 - - - - - - - PG11 I/O FT_hs (5)
SPI3_MOSI, USART1_CTS, -
TIM15_CH2, EVENTOUT
LPTIM1_ETR, OCTOSPI1_NCS,
- - - - D9 - - - - - - - PG12 I/O FT_hs (5)
SPI3_NSS(boot), -
USART1_RTS_DE, EVENTOUT

STM32U545xx
(5) I2C1_SDA, SPI3_RDY,
- - - - C8 - - - - - - - PG13 I/O FT_fhs -
USART1_CK, EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

(5) LPTIM1_CH2, I2C1_SCL,

- - - - A6 - - - - - - - PG14 I/O FT_fhs -
EVENTOUT
- - - - B7 - - - - - - - VSS S - - - -
- - - - A8 - - - - - - - VDDIO2 S - - - -
LPTIM1_CH1, I2C1_SMBA,
(5) OCTOSPI1_DQS,
- - - - B9 - - - - - - - PG15 I/O FT_hs -
DS14216 Rev 5

DCMI_D13/PSSI_D13,
EVENTOUT
JTDO/TRACESWO, TIM2_CH2,

Pinout, pin description, and alternate functions

LPTIM1_CH1, ADF1_CCK0,
PB3
I2C1_SDA, SPI1_SCK,
39 B4 55 A5 C10 89 B6 39 55 A5 89 A8 (JTDO/ I/O FT_fa - COMP1_INP4
SPI3_SCK, USART1_RTS_DE,
TRACESWO)
CRS_SYNC, LPGPIO1_P11,
SAI1_SCK_B, EVENTOUT
NJTRST, LPTIM1_CH2,
TIM3_CH1, ADF1_SDI0,
I2C3_SDA, SPI1_MISO,
PB4 (4) SPI3_MISO, USART1_CTS,
40 B6 56 B4 A10 90 A6 40 56 A4 90 A7 I/O FT_fa COMP1_INP5
(NJTRST) UART5_RTS_DE, TSC_G2_IO1,
DCMI_D12/PSSI_D12,
LPGPIO1_P12, SAI1_MCLK_B,
TIM17_BKIN, EVENTOUT
115/307
 Table 27. STM32U545xx pin/ball definitions(1) (continued)
116/307

Pinout, pin description, and alternate functions

Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

LPTIM1_IN1, TIM3_CH2,
OCTOSPI1_NCLK, I2C1_SMBA,
SPI1_MOSI, SPI3_MOSI(boot),
USART1_CK, UART5_CTS,
41 A7 57 D4 D11 91 B5 41 57 C4 91 C5 PB5 I/O FT_hav - WKUP6
TSC_G2_IO2,
DCMI_D10/PSSI_D10,
SAI1_SD_B, TIM16_BKIN,
EVENTOUT
DS14216 Rev 5

LPTIM1_ETR, TIM4_CH1,
TIM8_BKIN2, I2C1_SCL(boot),
I2C4_SCL, USART1_TX, COMP1_INP6,
42 C7 58 A4 B11 92 A5 42 58 D3 92 B5 PB6 I/O FT_fa -
TSC_G2_IO3, WKUP3
DCMI_D5/PSSI_D5, SAI1_FS_B,
TIM16_CH1N, EVENTOUT
LPTIM1_IN2, TIM4_CH2,
TIM8_BKIN, I2C1_SDA(boot),
I2C4_SDA, USART1_RX, PVD_IN,
43 D8 59 D3 D13 93 A4 43 59 C3 93 B4 PB7 I/O FT_fhav -
UART4_CTS, TSC_G2_IO4, WKUP4
DCMI_VSYNC/PSSI_RDY,
TIM17_CH1N, EVENTOUT
44 B8 60 A3 A12 94 A3 44 60 B4 94 A4 PH3-BOOT0 I/O FT - EVENTOUT BOOT0
TIM4_CH3, SAI1_CK1, I2C1_SCL,
MDF1_CCK0, SPI3_RDY,

STM32U545xx
SDMMC1_CKIN,
45 A9 61 C3 C12 95 B4 45 61 B3 95 A3 PB8 I/O FT_fh - FDCAN1_RX(boot), WKUP5
DCMI_D6/PSSI_D6,
SDMMC1_D4, SAI1_MCLK_A,
TIM16_CH1, EVENTOUT
 Table 27. STM32U545xx pin/ball definitions(1) (continued)

STM32U545xx
Pin number

UFQFPN48 SMPS

UFBGA100 SMPS

I/O structure
WLCSP56 SMPS

WLCSP72 SMPS
UFBGA64 SMPS

LQFP100 SMPS
LQFP48 SMPS

LQFP64 SMPS

Pin type
Pin name

UFQFPN48

UFBGA100

Notes
Additional

UFBGA64

LQFP100
LQFP48

LQFP64
(function Alternate functions
functions
after reset)

IR_OUT, TIM4_CH4, SAI1_D2,

I2C1_SDA, SPI2_NSS,
SDMMC1_CDIR,
- C9 - - - 96 A1 46 62 A3 96 B3 PB9 I/O FT_fh - FDCAN1_TX(boot), -
DCMI_D7/PSSI_D7,
SDMMC1_D5, SAI1_FS_A,
TIM17_CH1, EVENTOUT
DS14216 Rev 5

TIM4_ETR, DCMI_D2/PSSI_D2,
- - - - - 97 A2 - - - 97 C3 PE0 I/O FT_h - LPGPIO1_P13, TIM16_CH1, -
EVENTOUT

Pinout, pin description, and alternate functions

DCMI_D3/PSSI_D3, TIM17_CH1,
- - - - - - - - - - 98 A2 PE1 I/O FT_h - -
EVENTOUT
46 A11 62 A2 A14 98 C5 - - - - - VDD11 S - - - -
47 B10 63 B7 B13 99 D10 47 63 D6 99 F2 VSS S - - - -
48 A13 64 A8 A16 100 K4 48 64 E4 100 H3 VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14, and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs
in output mode is limited:
- PC13 speed must not exceed 2 MHz with a maximum load of 30 pF. Refer to FT_o electrical characteristics for PC14, PC15.
- These GPIOs must not be used as current sources (for example to drive a LED).
3. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
4. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.
5. Power supply is VDDIO2.
117/307
 4.3 Alternate functions
118/307

Pinout, pin description, and alternate functions

Table 28. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - SPI3_RDY -

PA1 LPTIM1_CH2 TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK - -
PA2 - TIM2_CH3 TIM5_CH3 - - SPI1_RDY - -
PA3 - TIM2_CH4 TIM5_CH4 SAI1_CK1 - - - -
PA4 - - - OCTOSPI1_NCS - SPI1_NSS SPI3_NSS -
DS14216 Rev 5

PA5 CSLEEP TIM2_CH1 TIM2_ETR TIM8_CH1N PSSI_D14 SPI1_SCK - USART3_RX

DCMI_PIXCLK/
PA6 CDSTOP TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO - USART3_CTS
PSSI_PDCK
PA7 SRDSTOP TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - USART3_TX
PA8 MCO TIM1_CH1 - SAI1_CK2 - SPI1_RDY - USART1_CK
Port A

DCMI_D0/
PA9 - TIM1_CH2 - SPI2_SCK - - USART1_TX
PSSI_D0
DCMI_D1/
PA10 CRS_SYNC TIM1_CH3 LPTIM2_IN2 SAI1_D1 - - USART1_RX
PSSI_D1
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS
OCTOSPI1_ USART1_
PA12 - TIM1_ETR - - - SPI1_MOSI
NCS RTS_DE
PA13 JTMS/SWDIO IR_OUT - - - - - -

STM32U545xx
PA14 JTCK/SWCLK LPTIM1_CH1 - - I2C1_SMBA I2C4_SMBA - -
USART3_
PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS
RTS_DE
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U545xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N LPTIM3_CH1 SPI1_NSS - USART3_CK

USART3_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N LPTIM3_CH2 - MDF1_SDI0
RTS_DE
PB2 - LPTIM1_CH1 - TIM8_CH4N I2C3_SMBA SPI1_RDY MDF1_CKI0 -
JTDO/ USART1_
PB3 TIM2_CH2 LPTIM1_CH1 ADF1_CCK0 I2C1_SDA SPI1_SCK SPI3_SCK
TRACESWO RTS_DE
PB4 NJTRST LPTIM1_CH2 TIM3_CH1 ADF1_SDI0 I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS
DS14216 Rev 5

PB5 - LPTIM1_IN1 TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK

PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL - USART1_TX

Pinout, pin description, and alternate functions

Port B

PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA - USART1_RX

PB8 - - TIM4_CH3 SAI1_CK1 I2C1_SCL MDF1_CCK0 SPI3_RDY -
PB9 - IR_OUT TIM4_CH4 SAI1_D2 I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 LPTIM3_CH1 I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA SPI2_RDY - USART3_RX
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS MDF1_SDI1 USART3_CK
PB13 - TIM1_CH1N LPTIM3_IN1 - I2C2_SCL SPI2_SCK MDF1_CKI1 USART3_CTS
USART3_
PB14 - TIM1_CH2N LPTIM3_ETR TIM8_CH2N I2C2_SDA SPI2_MISO -
RTS_DE
PB15 RTC_REFIN TIM1_CH3N LPTIM2_IN2 TIM8_CH3N - SPI2_MOSI - -
119/307
 Table 28. Alternate function AF0 to AF7(1) (continued)
120/307

Pinout, pin description, and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PC0 - LPTIM1_IN1 - OCTOSPI1_IO7 I2C3_SCL SPI2_RDY - -

PC1 TRACED0 LPTIM1_CH1 - SPI2_MOSI I2C3_SDA - - -
PC2 - LPTIM1_IN2 - - - SPI2_MISO MDF1_CCK1 -
PC3 - LPTIM1_ETR LPTIM3_CH1 SAI1_D1 - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
PC5 - TIM1_CH4N - SAI1_D3 PSSI_D15 - - USART3_RX
DS14216 Rev 5

PC6 CSLEEP - TIM3_CH1 TIM8_CH1 - - - -

PC7 CDSTOP - TIM3_CH2 TIM8_CH2 - - - -
Port C

PC8 SRDSTOP - TIM3_CH3 TIM8_CH3 - - - -

DCMI_D3/
PC9 TRACED0 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - -
PSSI_D3
PC10 TRACED1 - LPTIM3_ETR ADF1_CCK1 - - SPI3_SCK USART3_TX
DCMI_D2/ OCTOSPI1_
PC11 - - LPTIM3_IN1 ADF1_SDI0 SPI3_MISO USART3_RX
PSSI_D2 NCS
PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -

STM32U545xx
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U545xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PD0 - - - TIM8_CH4N - SPI2_NSS - -

PD1 - - - - - SPI2_SCK - -
USART3_
PD2 TRACED2 - TIM3_ETR - - - -
RTS_DE
DCMI_D5/
PD3 - - - SPI2_SCK SPI2_MISO MDF1_SDI0 -
PSSI_D5
PD4 - - - - - SPI2_MOSI MDF1_CKI0 -
DS14216 Rev 5

PD5 - - - - - SPI2_RDY - -
DCMI_D10/
PD6 - - - SAI1_D1 SPI3_MOSI MDF1_SDI1 -
PSSI_D10

Pinout, pin description, and alternate functions

Port D

PD7 - - - - - - MDF1_CKI1 -
PD8 - - - - - - - USART3_TX
PD9 - - LPTIM2_IN2 - - - - USART3_RX
PD10 - - LPTIM2_CH2 - - - - USART3_CK
PD11 - - - - I2C4_SMBA - - USART3_CTS
USART3_
PD12 - - TIM4_CH1 - I2C4_SCL - -
RTS_DE
PD13 - - TIM4_CH2 - I2C4_SDA - - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -
121/307
 Table 28. Alternate function AF0 to AF7(1) (continued)
122/307

Pinout, pin description, and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PE0 - - TIM4_ETR - - - - -
PE1 - - - - - - - -
PE2 TRACECLK - TIM3_ETR SAI1_CK1 - - - -
PE3 TRACED0 - TIM3_CH1 OCTOSPI1_DQS - - - -
PE4 TRACED1 - TIM3_CH2 SAI1_D2 - - - -
PE5 TRACED2 - TIM3_CH3 SAI1_CK2 - - - -
DS14216 Rev 5

PE6 TRACED3 - TIM3_CH4 SAI1_D1 - - - -

PE7 - TIM1_ETR - - - - - -
Port E

PE8 - TIM1_CH1N - - - - - -
PE9 - TIM1_CH1 - ADF1_CCK0 - - MDF1_CCK0 -
PE10 - TIM1_CH2N - ADF1_SDI0 - - - -
PE11 - TIM1_CH2 - - - SPI1_RDY - -
PE12 - TIM1_CH3N - - - SPI1_NSS - -
PE13 - TIM1_CH3 - - - SPI1_SCK - -
PE14 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - -
PE15 - TIM1_BKIN - TIM1_CH4N - SPI1_MOSI - -

STM32U545xx
 Table 28. Alternate function AF0 to AF7(1) (continued)

STM32U545xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

ADF1/I2C4/
DCMI/I2C4/
Port OCTOSPI/ DCMI/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LPTIM1/2/3/ MDF1/
SAI1/SPI2/ I2C1/2/3/4/ OCTOSPI/ USART1/3
SYS_AF TIM1/2/8 TIM1/2/3/4/5 OCTOSPI/
TIM1/8/ LPTIM3 SPI3
SPI1/2/3
USB

PG2 - - - - - SPI1_SCK - -
PG3 - - - - - SPI1_MISO - -
PG4 - - - - - SPI1_MOSI - -
PG5 - - - - - SPI1_NSS - -
PG6 - - - OCTOSPI1_DQS I2C3_SMBA SPI1_RDY - -
OCTOSPI1_
PG7 - - - SAI1_CK1 I2C3_SCL MDF1_CCK0 -
DQS
DS14216 Rev 5

PG8 - - - - I2C3_SDA - - -
Port G

PG9 - - - - - OCTOSPI1_IO6 SPI3_SCK USART1_TX

Pinout, pin description, and alternate functions

PG10 - LPTIM1_IN1 - - - OCTOSPI1_IO7 SPI3_MISO USART1_RX
PG11 - LPTIM1_IN2 - OCTOSPI1_IO5 - - SPI3_MOSI USART1_CTS
OCTOSPI1_ USART1_
PG12 - LPTIM1_ETR - - - SPI3_NSS
NCS RTS_DE
PG13 - - - - I2C1_SDA - SPI3_RDY USART1_CK
PG14 - LPTIM1_CH2 - - I2C1_SCL - - -
OCTOSPI1_
PG15 - LPTIM1_CH1 - - I2C1_SMBA - -
DQS
PH0 - - - - - - - -
Port H

PH1 - - - - - - - -
PH3 - - - - - - - -
1. Refer to the next table for AF8 to AF15.
123/307
 Table 29. Alternate function AF8 to AF15(1)
124/307

Pinout, pin description, and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PA0 UART4_TX - OCTOSPI1_NCS - - AUDIOCLK TIM2_ETR EVENTOUT

PA1 UART4_RX - OCTOSPI1_DQS LPGPIO1_P0 - - TIM15_CH1N EVENTOUT
PA2 LPUART1_TX - OCTOSPI1_NCS - - - TIM15_CH1 EVENTOUT
PA3 LPUART1_RX - OCTOSPI1_CLK LPGPIO1_P1 - SAI1_MCLK_A TIM15_CH2 EVENTOUT
DCMI_HSYNC/
PA4 - - - - SAI1_FS_B LPTIM2_CH1 EVENTOUT
PSSI_DE
PA5 - - - - - - LPTIM2_ETR EVENTOUT
PA6 LPUART1_CTS - OCTOSPI1_IO3 LPGPIO1_P2 - - TIM16_CH1 EVENTOUT
DS14216 Rev 5

Port A

PA7 - - OCTOSPI1_IO2 - - LPTIM2_CH2 TIM17_CH1 EVENTOUT

PA8 - - USB_SOF - TRACECLK SAI1_SCK_A LPTIM2_CH1 EVENTOUT
PA9 - - - - - SAI1_FS_A TIM15_BKIN EVENTOUT
PA10 - - - - - SAI1_SD_A TIM17_BKIN EVENTOUT
PA11 - FDCAN1_RX USB_DM - - - - EVENTOUT
PA12 - FDCAN1_TX USB_DP - - - - EVENTOUT
PA13 - - USB_NOE - - SAI1_SD_B - EVENTOUT
PA14 - - USB_SOF - - SAI1_FS_B - EVENTOUT
PA15 UART4_RTS_DE - - - - - - EVENTOUT

STM32U545xx
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U545xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PB0 - - OCTOSPI1_IO1 LPGPIO1_P9 COMP1_OUT AUDIOCLK - EVENTOUT

LPUART1_
PB1 - OCTOSPI1_IO0 LPGPIO1_P3 - - LPTIM2_IN1 EVENTOUT
RTS_DE
PB2 - - OCTOSPI1_DQS - - - - EVENTOUT
PB3 - - CRS_SYNC LPGPIO1_P11 - SAI1_SCK_B - EVENTOUT
DCMI_D12/
PB4 UART5_RTS_DE TSC_G2_IO1 LPGPIO1_P12 - SAI1_MCLK_B TIM17_BKIN EVENTOUT
PSSI_D12
DCMI_D10/
PB5 UART5_CTS TSC_G2_IO2 - - SAI1_SD_B TIM16_BKIN EVENTOUT
PSSI_D10
DS14216 Rev 5

PB6 - TSC_G2_IO3 DCMI_D5/PSSI_D5 - - SAI1_FS_B TIM16_CH1N EVENTOUT

Port B

DCMI_VSYNC/
PB7 UART4_CTS TSC_G2_IO4 - - - TIM17_CH1N EVENTOUT

Pinout, pin description, and alternate functions

PSSI_RDY
PB8 SDMMC1_CKIN FDCAN1_RX DCMI_D6/PSSI_D6 - SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT
PB9 SDMMC1_CDIR FDCAN1_TX DCMI_D7/PSSI_D7 - SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
PB10 LPUART1_RX TSC_SYNC OCTOSPI1_CLK LPGPIO1_P4 COMP1_OUT SAI1_SCK_A - EVENTOUT
PB11 LPUART1_TX - OCTOSPI1_NCS - - - - EVENTOUT
LPUART1_
PB12 TSC_G1_IO1 OCTOSPI1_NCLK - - - TIM15_BKIN EVENTOUT
RTS_DE
PB13 LPUART1_CTS TSC_G1_IO2 - - - - TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - - - - TIM15_CH1 EVENTOUT
PB15 - - - - - - TIM15_CH2 EVENTOUT
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 Table 29. Alternate function AF8 to AF15(1) (continued)
126/307

Pinout, pin description, and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PC0 LPUART1_RX - - - SDMMC1_D5 - LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - OCTOSPI1_IO4 - - SAI1_SD_A - EVENTOUT
PC2 - - OCTOSPI1_IO5 LPGPIO1_P5 - - - EVENTOUT
PC3 - - OCTOSPI1_IO6 - - SAI1_SD_A LPTIM2_ETR EVENTOUT
PC4 - - OCTOSPI1_IO7 - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
PC6 SDMMC1_D0DIR TSC_G4_IO1 DCMI_D0/PSSI_D0 - SDMMC1_D6 - - EVENTOUT
SDMMC1_D123D
DS14216 Rev 5

PC7 TSC_G4_IO2 DCMI_D1/PSSI_D1 - SDMMC1_D7 - LPTIM2_CH2 EVENTOUT

Port C

IR
PC8 - TSC_G4_IO3 DCMI_D2/PSSI_D2 - SDMMC1_D0 - LPTIM3_CH1 EVENTOUT
PC9 - TSC_G4_IO4 USB_NOE - SDMMC1_D1 - LPTIM3_CH2 EVENTOUT
PC10 UART4_TX TSC_G3_IO2 DCMI_D8/PSSI_D8 LPGPIO1_P8 SDMMC1_D2 - - EVENTOUT
PC11 UART4_RX TSC_G3_IO3 DCMI_D4/PSSI_D4 - SDMMC1_D3 - - EVENTOUT
PC12 UART5_TX TSC_G3_IO4 DCMI_D9/PSSI_D9 LPGPIO1_P10 SDMMC1_CK - - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT

STM32U545xx
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U545xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PD0 - FDCAN1_RX - - - - - EVENTOUT

PD1 - FDCAN1_TX - - - - - EVENTOUT
DCMI_D11/ SDMMC1_
PD2 UART5_RX TSC_SYNC LPGPIO1_P7 LPTIM4_ETR - EVENTOUT
PSSI_D11 CMD
PD3 - - OCTOSPI1_NCS - - - - EVENTOUT
PD4 - - OCTOSPI1_IO4 - - - - EVENTOUT
PD5 - - OCTOSPI1_IO5 - - - - EVENTOUT
PD6 - - OCTOSPI1_IO6 - - SAI1_SD_A - EVENTOUT
DS14216 Rev 5

PD7 - - OCTOSPI1_IO7 - - LPTIM4_OUT - EVENTOUT

Port D

DCMI_HSYNC/
PD8 - - - - - - EVENTOUT
PSSI_DE

Pinout, pin description, and alternate functions

DCMI_PIXCLK/
PD9 - - - - - LPTIM3_IN1 EVENTOUT
PSSI_PDCK
PD10 - TSC_G6_IO1 - - - - LPTIM3_ETR EVENTOUT
PD11 - TSC_G6_IO2 - - - - LPTIM2_ETR EVENTOUT
PD12 - TSC_G6_IO3 - - - - LPTIM2_IN1 EVENTOUT
PD13 - TSC_G6_IO4 - LPGPIO1_P6 - LPTIM4_IN1 LPTIM2_CH1 EVENTOUT
PD14 - - - - - - LPTIM3_CH1 EVENTOUT
PD15 - - - - - - LPTIM3_CH2 EVENTOUT
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 Table 29. Alternate function AF8 to AF15(1) (continued)
128/307

Pinout, pin description, and alternate functions

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PE0 - - DCMI_D2/PSSI_D2 LPGPIO1_P13 - - TIM16_CH1 EVENTOUT

PE1 - - DCMI_D3/PSSI_D3 - - - TIM17_CH1 EVENTOUT
PE2 - TSC_G7_IO1 - LPGPIO1_P14 - SAI1_MCLK_A - EVENTOUT
PE3 - TSC_G7_IO2 - LPGPIO1_P15 - SAI1_SD_B - EVENTOUT
PE4 - TSC_G7_IO3 DCMI_D4/PSSI_D4 - - SAI1_FS_A - EVENTOUT
PE5 - TSC_G7_IO4 DCMI_D6/PSSI_D6 - - SAI1_SCK_A - EVENTOUT
PE6 - - DCMI_D7/PSSI_D7 - - SAI1_SD_A - EVENTOUT
PE7 - - - - - SAI1_SD_B - EVENTOUT
Port E
DS14216 Rev 5

PE8 - - - - - SAI1_SCK_B - EVENTOUT

PE9 - - OCTOSPI1_NCLK - - SAI1_FS_B - EVENTOUT
PE10 - TSC_G5_IO1 OCTOSPI1_CLK - - SAI1_MCLK_B - EVENTOUT
PE11 - TSC_G5_IO2 OCTOSPI1_NCS - - - - EVENTOUT
PE12 - TSC_G5_IO3 OCTOSPI1_IO0 - - - - EVENTOUT
PE13 - TSC_G5_IO4 OCTOSPI1_IO1 - - - - EVENTOUT
PE14 - - OCTOSPI1_IO2 - - - - EVENTOUT
PE15 - - OCTOSPI1_IO3 - - - - EVENTOUT

STM32U545xx
 Table 29. Alternate function AF8 to AF15(1) (continued)

STM32U545xx
AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPUART1/ CRS/DCMI/ COMP1/

CAN1/ LPTIM2/4/ LPTIM2/3/
SDMMC1/ OCTOSPI/ LPGPIO1 SDMMC1/ EVENTOUT
TSC SAI1 TIM2/15/16/17
UART4/5 USB SYS_AF

PG2 - - - - - - - EVENTOUT
PG3 - - - - - - - EVENTOUT
PG4 - - - - - - - EVENTOUT
PG5 LPUART1_CTS - - - - - - EVENTOUT
LPUART1_
PG6 - - - - - - EVENTOUT
RTS_DE
PG7 LPUART1_TX - - - - SAI1_MCLK_A - EVENTOUT
PG8 LPUART1_RX - - - - - - EVENTOUT
Port G
DS14216 Rev 5

PG9 - - - - - - TIM15_CH1N EVENTOUT

PG10 - - - - - - TIM15_CH1 EVENTOUT

Pinout, pin description, and alternate functions

PG11 - - - - - - TIM15_CH2 EVENTOUT
PG12 - - - - - - - EVENTOUT
PG13 - - - - - - - EVENTOUT
PG14 - - - - - - - EVENTOUT
DCMI_D13/
PG15 - - - - - - EVENTOUT
PSSI_D13
PH0 - - - - - - - EVENTOUT
Port H

PH1 - - - - - - - EVENTOUT
PH3 - - - - - - - EVENTOUT
1. For AF0 to AF7, refer to the previous table.
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Electrical characteristics STM32U545xx

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range and supply voltage range, where
95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 21.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 22.

Figure 21. Pin loading conditions Figure 22. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MSv68045V1 MSv68046V1

5.1.6 Power supply scheme

Each power supply pair (such as VDD/VSS or VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown in Figure 23 and Figure 24. These capacitors must be placed

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STM32U545xx Electrical characteristics

as close as possible to, or below, the appropriate pins on the underside of the PCB to
ensure the proper functionality of the device.

Figure 23. STM32U545xx power supply scheme (without SMPS)

VBAT
Backup circuitry
1.65 – 3.6 V (LSE, RTC, TAMP
backup registers,
VDDUSB backup SRAM)
VDDUSB
100 nF
VCAP Power switch

COUT = 4.7 μF

VDD VCORE
n x VDD LDO
VCORE
regulator
VDDIO1
OUT Kernel logic

Level shifter
n x 100 nF I/O (CPU, digital
+ 1 x 10 μF GPIOs logic and
IN
memories)

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
m x 100 nF OUT
Level shifter

+ 4.7 μF I/O
GPIOs logic
IN

m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF+ 1 μF VREF- COMPs/
VREFBUF

VSSA
MSv64358V4

The external capacitor on VCAP pin requires the following characteristics:

• COUT = 4.7 µF or 2 × 2.2 µF ±20%
• COUT ESR < 20 mΩ at 3 MHz
• COUT rated voltage ≥ 10 V

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268
Electrical characteristics STM32U545xx

Figure 24. STM32U545xQ power supply scheme (with SMPS)

VBAT Backup circuitry

1.65 – 3.6 V
(LSE, RTC, TAMP,
backup registers,
VDDUSB backup SRAM)
Power switch
VDDUSB
100 nF
VDD
VDDSMPS
Voltage regulator
CIN = 10 μF
SMPS VCORE
VLXSMPS SMPS ON

L = 2.2 μH
2 x VDD11
COUT = 2 x 2.2 μF Kernel logic
VSSSMPS
SMPS OFF (CPU, digital
and memories)
VDD LDO
n x VDD

VDDIO1
OUT

Level shifter
I/O
n x 100 nF GPIOs
IN
logic
+ 10 μF

n x VSS

VDDIO2
m x VDDIO2
VDDIO2
Level shifter

m x100 nF OUT
+ 4.7 μF I/O
GPIOs logic
IN
m x VSS

VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+ 1 μF OPAMPs/
100 nF+ 1 μF VREF- COMPs/
VREFBUF

VSSA
MSv64359V4

Note: SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on
application requirements. However, only one of them is active at the same time. When
SMPS is active, it feeds the VCORE on the two VDD11 pins supplied by the filtered SMPS
VLXSMPS output pin. When LDO is active, it supplies the VCORE and regulates it using the
same capacitors on VDD11 pins. It is recommended to add a decoupling capacitor of 100 nF
near each VDD11 pin/ball, but it is not mandatory.

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STM32U545xx Electrical characteristics

The external capacitors on VDD11 pins require the following characteristics:

• COUT = 2 × 2.2 µF ±20%
• COUT ESR < 20 mΩ at 3 MHz
• COUT rated voltage ≥ 10 V
The external capacitor on VDDSMPS pin requires the following characteristics:
• CIN = 10 µF ±20%
• CIN ESR < 10 mΩ at 3 MHz
• CIN rated voltage ≥ 10 V
The external inductance between VLXSMPS and VDD11 requires the following
characteristics:
• L = 2.2 µH ±20%
• L ISAT > 0.5 A
• L DCR < 200 mΩ

5.1.7 Current consumption measurement

The IDD parameters given in various tables in the next sections, represent the total MCU
consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VBAT and
VDDSMPS (if the device embeds the SMPS).

Figure 25. Current consumption measurement

VBAT
IDD_VBAT

IDD
VDD

VDDA

VDDUSB

VDDSMPS

VDDIO2
MSv62920V2

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 30, Table 31 and Table 32
may cause permanent damage to the device. These are stress ratings only and the
functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended
mission profiles are available on demand.

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268
Electrical characteristics STM32U545xx

Table 30. Voltage characteristics(1)(2)

Symbol Ratings Min Max Unit

External main supply voltage (including

VDDX - VSS -0.3 4.0
VDDSMPS, VDDA, VDDUSB, VBAT, VREF+)
I/O supply when HSLV = 0 -0.3 4.0
VDDIOx(3) - VSS
I/O supply when HSLV = 1 -0.3 2.75
Input voltage on FT_xx pins except Min (min (VDD, VDDA, VDDUSB, VDDIO2)
VSS - 0.3
FT_c pins + 4.0, 6.0)(5)(6)
VIN(4) V
Input voltage on FT_t pins in Min (min (VBAT, VDDA, VDDUSB,
VSS - 0.3
VBAT mode VDDIO2) + 4.0, 6.0) (5)(6)
Input voltage on FT_c pins VSS - 0.3 5.5
VIN(4)
Input voltage on any other pins VSS - 0.3 4.0
Allowed voltage difference for
VREF+ - VDDA - 0.4
VREF+ > VDDA
Variations between different VDDx
|∆VDDx| - 50.0
power pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50.0
ground pins(7)
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supply, in the permitted range.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. VDDIO1 or VDDIO2 or VSW, VDDIO1 = VDD.
4. VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
7. Including VREF- pin.

Table 31. Current characteristics

Symbol Ratings Max Unit
(1)
∑IVDD Total current into sum of all VDD power lines (source) 200
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(2) 120
∑I(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 120
IINJ(PIN)(3)(4) Injected current on FT_xx, TT_xx, RST pins -5/+0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must
always be connected to the external power supplies, in the permitted range.

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STM32U545xx Electrical characteristics

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum
allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN) is the absolute sum of the negative
injected currents (instantaneous values).

Table 32. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150

°C
TJ Maximum junction temperature 140

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268
Electrical characteristics STM32U545xx

5.3 Operating conditions

5.3.1 General operating conditions

Table 33. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit

IO_VDD_HSLV(1) = 0 1.71(2) - 3.6

Standard operating
VDD
voltage
IO_VDD_HSLV = 1 1.71(2) - 2.7

Supply voltage for

the internal SMPS
VDDSMPS - VDD
step-down
converter
At least one I/O in
PG[15:2] used, 1.08 - 3.6
IO_VDDIO2_HSLV = 0
Supply voltage for
VDDIO2 At least one I/O in
PG[15:2] I/Os
PG[15:2] used, 1.08 - 2.7
IO_VDDIO2_HSLV = 1
PG[15:2] I/Os not used 0 - 3.6
USB used 3.0 - 3.6
VDDUSB USB supply voltage
USB not used 0 - 3.6
COMP used 1.58 - 3.6 V

DAC or OPAMP used 1.60 3.6

ADC used 1.62 - 3.6
Analog supply
VDDA VREFBUF used
voltage 1.8 - 3.6
(normal mode)
ADC, DAC, COMP,
OPAMP, and VREFBUF 0 - 3.6
not used
Backup domain
VBAT - 1.65(3) - 3.6
supply voltage
All I/Os except FT_c and Min(min(VDD, VDDA, VDDUSB,
-0.3 -
TT_xx pins VDDIO2) +3.6, 5.5)(4)(5)
Min(min(VBAT, VDDA,
Input voltage on FT_t pins
VIN I/O input voltage -0.3 - VDDUSB, VDDIO2)+ 3.6,
in VBAT mode
5.5)(4)(5)
FT_c I/Os -0.3 - 5.0
TT_xx I/Os -0.3 - VDDIOx + 0.3
Sum of output
current sourced by
IIO_SW - - - 3 mA
all I/Os powered by
VSW(6)

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STM32U545xx Electrical characteristics

Table 33. General operating conditions (continued)

Symbol Parameter Conditions Min Typ Max Unit

Range 1 1.15 1.21 1.27

Internal regulator Range 2 1.05 1.1 1.15

VCORE V
ON Range 3 0.95 1.0 1.05
Range 4 0.81 0.9 0.99
Range 1 - - 160

AHB clock Range 2 - - 110

fHCLK
frequency Range 3 - - 55
Range 4 - - 25
MHz
Range 1 - - 160
APB1, APB2, Range 2 - - 110
fPCLKx
APB3 clock
(x = 1, 2, 3) frequency Range 3 - - 55
Range 4 - - 25

Ambient Maximum power

–40 - 85
temperature dissipation
for suffix 6 Low-power dissipation(7) –40 - 105
TA
Ambient Maximum power
–40 - 125 °C
temperature dissipation
for suffix 3 Low-power dissipation(7) –40 - 130

Junction Suffix 6 version –40 - 105

TJ
temperature range Suffix 3 version –40 - 130
1. HSLV means high-speed low-voltage mode (refer to the product reference manual).
2. When RESET is released, the functionality is guaranteed down to VBORx min.
3. In VBAT mode, the functionality is guaranteed down to VBOR_VBAT min.
4. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table.
The maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDDUSB, VDDIO2)+3.6 V, and 5.5V.
5. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors
must be disabled.
6. The I/Os powered by VSW are:
- PC13, PC14, PC15 when VDD is present.
- PC13, PC14, PC15, and all FT_t I/Os in VBAT mode.
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max.

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268
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5.3.2 Operating conditions at power-up/power-down

The parameters given in the table below are derived from tests performed under the
ambient temperature condition summarized in Table 33.

Table 34. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Max Unit

VDD rise-time rate - 0 ∞

µs/V
ULPMEN = 0 (default value) 20 ∞
tVDD
VDD fall-time rate Standby mode, BOR level 0 selected
250 ∞ ms/V
with ULPMEN = 1

5.3.3 Embedded reset and power control block characteristics

The parameters given in the table below are derived from tests performed under the
ambient temperature conditions summarized in Table 33.

Table 35. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Reset temporization after BOR0 is

tRSTTEMPO(2) VDD rising - - 900 μs
detected

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STM32U545xx Electrical characteristics

Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

Rising edge 1.6 1.66 1.71

Falling edge, range 1, 2, 3 1.58 1.64 1.69
VBOR0 Brownout reset threshold 0
Falling edge, range 4 and
1.58 1.64 1.69
low-power modes
Rising edge 1.98 2.08 2.17
VBOR1 Brownout reset threshold 1
Falling edge 1.9 2.00 2.1
Rising edge 2.18 2.29 2.39
VBOR2 Brownout reset threshold 2
Falling edge 2.08 2.18 2.25
Rising edge 2.48 2.59 2.7
VBOR3 Brownout reset threshold 3
Falling edge 2.39 2.5 2.61
Rising edge 2.76 2.88 3.0
VBOR4 Brownout reset threshold 4
Falling edge 2.67 2.79 2.9

Programmable voltage detector Rising edge 2.03 2.13 2.23

VPVD0 V
threshold 0 Falling edge 1.93 2.03 2.12
Rising edge 2.18 2.29 2.39
VPVD1 PVD threshold 1
Falling edge 2.08 2.18 2.28
Rising edge 2.33 2.44 2.55
VPVD2 PVD threshold 2
Falling edge 2.23 2.34 2.44
Rising edge 2.47 2.59 2.7
VPVD3 PVD threshold 3
Falling edge 2.39 2.50 2.61
Rising edge 2.6 2.72 2.83
VPVD4 PVD threshold 4
Falling edge 2.5 2.62 2.73
Rising edge 2.76 2.88 3.0
VPVD5 PVD threshold 5
Falling edge 2.66 2.78 2.9
Rising edge 2.83 2.96 3.08
VPVD6 PVD threshold 6
Falling edge 2.76 2.88 3.0
Vhyst_BOR0 Hysteresis voltage of BOR0 - - 20 -
Hysteresis voltage of BOR mV
Vhyst_BOR_PVD - - 80 -
(except BOR0) and PVD
tBOR0_sampling BOR0 sampling period ULPMEN = 1 - 30 55 ms
Additional BOR0 consumption if
IDD_BOR0(2) Standby mode - 60 - nA
ULPMEN = 0 versus ULPMEN = 1
BOR(3) (except BOR0) and PVD
IDD_BOR_PVD(2) - - 1 1.5 µA
consumption from VDD(4)
VBOR_VBAT VBAT brownout reset threshold - 1.58 - 1.65 V

DS14216 Rev 5 139/307

268
Electrical characteristics STM32U545xx

Table 35. Embedded reset and power control block characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

tVBAT_BOR VBAT BOR sampling period

MONEN = 0(5) - 0.5 2.5 s
_sampling in VBAT mode
Rising edge 1.61 1.68 1.75
VAVM1 VDDA voltage monitor 1 threshold
Falling edge 1.58 1.65 1.71
Rising edge 1.77 1.86 1.95
VAVM2 VDDA voltage monitor 2 threshold V
Falling edge 1.73 1.82 1.9
VIO2VM VDDIO2 voltage monitor threshold - 0.96 1.01 1.05
VUVM VDDUSB voltage monitor threshold - 1.15 1.22 1.28
Hysteresis of VDDA voltage
Vhyst_AVM - - 40 - mV
monitor
Voltage monitor consumption from
IDD_VM(2) VDD (AVM1, AVM2, IO2VM or - - 0.4 0.6
UVM single instance)
µA
VDDA voltage monitor
IDD_AVM_A(2) consumption from VDDA (resistor - - 1.25 1.85
bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design. Not tested in production
3. BOR0 is enabled in all modes (except Shutdown), and its consumption is therefore included in the supply current
characteristics tables.
4. This is also the consumption saved in Standby mode when ULPMEN = 1.
5. VBAT brownout reset monitoring is discontinuous when MONEN = 0 in PWR_BDCR1, and is continuous when MONEN = 1.

5.3.4 SMPS characteristics

Table 36. SMPS characteristics

Symbol Parameter Conditions Typ Unit

VDD > 1.9 V 3

Freq Switching frequency (range 1, 2, 3)(1) MHz
VDD < 1.9 V 1.5
1. The SMPS is asynchronous in range 4 and low-power modes.

5.3.5 Embedded voltage reference

The parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 33.

Table 37. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

Range 1, 2, 3 1.175 1.215 1.255

VREFINT(1) Internal reference voltage Range 4 and V
1.170 1.215 1.260
low-power modes

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STM32U545xx Electrical characteristics

Table 37. Embedded internal voltage reference (continued)

Symbol Parameter Conditions Min Typ Max Unit

ADC sampling time when reading

tS_vrefint(2)(3) - 12.65 - -
the internal reference voltage
µs
(3) Start time of reference voltage buffer
tstart_vrefint - - 4 6
when the ADC is enabled
IDD(VREFINTBUF) VREFINT buffer consumption from
(3) - - 1.5 2.1 µA
VDD when converted by the ADC
Internal reference voltage spread
∆VREFINT(4) VDD = 3 V - 6 11.5 mV
over the temperature range
TCoeff(4) Average temperature coefficient –40°C < TJ < +130 °C - 40 125 ppm/°C
ACoeff (3) Long term stability 1000 hours, TJ = 25 °C - 400 1000 ppm
(4)
VDDCoeff Average voltage coefficient 3.0 V ≤ VDD ≤ 3.6 V - 500 2900 ppm/V
VREFINT_DIV1(3) 1/4 reference voltage - 24 25 26
(3) %
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage - 74 75 76
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design. Not tested in production.
4. Evaluated by characterization. Not tested in production.

Figure 26. VREFINT versus temperature

MSv69159V1

5.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.

DS14216 Rev 5 141/307

268
Electrical characteristics STM32U545xx

The current consumption is measured as described in Section 5.1.7: Current consumption

measurement.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “Number of wait states according
to CPU clock (HCLK) frequency” available in the product reference manual).
• When the peripherals are enabled, fPCLK = fHCLK.
• The voltage scaling range is adjusted to fHCLK frequency as follows:
– Voltage range 1 for 110 MHz < fHCLK ≤ 160 MHz
– Voltage range 2 for 55 MHz < fHCLK ≤ 110 MHz
– Voltage range 3 for 25 MHz < fHCLK ≤ 55 MHz
– Voltage range 4 for fHCLK ≤ 25 MHz
The parameters given in the tables below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33.

142/307 DS14216 Rev 5

 STM32U545xx
Table 38. Current consumption in Run mode on LDO, code with data processing
running from flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Max(2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 1.60 1.75 2.20 2.85 4.10 2.10 2.50 3.80 5.70 9.60
16 1.20 1.30 1.75 2.40 3.65 1.70 2.00 3.30 5.30 9.10
fHCLK = fMSI, 12 0.93 1.05 1.50 2.15 3.40 1.40 1.70 3.10 5.00 8.80
all peripherals and AHB/APB 4 0.40 0.54 0.96 1.60 2.90 0.72 1.20 2.50 4.40 8.30
disabled, Range 4
Flash bank 2 in power down, 2 0.27 0.41 0.84 1.50 2.75 0.59 1.00 2.30 4.30 8.10
all SRAMs enabled 1 0.21 0.35 0.78 1.45 2.70 0.52 0.93 2.30 4.20 8.10
0.4 0.17 0.31 0.74 1.40 2.65 0.47 0.88 2.20 4.20 8.00
DS14216 Rev 5

0.1 0.15 0.29 0.72 1.35 2.65 0.45 0.86 2.20 4.10 8.00
Supply 160 13.00 13.50 14.00 15.00 17.00 16.00 17.00 20.00 24.00 33.00
IDD
current in fHCLK = PLL on HSE 16 MHz in mA
(Run) Run mode Range 1 140 11.50 12.00 12.50 13.50 15.50 14.00 15.00 18.00 22.00 31.00
bypass mode,
all peripherals and AHB/APB 120 9.90 10.00 11.00 12.00 14.00 12.00 13.00 16.00 21.00 29.00
disabled, 110 8.35 8.60 9.20 10.00 11.50 9.80 11.00 13.00 16.00 23.00
Flash bank 2 in power down,
Range 2 72 5.65 5.90 6.50 7.35 8.95 6.80 7.60 9.80 13.00 20.00
all SRAMs enabled
64 5.10 5.30 5.90 6.80 8.35 6.20 6.90 9.10 13.00 19.00
fHCLK = fHSE bypass mode, 55 4.05 4.25 4.75 5.45 6.85 4.90 5.50 7.10 9.60 15.00
all peripherals and AHB/APB

Electrical characteristics
disabled, Range 3
Flash bank 2 in power down, 32 2.50 2.65 3.15 3.90 5.30 3.20 3.70 5.40 7.90 13.00
all SRAMs enabled
1. The current consumption from SRAM is similar.
2. Evaluated by characterization. Not tested in production.
143/307
 Table 39. Current consumption in Run mode on SMPS, code with data processing
144/307

Electrical characteristics
running from flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(2)(3)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.95 1.05 1.30 1.70 2.45 1.30 1.60 2.30 3.60 6.00
16 0.69 0.78 1.05 1.45 2.20 0.97 1.20 2.00 3.40 5.70
12 0.45 0.63 0.89 1.30 2.05 0.68 1.10 1.80 3.20 5.50
fHCLK = fMSI,
all peripherals disable 4 0.21 0.28 0.49 0.97 1.70 0.41 0.62 1.30 2.80 5.10
Range 4
Flash bank 2 in power down, 2 0.15 0.21 0.40 0.89 1.65 0.34 0.55 1.20 2.70 5.10
all SRAMs enabled
1 0.12 0.18 0.37 0.85 1.60 0.30 0.51 1.20 2.70 5.00
0.4 0.09 0.16 0.36 0.83 1.60 0.28 0.49 1.20 2.60 5.00
0.1 0.08 0.15 0.35 0.82 1.55 0.26 0.48 1.20 2.60 4.90
DS14216 Rev 5

Supply
IDD 160 10.00 10.50 11.00 11.50 13.00 13.00 13.00 15.00 18.00 24.00
current in mA
(Run) Run mode
fHCLK = PLL on HSE 16 MHz in Range 1 140 8.90 9.15 9.75 10.50 12.00 11.00 12.00 14.00 17.00 23.00
bypass mode,
120 7.70 7.95 8.55 9.30 10.50 9.40 11.00 12.00 16.00 21.00
all peripherals disable,
Flash bank 2 in power down, 110 6.00 6.20 6.60 7.25 8.35 7.30 7.80 9.00 12.00 16.00
all SRAMs enabled Range 2 72 4.10 4.30 4.70 5.30 6.40 5.10 5.60 6.80 9.30 14.00
64 3.75 3.90 4.30 4.90 6.00 4.70 5.10 6.40 8.80 13.00
fHCLK = fHSE bypass mode, 55 2.75 2.85 3.20 3.65 4.55 3.50 3.80 4.70 6.50 9.60
all peripherals disabled,
Range 3
Flash bank 2 in power down, 32 1.75 1.85 2.20 2.65 3.55 2.30 2.60 3.60 5.40 8.40
all SRAMs enabled
1. The current consumption from SRAM is similar.
2. Evaluated by characterization. Not tested in production.

STM32U545xx
3. The maximum value is at VDD = 1.71 V in Sleep mode on SMPS.
 Table 40. Current consumption in Run mode on SMPS, code with data processing

STM32U545xx
running from flash memory, ICACHE ON (1-way), prefetch ON, VDD = 3.0 V(1)
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.63 0.69 0.86 1.10 1.60 0.83 1.10 1.60 2.30 3.80
16 0.47 0.52 0.69 0.95 1.45 0.66 0.82 1.40 2.10 3.60
fHCLK = fMSI, 12 0.37 0.43 0.60 0.85 1.35 0.55 0.72 1.30 2.00 3.50
all peripherals and AHB/APB 4 0.17 0.22 0.39 0.65 1.15 0.33 0.49 0.99 1.80 3.30
disabled, Range 4
Flash bank 2 in power down, 2 0.12 0.18 0.34 0.60 1.10 0.28 0.44 0.94 1.80 3.30
all SRAMs enabled 1 0.10 0.15 0.32 0.58 1.05 0.25 0.42 0.91 1.70 3.20
0.4 0.08 0.14 0.30 0.56 1.05 0.24 0.40 0.90 1.70 3.20
0.1 0.07 0.13 0.30 0.55 1.05 0.23 0.39 0.89 1.70 3.20
DS14216 Rev 5

Supply 160 7.35 7.55 8.05 8.65 9.70 8.50 9.00 11.00 13.00 16.00
IDD
current in fHCLK = PLL on HSE 16 MHz in mA
(Run) Run mode Range 1 140 6.55 6.70 7.20 7.75 8.75 7.60 8.10 9.50 12.00 15.00
bypass mode,
all peripherals and AHB/APB 120 5.65 5.90 6.30 6.90 7.95 6.60 7.20 8.50 11.00 15.00
disabled, 110 4.50 4.65 5.00 5.50 6.35 5.30 5.60 6.60 8.10 11.00
Flash bank 2 in power down,
Range 2 72 3.15 3.30 3.65 4.10 4.90 3.80 4.10 5.10 6.50 9.20
all SRAMs enabled
64 2.85 3.00 3.35 3.80 4.60 3.50 3.80 4.80 6.20 8.90
fHCLK = fHSE bypass mode, 55 2.20 2.30 2.55 2.90 3.60 2.70 2.90 3.60 4.70 6.80
all peripherals and AHB/APB
disabled, Range 3

Electrical characteristics
Flash bank 2 in power down, 32 1.45 1.55 1.80 2.15 2.80 1.80 2.10 2.80 3.90 5.90
all SRAMs enabled
1. The current consumption from SRAM is similar.
2. Evaluated by characterization. Not tested in production.
145/307
 Table 41. Typical current consumption in Run mode on LDO, with different codes
146/307

Electrical characteristics
running from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.55 1.55 1.55 64.58 64.58 64.58
fHCLK = fMSI = 24 MHz, CoreMark 1.50 1.50 1.50 62.50 62.50 62.50
Supply all peripherals disabled,
IDD SecureMark 1.65 1.65 1.65 68.75 68.75 68.75 µA/
current in Flash bank 2 in power down, Range 4 mA
(Run) Run mode Dhrystone 2.1 1.60 1.60 1.60 66.67 66.67 66.67 MHz
SRAM2 enabled,
SRAM1, SRAM4 in power down Fibonacci 1.20 1.20 1.20 50.00 50.00 50.00
while 1.10 1.10 1.10 45.83 45.83 45.83

Table 42. Typical current consumption in Run mode on LDO, with different codes
DS14216 Rev 5

running from flash memory, ICACHE ON (1-way), prefetch ON(1)

Conditions Typ Typ
Symbol

Parameter Unit Unit

- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.60 1.60 1.60 66.67 66.67 66.67
CoreMark 1.55 1.55 1.55 64.58 64.58 64.58
fHCLK = fMSI = 24 MHz,
Supply SecureMark 1.70 1.70 1.70 70.83 70.83 70.83
IDD all peripherals disabled, µA/
current in Range 4 mA
(Run) Run mode Flash bank 2 in power down, Dhrystone 2.1 1.65 1.65 1.65 68.75 68.75 68.75 MHz
all SRAMs enabled
Fibonacci 1.25 1.25 1.25 52.08 52.08 52.08
While(1) 1.15 1.15 1.15 47.92 47.92 47.92

STM32U545xx
 Table 42. Typical current consumption in Run mode on LDO, with different codes

STM32U545xx
running from flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 13.00 13.00 13.00 81.25 81.25 81.25
fHCLK = fPLL = 160 MHz,
CoreMark 13.00 13.00 13.00 81.25 81.25 81.25
PLL on HSE 16 MHz in bypass
mode, SecureMark 14.00 14.00 14.00 87.50 87.50 87.50
Range 1
all peripherals disabled, Dhrystone 2.1 13.50 13.50 13.50 84.38 84.38 84.38
Flash bank 2 in power down,
Fibonacci 10.50 10.50 10.50 65.63 65.63 65.63
all SRAMs enabled
While 9.65 9.70 9.70 60.31 60.63 60.63
Reduced Code 8.30 8.35 8.35 75.45 75.91 75.91
fHCLK = fPLL = 110 MHz,
CoreMark 8.25 8.25 8.30 75.00 75.00 75.45
DS14216 Rev 5

PLL on HSE 16 MHz in bypass

Supply mode, SecureMark 9.05 9.10 9.10 82.27 82.73 82.73
IDD µA/
current in Range 2 mA
(Run) Run mode all peripherals disabled, Dhrystone 2.1 8.75 8.80 8.80 79.55 80.00 80.00 MHz
Flash bank 2 in power down,
Fibonacci 6.60 6.65 6.65 60.00 60.45 60.45
all SRAMs enabled
While 6.20 6.25 6.25 56.36 56.82 56.82
Reduced Code 4.00 4.05 4.05 72.73 73.64 73.64
CoreMark 3.95 4.00 4.05 71.82 72.73 73.64
fHCLK = fHSE = 55 MHz,
all peripherals disable, SecureMark 4.35 4.40 4.40 79.09 80.00 80.00
Range 3
Flash bank 2 in power down, Dhrystone 2.1 4.20 4.25 4.25 76.36 77.27 77.27
all SRAMs enabled

Electrical characteristics
Fibonacci 3.10 3.15 3.20 56.36 57.27 58.18
While 2.85 2.90 2.95 51.82 52.73 53.64
1. The current consumption from SRAM is similar.
147/307
148/307

Electrical characteristics
Table 43. Typical current consumption in Run mode on SMPS, with different codes
running from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 0.91 0.60 0.56 37.92 24.79 23.33
fHCLK = fMSI = 24 MHz,
CoreMark 0.88 0.58 0.54 36.67 23.96 22.50
all peripherals disabled,
Supply SecureMark 0.97 0.64 0.60 40.42 26.46 25.00
IDD Flash bank 2 in power down, µA/
current in Range 4 mA
(Run) SRAM2 enabled, Dhrystone 2.1 0.95 0.62 0.58 39.38 25.63 24.17 MHz
Run mode
SRAM1, SRAM4 in power
Fibonacci 0.71 0.47 0.44 29.38 19.38 18.13
down
while 0.62 0.41 0.39 26.00 17.27 16.25
DS14216 Rev 5

Table 44. Typical current consumption in Run mode on SMPS, with different codes
running from flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Typ
Symbol

Parameter Unit Unit

- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 0.95 0.63 0.59 39.38 26.04 24.58
CoreMark 0.91 0.61 0.57 37.92 25.21 23.75
fHCLK = fMSI = 24 MHz,
Supply SecureMark 1.00 0.67 0.63 41.67 27.71 26.04
IDD all peripherals disabled, µA/
current in Range 4 mA
(Run) Flash bank 2 in power down, Dhrystone 2.1 0.98 0.65 0.61 40.63 26.88 25.42 MHz
Run mode
all SRAMs enabled
Fibonacci 0.74 0.50 0.47 30.83 20.63 19.38
while 0.67 0.46 0.43 27.92 18.96 17.71

STM32U545xx
 Table 44. Typical current consumption in Run mode on SMPS, with different codes

STM32U545xx
running from flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ

Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 10.00 7.35 6.95 62.50 45.94 43.44
fHCLK = fPLL = 160 MHz,
CoreMark 10.00 7.30 6.90 62.50 45.63 43.13
PLL on HSE 16 MHz in bypass
mode, SecureMark 11.00 7.95 7.45 68.75 49.69 46.56
Range 1
all peripherals disabled, Dhrystone 2.1 10.50 7.70 7.30 65.63 48.13 45.63
Flash bank 2 in power down,
Fibonacci 8.05 5.90 5.55 50.31 36.88 34.69
all SRAMs enabled
while 7.55 5.55 5.25 47.19 34.69 32.81
Reduced Code 6.00 4.50 4.30 54.55 40.91 39.09
fHCLK = fPLL = 110 MHz,
CoreMark 5.95 4.45 4.25 54.09 40.45 38.64
DS14216 Rev 5

PLL on HSE 16 MHz in bypass

Supply mode, SecureMark 6.50 4.90 4.65 59.09 44.55 42.27
IDD µA/
current in Range 2 mA
(Run) all peripherals disabled, Dhrystone 2.1 6.30 4.70 4.50 57.27 42.73 40.91 MHz
Run mode
Flash bank 2 in power down,
Fibonacci 4.80 3.65 3.50 43.64 33.18 31.82
all SRAMs enabled
while 4.55 3.45 3.30 41.36 31.36 30.00
Reduced Code 2.75 2.20 2.10 50.00 40.00 38.18
CoreMark 2.70 2.15 2.10 49.09 39.09 38.18
fHCLK = fHSE = 55 MHz,
all peripherals disabled, SecureMark 2.95 2.35 2.25 53.64 42.73 40.91
Range 3
Flash bank 2 in power down, Dhrystone 2.1 2.85 2.25 2.20 51.82 40.91 40.00

Electrical characteristics
all SRAMs enabled
Fibonacci 2.15 1.75 1.70 39.09 31.82 30.91
while 2.00 1.65 1.60 36.36 30.00 29.09
1. The current consumption from SRAM is similar.
149/307
 Table 45. Current consumption in Sleep mode on LDO, flash memory in power down
150/307

Electrical characteristics
Conditions Typ Max(1)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.49 0.63 1.05 1.70 2.95 0.73 1.20 2.50 4.40 8.10
16 0.37 0.51 0.93 1.60 2.85 0.60 1.10 2.30 4.30 8.00
12 0.31 0.45 0.88 1.55 2.80 0.54 0.96 2.30 4.20 8.00

fHCLK = fMSI, 4 0.16 0.30 0.72 1.40 2.65 0.37 0.79 2.10 4.10 7.80
Range 4
all peripherals disabled 2 0.13 0.27 0.69 1.35 2.60 0.34 0.76 2.10 4.00 7.80
1 0.12 0.26 0.68 1.35 2.60 0.32 0.74 2.00 4.00 7.80
0.4 0.11 0.24 0.67 1.30 2.55 0.31 0.72 2.00 3.90 7.70
Supply
IDD current in 0.1 0.10 0.24 0.66 1.30 2.55 0.30 0.72 2.00 3.90 7.70
mA
(Sleep) Sleep
DS14216 Rev 5

160 4.10 4.35 5.05 6.00 7.85 5.10 6.00 8.90 14.00 22.00
mode
Range 1 140 3.65 3.90 4.60 5.60 7.40 4.60 5.50 8.40 13.00 21.00
fHCLK = PLL on HSE 16 MHz 120 3.20 3.45 4.15 5.15 6.95 4.10 5.10 7.90 13.00 21.00
in bypass mode,
all peripherals disabled 110 2.75 2.95 3.50 4.35 5.95 3.40 4.20 6.30 9.50 16.00
Range 2 72 1.95 2.20 2.75 3.60 5.15 2.60 3.30 5.50 8.70 15.00
64 1.80 2.00 2.60 3.45 5.00 2.40 3.10 5.30 8.50 15.00

fHCLK = fHSE bypass mode, 55 1.30 1.45 1.95 2.70 4.05 1.70 2.30 3.90 6.40 12.00
Range 3
all peripherals disabled 32 0.89 1.05 1.55 2.25 3.65 1.30 1.80 3.50 5.90 11.00
1. Evaluated by characterization. Not tested in production.

STM32U545xx
 Table 46. Current consumption in Sleep mode on SMPS, flash memory in power down

STM32U545xx
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(1) (2)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.25 0.30 0.60 0.99 1.75 0.36 0.57 1.40 2.70 5.10
16 0.18 0.25 0.48 0.92 1.65 0.29 0.51 1.20 2.60 5.00
12 0.16 0.22 0.42 0.89 1.65 0.26 0.48 1.20 2.60 5.00

fHCLK = fMSI, 4 0.07 0.14 0.33 0.80 1.55 0.17 0.39 1.10 2.50 4.80
Range 4
all peripherals disabled 2 0.06 0.13 0.33 0.78 1.50 0.15 0.37 1.10 2.50 4.80
1 0.05 0.12 0.32 0.77 1.50 0.14 0.36 1.10 2.50 4.80
0.4 0.04 0.11 0.32 0.77 1.50 0.13 0.35 1.00 2.50 4.80
Supply 0.1 0.04 0.11 0.32 0.76 1.50 0.12 0.35 1.00 2.40 4.80
IDD
current in mA
DS14216 Rev 5

(Sleep) Sleep mode 160 3.30 3.50 4.00 4.75 6.15 4.10 4.70 6.40 9.60 16.00
Range 1 140 2.95 3.15 3.70 4.45 5.80 3.70 4.30 6.00 9.20 15.00
fHCLK = PLL on HSE 16 MHz 120 2.60 2.80 3.35 4.10 5.45 3.30 3.90 5.60 8.80 15.00
in bypass mode,
all peripherals disabled 110 2.10 2.25 2.65 3.25 4.30 2.60 3.10 4.30 6.70 11.00
Range 2 72 1.55 1.70 2.10 2.70 3.75 2.00 2.40 3.70 6.10 11.00
64 1.45 1.60 2.00 2.55 3.65 1.90 2.30 3.60 5.90 10.00

fHCLK = fHSE bypass mode, 55 0.96 1.05 1.40 1.85 2.70 1.30 1.60 2.50 4.30 7.30
Range 3
all peripherals disabled 32 0.70 0.81 1.10 1.60 2.45 0.91 1.30 2.20 4.00 7.00
1. Evaluated by characterization. Not tested in production.

Electrical characteristics
2. The maximum value is at VDD = 1.71 V in Sleep mode on SMPS.
151/307
 Table 47. Current consumption in Sleep mode on SMPS,
152/307

Electrical characteristics
flash memory in power down, VDD = 3.0 V
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(1)

Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 0.18 0.23 0.40 0.65 1.15 0.25 0.41 0.90 1.70 3.20
16 0.13 0.19 0.35 0.60 1.10 0.20 0.36 0.86 1.70 3.10
12 0.11 0.17 0.33 0.58 1.05 0.18 0.34 0.83 1.60 3.10

fHCLK = fMSI, 4 0.05 0.11 0.27 0.52 1.00 0.12 0.28 0.77 1.60 3.00
Range 4
all peripherals disabled 2 0.04 0.09 0.26 0.51 1.00 0.11 0.26 0.75 1.60 3.00
1 0.04 0.09 0.25 0.51 1.00 0.10 0.26 0.75 1.50 3.00
0.4 0.03 0.08 0.25 0.50 0.99 0.09 0.25 0.74 1.50 3.00
Supply 0.1 0.03 0.08 0.25 0.50 0.99 0.09 0.25 0.74 1.50 3.00
DS14216 Rev 5

IDD
current in mA
(Sleep) Sleep mode 160 2.55 2.70 3.10 3.65 4.65 3.00 3.40 4.70 6.60 11.00
Range 1 140 2.30 2.45 2.85 3.40 4.40 2.70 3.20 4.40 6.30 9.90
fHCLK = PLL on HSE 16 MHz 120 2.05 2.20 2.60 3.15 4.15 2.50 2.90 4.10 6.00 9.60
in bypass mode,
all peripherals disabled 110 1.70 1.80 2.10 2.55 3.35 2.00 2.30 3.20 4.60 7.30
Range 2 72 1.30 1.40 1.70 2.15 2.95 1.60 1.90 2.80 4.20 6.90
64 1.20 1.35 1.65 2.05 2.85 1.50 1.80 2.70 4.10 6.70

fHCLK = fHSE bypass mode, 55 0.88 0.97 1.20 1.55 2.20 1.10 1.30 2.00 3.10 5.10
Range 3
all peripherals disabled 32 0.67 0.75 0.99 1.35 2.00 0.82 1.10 1.80 2.80 4.80
1. Evaluated by characterization. Not tested in production.

STM32U545xx
 Table 48. SRAM1 current consumption in Run/Sleep mode with LDO and SMPS

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
Voltage fHCLK
- 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling (MHz)

Range 4 24 0.01 0.04 0.13 0.27 0.54 0.04 0.12 0.38 0.81 1.63
Range 1 160 0.03 0.08 0.21 0.41 0.80 0.10 0.23 0.63 1.24 2.39
LDO
Range 2 110 0.02 0.06 0.17 0.35 0.69 0.07 0.18 0.52 1.05 2.08
Range 3 55 0.02 0.05 0.15 0.30 0.60 0.05 0.15 0.44 0.90 1.80
SRAM1 supply Range 4 24 0.005 0.01 0.05 0.10 0.21 0.01 0.04 0.15 0.31 0.62
current in
IDD SMPS Run/Sleep mode Range 1 160 0.02 0.04 0.11 0.22 0.42 0.06 0.12 0.34 0.67 1.27
mA
(SRAM1) VDD = 3.0 V (SRAM1PD = 1 Range 2 110 0.01 0.03 0.09 0.18 0.34 0.04 0.09 0.26 0.53 1.02
versus
SRAM1PD = 0) Range 3 55 0.01 0.02 0.07 0.14 0.28 0.02 0.07 0.21 0.42 0.85
DS14216 Rev 5

Range 4 24 0.01 0.02 0.08 0.17 0.35 0.03 0.08 0.25 0.54 1.09
Range 1 160 0.03 0.07 0.19 0.37 0.70 0.10 0.22 0.60 1.17 2.22
SMPS(2)
Range 2 110 0.02 0.05 0.15 0.29 0.57 0.06 0.16 0.46 0.92 1.80
Range 3 55 0.01 0.04 0.11 0.24 0.47 0.04 0.12 0.36 0.74 1.50
1. Evaluated by characterization. Not tested in production.
2. The typical value is measured at VDD = 1.8 V. The maximum value is for 1.71 V ≤ VDD ≤ 3.6 V and is at VDD = 1.71 V in Run/Sleep mode on SMPS.

Electrical characteristics
153/307
 Table 49. Static power consumption of flash banks, when supplied by LDO/SMPS
154/307

Electrical characteristics
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

IDD Flash bank 1 static consumption in normal mode

(2) 45.0 45.0 50.0 50.0 100.0 60.0 100.0 100.0 100.0 150.0
(Flash_Bank1) (PD1 = 1 versus PD1 = 0)

IDD Flash bank 2 static consumption in normal mode

(2) 45.0 45.0 50.0 50.0 100.0 60.0 100.0 100.0 100.0 150.0
(Flash_Bank2) (PD2 = 1 versus PD2 = 0) µA
One flash bank additional static consumption in
IDD
(3) normal mode versus low-power mode 25.0 25.0 25.0 25.0 50.0 40.0 40.0 40.0 40.0 70.0
(Flash_Bank_LPM)
(LPM = 0 versus LPM = 1)
1. Evaluated by characterization. Not tested in production.
2. When one bank is in power-down, this consumption is saved. When the flash memory is in power down in Sleep mode (SLEEP_PD =1 ), Bank 1 and Bank 2 are in
power down.
3. If no bank is in power-down, the flash memory additional static consumption in normal mode versus low-power mode is 2 x IDD(Flash_Bank_LPM).
DS14216 Rev 5

Table 50. Current consumption in Stop 0 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 74.5 165 435 845 1600 230 500 1400 2600 4800
Supply current in Stop 0 mode,
regulator in Range 4, 2.4 74.5 165 435 845 1600 230 500 1400 2600 4800
RTC disabled, 3.0 74.5 165 440 845 1600 230 500 1400 2600 4800
8-Kbyte SRAM2 + ICACHE 3.3 75.0 165 440 850 1600 230 500 1400 2600 4800
retained
3.6 76.0 170 440 850 1650 230 510 1400 2600 5000
IDD(Stop 0) µA
1.8 79.0 175 465 905 1750 240 530 1400 2800 5300
Supply current in Stop 0 mode, 2.4 79.0 175 465 910 1750 240 530 1400 2800 5300

STM32U545xx
regulator in Range 4,
3.0 79.0 175 465 910 1750 240 530 1400 2800 5300
RTC disabled,
All SRAMs retained 3.3 79.5 175 465 910 1750 240 530 1400 2800 5300
3.6 80.5 180 470 915 1750 250 540 1500 2800 5300
 STM32U545xx
1. Evaluated by characterization. Not tested in production.

Table 51. Current consumption in Stop 0 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 26.0 73.0 215 400 945 78.0 220 650 1200 2900
Supply current in Stop 0 mode,
regulator in Range 4, 2.4 23.5 64.5 190 375 735 71.0 200 570 1200 2300
RTC disabled, 3.0 20.5 55.0 160 320 625 62.0 170 480 960 1900
8-Kbyte SRAM2 + ICACHE 3.3 19.5 52.0 150 300 590 59.0 160 450 900 1800
retained
3.6 19.0 50.5 145 290 560 57.0 160 440 870 1700
IDD(Stop 0) µA
1.8 28.5 78.0 235 455 1050 86.0 240 710 1400 3200
Supply current in Stop 0 mode, 2.4 25.5 68.5 200 405 795 77.0 210 600 1300 2400
DS14216 Rev 5

regulator in Range 4,
3.0 22.0 58.5 170 340 675 66.0 180 510 1100 2100
RTC disabled,
All SRAM retained 3.3 21.0 55.5 160 325 635 63.0 170 480 980 2000
3.6 20.5 53.5 155 310 605 62.0 170 470 930 1900
1. Evaluated by characterization. Not tested in production.

Table 52. Current consumption in Stop 1 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Electrical characteristics
1.8 41.5 130 385 770 1500 130 390 1200 2400 4500
Supply current in Stop 1 mode, 2.4 44.5 130 385 770 1500 140 390 1200 2400 4500
RTC disabled,
IDD (Stop 1) 3.0 47.0 130 385 775 1500 150 390 1200 2400 4500 µA
8-Kbyte SRAM2 + ICACHE
retained 3.3 46.0 130 390 775 1500 140 390 1200 2400 4500
3.6 45.5 135 390 780 1500 140 410 1200 2400 4500
155/307
 Table 52. Current consumption in Stop 1 mode on LDO (continued)
156/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 48.5 135 410 830 1600 150 410 1300 2500 4800
2.4 48.0 135 410 830 1650 150 410 1300 2500 5000
Supply current in Stop 1 mode,
IDD (Stop 1) RTC disabled, 3.0 50.0 140 415 830 1650 150 420 1300 2500 5000
All SRAMs retained
3.3 49.5 140 415 835 1650 150 420 1300 2600 5000
3.6 49.5 140 420 840 1650 150 420 1300 2600 5000
1.8 45.0 130 385 770 1500 140 390 1200 2400 4500
Supply current in Stop 1 mode, 2.4 45.0 130 385 770 1500 140 390 1200 2400 4500
RTC(2) clocked by LSI 32 kHz,
3.0 47.0 130 385 775 1500 150 390 1200 2400 4500
8-Kbyte SRAM2 + ICACHE
retained 3.3 46.5 130 390 780 1500 140 390 1200 2400 4500
DS14216 Rev 5

3.6 46.5 135 390 780 1500 140 410 1200 2400 4500
µA
1.8 45.0 133 395 790 1545 140 380 1200 2300 4400
Supply current in Stop 1 mode,
2.4 45.8 133 395 790 1545 140 390 1200 2300 4500
RTC(2) clocked by LSE
IDD(Stop 1 bypassed at 32768 Hz,
3.0 48.1 133 395 795 1545 140 390 1200 2300 4500
with RTC)
8-Kbyte SRAM2 + ICACHE
3.3 46.7 133 400 795 1545 140 390 1200 2300 4500
retained
3.6 46.4 145 400 800 1545 140 440 1200 2400 4500
1.8 44.5 130 385 770 1500 - - - - -
Supply current in Stop 1 mode,
RTC(2) clocked by LSE quartz in 2.4 45.0 130 385 770 1500 - - - - -
low-drive mode,
3.0 47.0 130 385 775 1500 - - - - -
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE 3.3 47.0 130 385 775 1500 - - - - -
retained
3.6 46.5 135 390 780 1500 - - - - -

STM32U545xx
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
 Table 53. Current consumption during wake-up from Stop 1 mode on LDO

STM32U545xx
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 40

Electrical charge consumed during wake-up from
QDD(wakeup from Stop 1) Wake-up clock is HSI 16 MHz 3.0 40 nAs
Stop 1 mode
Wake-up clock is MSI 1 MHz 70

Table 54. Current consumption in Stop 1 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 26.0 72.5 215 400 945 78.0 220 650 1200 2900
DS14216 Rev 5

Supply current in Stop 1 mode, 2.4 23.5 64.0 185 375 735 71.0 200 560 1200 2300
RTC disabled,
3.0 20.0 54.5 160 320 625 60.0 170 480 960 1900
8-Kbyte SRAM2 + ICACHE
retained 3.3 19.0 51.5 150 300 590 57.0 160 450 900 1800
3.6 19.0 50.0 145 285 560 57.0 150 440 860 1700
IDD(Stop 1) µA
1.8 28.0 78.0 235 455 1000 84.0 240 710 1400 3000
2.4 25.0 68.5 200 405 795 75.0 210 600 1300 2400
Supply current in Stop 1 mode,
RTC disabled, 3.0 21.5 58.0 170 340 675 65.0 180 510 1100 2100
All SRAMs retained
3.3 20.5 55.0 160 320 635 62.0 170 480 960 2000
3.6 20.5 53.5 155 310 605 62.0 170 470 930 1900

Electrical characteristics
157/307
 Table 54. Current consumption in Stop 1 mode on SMPS (continued)
158/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 26.0 73.0 215 400 945 78.0 220 650 1200 2900
Supply current in Stop 1 mode, 2.4 23.5 64.5 190 375 735 71.0 200 570 1200 2300
RTC(2) clocked by LSI 32 kHz,
3.0 20.5 55.0 160 320 625 62.0 170 480 960 1900
8-Kbyte SRAM2 + ICACHE
retained 3.3 19.5 52.0 150 300 590 59.0 160 450 900 1800
3.6 19.5 50.5 145 290 565 59.0 160 440 870 1700
1.8 26.5 73.4 220 410 970 66.0 180 630 930 2800
Supply current in Stop 1 mode,
2.4 23.9 64.8 190 380 730 71.0 190 560 1100 2200
RTC(2) clocked by LSE
IDD(Stop 1
bypassed at 32768 Hz, 3.0 20.5 55.0 164 325 640 62.0 170 470 930 1900 µA
with RTC)
8-Kbyte SRAM2 + ICACHE
3.3 19.5 52.4 153 305 600 59.0 160 440 890 1800
retained
DS14216 Rev 5

3.6 19.5 51.0 147 290 570 59.0 150 420 840 1700
1.8 26.0 73.0 215 400 945 - - - - -
Supply current in Stop 1 mode,
RTC(2) clocked by LSE quartz 2.4 23.5 64.5 190 375 735 - - - - -
in low-drive mode,
3.0 20.5 55.0 160 320 625 - - - - -
LSESYSEN = 0 in RCC_BDCR,
8-Kbyte SRAM2 + ICACHE 3.3 19.5 52.0 150 300 590 - - - - -
retained
3.6 19.5 50.5 145 290 565 - - - - -
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.

STM32U545xx
 STM32U545xx
Table 55. Current consumption during wake-up from Stop 1 mode on SMPS
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 40

Electrical charge consumed during wake-up from
QDD(wakeup from Stop 1) Wake-up clock is HSI 16 MHz 3.0 40 nAs
Stop 1 mode
Wake-up clock is MSI 1 MHz 70

Table 56. Current consumption in Stop 2 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 7.10 18.00 55.00 110.00 230.00 22.00 54.00 170.00 330.00 690.00
DS14216 Rev 5

Supply current in Stop 2 2.4 7.60 19.50 55.50 115.00 230.00 23.00 59.00 170.00 350.00 690.00
mode, RTC disabled,
3.0 7.80 21.50 56.00 115.00 230.00 24.00 65.00 170.00 350.00 690.00
8-Kbyte SRAM2 + ICACHE
retained 3.3 7.85 22.00 57.00 115.00 235.00 24.00 66.00 180.00 350.00 710.00
3.6 8.30 21.00 58.50 120.00 240.00 25.00 63.00 180.00 360.00 720.00
IDD(Stop 2) µA
1.8 11.00 27.50 84.50 175.00 365.00 33.00 83.00 260.00 530.00 1100.00
2.4 11.50 29.00 85.50 175.00 365.00 35.00 87.00 260.00 530.00 1100.00
Supply current in Stop 2
mode, RTC disabled, 3.0 12.00 31.50 85.50 180.00 370.00 36.00 95.00 260.00 540.00 1200.00
All SRAMs retained
3.3 12.00 32.50 86.50 180.00 370.00 36.00 98.00 260.00 540.00 1200.00
3.6 12.00 30.50 88.50 185.00 380.00 36.00 92.00 270.00 560.00 1200.00

Electrical characteristics
159/307
 Table 56. Current consumption in Stop 2 mode on LDO (continued)
160/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 7.40 18.00 55.00 115.00 230.00 23.00 54.00 170.00 350.00 690.00
Supply current in Stop 2
2.4 7.80 20.00 55.50 115.00 230.00 24.00 60.00 170.00 350.00 690.00
mode, RTC(2) clocked by
LSI 32 kHz, 3.0 8.20 22.00 56.00 115.00 230.00 25.00 66.00 170.00 350.00 690.00
8-Kbyte SRAM2 + ICACHE
3.3 8.30 22.00 57.00 115.00 235.00 25.00 66.00 180.00 350.00 710.00
retained
3.6 8.80 21.50 59.00 120.00 240.00 27.00 65.00 180.00 360.00 720.00
1.8 7.25 18.00 55.00 110.00 230.00 22.00 54.00 170.00 330.00 690.00
Supply current in Stop 2
2.4 7.60 19.50 55.50 115.00 230.00 23.00 59.00 170.00 350.00 690.00
mode, RTC(2) clocked by
LSI 250 Hz, 3.0 7.90 21.50 56.00 115.00 230.00 24.00 65.00 170.00 350.00 690.00
8-Kbyte SRAM2 + ICACHE
3.3 8.00 22.00 57.00 115.00 235.00 24.00 66.00 180.00 350.00 710.00
retained
DS14216 Rev 5

IDD(Stop 2 3.6 8.40 21.00 59.00 120.00 240.00 26.00 63.00 180.00 360.00 720.00
µA
with RTC) 1.8 7.30 18.50 56.00 110.00 235.00 22.00 53.00 170.00 330.00 680.00
Supply current in Stop 2
2.4 7.75 20.00 56.60 115.00 235.00 24.00 59.00 170.00 350.00 680.00
mode, RTC(2) clocked by
LSE bypassed at 32768 Hz, 3.0 8.10 22.00 57.00 115.00 235.00 25.00 65.00 170.00 350.00 690.00
8-Kbyte SRAM2 + ICACHE
3.3 8.30 22.50 58.00 115.00 245.00 25.00 66.00 170.00 350.00 690.00
retained
3.6 9.80 22.00 60.00 120.00 245.00 30.00 65.00 180.00 360.00 710.00
1.8 7.45 18.00 55.00 115.00 230.00 - - - - -
Supply current in Stop 2
mode, RTC(2) clocked by 2.4 7.85 20.00 56.00 115.00 230.00 - - - - -
LSE quartz in low-drive
3.0 8.20 22.00 56.50 115.00 230.00 - - - - -
mode,
8-Kbyte SRAM2 + ICACHE 3.3 8.25 22.50 57.00 115.00 235.00 - - - - -
retained
3.6 8.65 21.50 59.00 120.00 240.00 - - - - -

STM32U545xx
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
 Table 57. SRAM static power consumption in Stop 2 when supplied by LDO

STM32U545xx
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.9 2.1 6.3 12.6 28.5 2.8 6.3 19.0 38.0 86.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.2 0.5 1.5 3.2 6.6 0.7 1.5 4.5 9.7 20.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 1.1 2.8 8.4 17.3 37.8 3.3 8.4 26.0 52.0 120.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM4 static consumption
IDD(SRAM4) 0.3 0.6 2.0 4.1 8.4 0.9 1.8 6.0 13.0 26.0
(SRAM4PDS = 1 versus SRAM4PDS = 0)
µA
ICACHE SRAM static consumption
IDD(ICRAM) 0.2 0.4 1.3 2.7 5.6 0.5 1.2 3.9 8.2 17.0
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DS14216 Rev 5

DCACHE1 SRAM static consumption

IDD(DC1RAM) 0.1 0.2 0.8 1.6 3.0 0.3 0.6 2.4 4.9 9.2
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.1 0.1 0.5 0.9 1.7 0.3 0.3 1.5 2.7 5.1
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.1 0.2 0.7 1.4 3.0 0.2 0.6 2.2 4.4 8.9
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

Electrical characteristics
Table 58. Current consumption during wake-up from Stop 2 mode on LDO
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 30

Electrical charge consumed during wake-up from
161/307

QDD(wakeup from Stop 2) Wake-up clock is HSI 16 MHz 3.0 30 nAs

Stop 2 mode
Wake-up clock is MSI 1 MHz 70
 Table 59. Current consumption in Stop 2 mode on SMPS
162/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 3.70 9.9 30.5 64.5 135 11.0 30.0 90.0 190.0 400.0
Supply current in Stop 2 mode, 2.4 3.40 9.0 27.5 58.0 120 11.0 27.0 81.0 170.0 350.0
RTC disabled,
3.0 3.00 7.9 24.0 51.0 110 8.9 24.0 71.0 150.0 320.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 3.05 7.9 23.5 49.5 105 8.9 23.0 69.0 150.0 310.0
3.6 3.50 8.5 24.0 50.0 105 10.0 25.0 69.0 150.0 300.0
IDD(Stop 2) µA
1.8 5.90 15.0 46.5 100.0 210 18.0 45.0 140.0 300.0 620.0
2.4 5.35 13.5 41.5 88.0 185 16.0 41.0 130.0 260.0 550.0
Supply current in Stop 2 mode,
RTC disabled, 3.0 4.60 11.5 36.0 76.5 160 14.0 35.0 110.0 230.0 470.0
all SRAMs retained
3.3 4.60 11.5 34.5 73.5 155 14.0 34.0 110.0 220.0 460.0
DS14216 Rev 5

3.6 4.95 12.0 34.5 72.5 155 15.0 35.0 110.0 220.0 450.0

STM32U545xx
 Table 59. Current consumption in Stop 2 mode on SMPS (continued)

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 3.95 10.0 31.0 65.0 135 12.0 30.0 92.0 200.0 400.0
Supply current in Stop 2 mode, 2.4 3.70 9.3 28.0 58.0 120 11.0 28.0 83.0 170.0 350.0
RTC(2) clocked by LSI 32 kHz,
3.0 3.40 8.3 24.5 51.5 110 11.0 25.0 72.0 150.0 320.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 3.50 8.3 24.0 50.0 105 11.0 25.0 70.0 150.0 310.0
3.6 4.00 9.0 24.5 50.5 105 12.0 26.0 71.0 150.0 300.0
1.8 3.80 10.0 30.5 64.5 135 12.0 30.0 90.0 190.0 400.0
Supply current in Stop 2 mode, 2.4 3.50 9.1 27.5 58.0 120 11.0 27.0 81.0 170.0 350.0
RTC(2) clocked by LSI 250 Hz,
3.0 3.10 8.0 24.5 51.0 110 9.2 24.0 72.0 150.0 320.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 3.20 8.0 24.0 50.0 105 9.4 24.0 70.0 150.0 310.0
DS14216 Rev 5

IDD(Stop 2 3.6 3.65 8.6 24.5 50.5 105 11.0 25.0 71.0 150.0 300.0
µA
with RTC) 1.8 3.80 10.0 31.0 66.0 135 10.0 26.0 77.0 170.0 340.0
Supply current in Stop 2 mode,
2.4 3.65 9.1 28.0 59.0 120 11.0 27.0 80.0 170.0 350.0
RTC(2) clocked by LSE
bypassed at 32768 Hz, 3.0 3.30 8.1 24.5 52.0 110 9.8 24.0 71.0 150.0 310.0
8-Kbyte SRAM2 + ICACHE
3.3 3.45 8.2 24.2 50.0 105 11.0 24.0 69.0 150.0 290.0
retained
3.6 4.00 8.8 24.7 51.0 105 12.0 26.0 69.0 150.0 290.0
1.8 4.00 10.5 31.0 65.0 135 - - - - -
Supply current in Stop 2 mode,
2.4 3.70 9.3 28.0 58.5 120 - - - - -
RTC(2) clocked by LSE quartz in

Electrical characteristics
low-drive mode, 3.0 3.35 8.3 24.5 51.5 110 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 3.40 8.3 24.0 50.0 105 - - - - -
retained
3.6 3.90 8.9 24.5 50.5 105 - - - - -
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
163/307
 Table 60. SRAM static power consumption in Stop 2 when supplied by SMPS
164/307

Electrical characteristics
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.3 0.8 2.4 5.2 11.2 1.1 2.4 7.2 16.0 34.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.1 0.2 0.6 1.2 2.7 0.2 0.6 1.8 3.7 8.2
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 0.4 1.0 3.2 7.0 14.9 1.2 3.1 9.6 21.0 45.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM4 static consumption
IDD(SRAM4) 0.1 0.2 0.7 1.6 3.4 0.3 0.7 2.1 4.8 11.0
(SRAM4PDS = 1 versus SRAM4PDS = 0)
µA
ICACHE SRAM static consumption
IDD(ICRAM) 0.1 0.2 0.5 1.0 2.3 0.2 0.5 1.5 3.0 6.9
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DS14216 Rev 5

DCACHE1 SRAM static consumption

IDD(DC1RAM) 0.0 0.1 0.3 0.6 1.3 0.1 0.3 0.9 1.8 4.0
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.0 0.1 0.2 0.3 0.7 0.1 0.2 0.6 0.9 2.2
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.0 0.1 0.3 0.5 1.2 0.1 0.3 0.9 1.5 3.5
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

STM32U545xx
 STM32U545xx
Table 61. Current consumption during wake-up from Stop 2 mode on SMPS
Conditions Typ
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 30

Electrical charge consumed during wake-up from
QDD(wakeup from Stop 2) Wake-up clock is HSI 16 MHz 3.0 30 nAs
Stop 2 mode
Wake-up clock is MSI 1 MHz 70

Table 62. Current consumption in Stop 3 mode on LDO

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 4.10 12.5 38.5 83 175 13.0 38.0 120.0 250.0 520.0
DS14216 Rev 5

Supply current in Stop 3 mode, 2.4 4.25 12.0 39.0 84 180 13.0 36.0 120.0 250.0 530.0
RTC disabled,
3.0 4.55 12.0 39.5 86 180 14.0 36.0 120.0 260.0 530.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 4.60 12.5 40.5 87 185 14.0 37.0 120.0 260.0 550.0
3.6 5.70 14.5 42.5 90 185 17.0 43.0 130.0 270.0 540.0
IDD(Stop 3) µA
1.8 6.45 21.5 71.0 160 345 20.0 65.0 220.0 480.0 1100.0
2.4 7.35 20.0 71.5 160 350 22.0 60.0 220.0 480.0 1100.0
Supply current in Stop 3 mode,
RTC disabled, 3.0 7.90 20.5 72.0 160 350 24.0 62.0 220.0 480.0 1100.0
all SRAMs retained
3.3 7.70 20.5 73.0 165 355 23.0 61.0 220.0 490.0 1100.0
3.6 9.35 23.5 75.0 165 360 28.0 70.0 230.0 490.0 1100.0

Electrical characteristics
165/307
 Table 62. Current consumption in Stop 3 mode on LDO (continued)
166/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 4.25 12.5 38.5 84 175 13.0 38.0 120.0 250.0 520.0
Supply current in Stop 3 mode, 2.4 4.55 12.0 39.0 84 180 14.0 36.0 120.0 250.0 530.0
RTC(2) clocked by LSI 32 kHz,
3.0 4.90 12.5 40.0 86 180 15.0 38.0 120.0 260.0 530.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 5.10 13.0 41.0 87 185 16.0 39.0 130.0 260.0 550.0
3.6 6.20 15.0 43.0 90 190 19.0 44.0 130.0 270.0 560.0
1.8 3.90 12.5 38.5 83 175 12.0 38.0 120.0 250.0 520.0
Supply current in Stop 3 mode, 2.4 4.40 12.0 39.0 84 180 14.0 36.0 120.0 250.0 530.0
RTC(2) clocked by LSI 250 Hz,
3.0 4.75 12.5 40.0 86 180 15.0 38.0 120.0 260.0 530.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 4.75 12.5 41.0 87 185 14.0 37.0 130.0 260.0 550.0
DS14216 Rev 5

IDD(Stop 3 3.6 5.85 14.5 42.5 90 190 17.0 43.0 130.0 270.0 560.0
µA
with RTC) 1.8 4.30 12.8 39.5 85 180 13.0 38.0 120.0 250.0 520.0
Supply current in Stop 3 mode,
2.4 4.50 12.3 39.9 86 185 14.0 36.0 120.0 250.0 520.0
RTC(2) clocked by LSE
bypassed at 32768 Hz, 3.0 5.00 12.5 40.5 87 185 15.0 38.0 120.0 250.0 530.0
8-Kbyte SRAM2 + ICACHE
3.3 5.10 12.8 41.5 88 190 16.0 37.0 120.0 260.0 530.0
retained
3.6 6.05 15.5 43.5 92 190 18.0 46.0 130.0 270.0 540.0
1.8 4.20 13.0 39.0 84 175 - - - - -
Supply current in Stop 3 mode,
2.4 4.65 12.5 39.5 85 180 - - - - -
RTC(2) clocked by LSE quartz in
low-drive mode, 3.0 5.10 12.5 40.5 86 180 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 5.10 13.0 41.0 88 185 - - - - -
retained
3.6 6.25 15.0 43.0 90 190 - - - - -

STM32U545xx
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
 STM32U545xx
Table 63. SRAM static power consumption in Stop 3 when supplied by LDO
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.8 1.8 6.9 16.1 36.4 2.4 5.4 21.0 49.0 110.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.3 0.6 2.6 5.8 13.2 0.8 1.8 7.8 18.0 40.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 1.0 2.2 8.5 19.5 43.3 3.0 6.6 26.0 59.0 130.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM4 static consumption
IDD(SRAM4) 0.2 0.4 1.8 4.1 9.7 0.6 1.2 5.4 13.0 30.0
(SRAM4PDS = 1 versus SRAM4PDS = 0)
µA
ICACHE SRAM static consumption
IDD(ICRAM) 0.1 0.3 1.3 2.6 6.4 0.4 0.9 3.9 7.8 20.0
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DS14216 Rev 5

DCACHE1 SRAM static consumption

IDD(DC1RAM) 0.0 0.1 0.7 1.3 3.5 0.0 0.3 2.1 3.9 11.0
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.1 0.1 0.4 0.7 2.6 0.2 0.3 1.2 2.2 7.8
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.0 0.1 0.8 1.5 3.5 0.0 0.3 2.4 4.5 11.0
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

Electrical characteristics
167/307
168/307

Electrical characteristics
Table 64. Current consumption during wake-up from Stop 3 mode on LDO
Conditions Typ(1)
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 430

Electrical charge consumed during wake-up from
QDD(wakeup from Stop 3) Wake-up clock is HSI 16 MHz 3.0 410 nAs
Stop 3 mode
Wake-up clock is MSI 1 MHz 610
1. Evaluated by characterization in worse case condition (VDD11 = 0.7 V before wake-up).

Table 65. Current consumption in Stop 3 mode on SMPS

Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 1.75 5.65 19.5 43.5 95.0 5.2 17.0 57.0 130.0 280.0
DS14216 Rev 5

Supply current in Stop 3 mode, 2.4 1.50 4.65 16.0 36.0 79.5 4.4 14.0 47.0 110.0 230.0
RTC disabled,
3.0 1.40 4.25 14.5 32.5 72.5 4.1 13.0 42.0 93.0 210.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 1.55 4.40 14.5 32.5 71.5 4.4 13.0 42.0 93.0 210.0
3.6 2.05 5.15 15.5 33.5 72.5 5.6 15.0 44.0 94.0 210.0
IDD(Stop 3) µA
1.8 3.05 9.75 35.0 80.0 175.0 9.1 29.0 110.0 240.0 520.0
2.4 2.45 7.80 28.0 64.0 145.0 7.3 24.0 83.0 190.0 430.0
Supply current in Stop 3 mode,
RTC disabled, 3.0 2.20 6.90 24.5 56.0 125.0 6.5 21.0 72.0 170.0 370.0
all SRAMs retained
3.3 2.30 6.90 24.0 54.5 120.0 6.7 21.0 70.0 160.0 350.0
3.6 2.75 7.50 24.5 54.5 120.0 7.7 22.0 71.0 160.0 350.0

STM32U545xx
 Table 65. Current consumption in Stop 3 mode on SMPS (continued)

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 2.05 5.90 20.0 44.0 95.5 6.1 18.0 59.0 130.0 280.0
Supply current in Stop 3 mode, 2.4 1.80 5.00 16.5 36.5 80.0 5.3 15.0 48.0 110.0 230.0
RTC(2) clocked by LSI 32 kHz,
3.0 1.80 4.65 15.0 33.0 72.5 5.3 14.0 44.0 95.0 210.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 2.00 4.85 15.0 32.5 71.5 5.8 14.0 43.0 93.0 210.0
3.6 2.55 5.65 16.0 34.0 73.0 7.1 16.0 45.0 96.0 210.0
1.8 1.90 5.75 19.5 43.5 95.0 5.6 17.0 57.0 130.0 280.0
Supply current in Stop 3 mode, 2.4 1.60 4.75 16.0 36.0 79.5 4.7 14.0 47.0 110.0 230.0
RTC(2) clocked by LSI 250 Hz,
3.0 1.50 4.40 14.5 32.5 72.5 4.4 13.0 42.0 93.0 210.0
8-Kbyte SRAM2 + ICACHE
retained 3.3 1.65 4.55 14.5 32.5 71.5 4.7 13.0 42.0 93.0 210.0
DS14216 Rev 5

IDD(Stop 3 3.6 2.20 5.30 15.5 33.5 72.5 6.1 15.0 44.0 94.0 210.0
µA
with RTC) 1.8 1.95 5.70 19.5 44.0 97.0 5.8 17.0 56.0 130.0 270.0
Supply current in Stop 3 mode,
2.4 1.75 4.85 16.4 36.5 81.0 5.2 15.0 47.0 110.0 220.0
RTC(2) clocked by LSE bypassed
at 32768 Hz, 3.0 1.75 4.55 14.9 33.4 74.0 5.1 14.0 42.0 92.0 200.0
8-Kbyte SRAM2 + ICACHE
3.3 1.95 4.75 14.9 32.6 72.5 5.6 14.0 42.0 91.0 200.0
retained
3.6 2.50 5.55 15.9 33.5 73.5 7.0 16.0 44.0 93.0 200.0
1.8 2.15 6.05 20.0 44.0 96.0 - - - - -
Supply current in Stop 3 mode,
2.4 1.90 5.10 16.5 36.5 80.0 - - - - -
RTC(2) clocked by LSE quartz in

Electrical characteristics
low-drive mode, 3.0 1.85 4.75 15.0 33.0 73.0 - - - - -
8-Kbyte SRAM2 + ICACHE
3.3 2.00 4.95 15.0 33.0 72.0 - - - - -
retained
3.6 2.55 5.70 16.0 34.0 73.5 - - - - -
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
169/307
 Table 66. SRAM static power consumption in Stop 3 when supplied by SMPS
170/307

Electrical characteristics
Typ Max(1)
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

SRAM1 64-Kbyte page x static consumption

IDD(SRAM1_64kB)(2) 0.2 0.6 2.1 5.1 11.5 0.5 1.7 6.3 16.0 35.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8-Kbyte page 1 static consumption
IDD(SRAM2_8KB)(3) 0.1 0.2 0.8 1.8 4.0 0.2 0.7 2.4 5.4 12.0
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56-Kbyte page 2 static consumption
IDD(SRAM2_56KB)(3) 0.2 0.7 2.6 6.1 13.6 0.6 2.1 7.8 19.0 41.0
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)
SRAM4 static consumption
IDD(SRAM4) 0.0 0.1 0.5 1.3 2.9 0.1 0.4 1.5 3.9 8.8
(SRAM4PDS = 1 versus SRAM4PDS = 0)
µA
ICACHE SRAM static consumption
IDD(ICRAM) 0.0 0.1 0.4 0.9 1.9 0.1 0.3 1.2 2.8 5.8
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DS14216 Rev 5

DCACHE1 SRAM static consumption

IDD(DC1RAM) 0.0 0.0 0.2 0.5 1.0 0.1 0.2 0.6 1.5 3.0
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
FMAC, FDCAN and USB SRAM static consumption
IDD(PRAM) 0.0 0.0 0.1 0.3 0.6 0.0 0.1 0.3 0.9 1.9
(PRAMPDS = 1 versus PRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.0 0.0 0.2 0.5 1.1 0.1 0.2 0.6 1.5 3.4
(PKARAMPDS = 1 versus PKARAMPDS = 0)
1. Evaluated by characterization. Not tested in production.
2. SRAM1 total consumption is 3 × IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).

STM32U545xx
 STM32U545xx
Table 67. Current consumption during wake-up from Stop 3 mode on SMPS
Conditions Typ(1)
Symbol Parameter Unit
- VDD (V) 25°C

Wake-up clock is MSI 24 MHz 160

Electrical charge consumed during wake-up from
QDD(wakeup from Stop 3) Wake-up clock is HSI 16 MHz 3.0 150 nAs
Stop 3 mode
Wake-up clock is MSI 1 MHz 250
1. Evaluated by characterization in worse case condition (VDD11 = 0.7 V before wake-up).
DS14216 Rev 5

Electrical characteristics
171/307
 Table 68. Current consumption in Standby mode
172/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.20 0.66 3.07 8.19 21.80 0.34 1.50 6.70 18.00 47.00
2.4 0.22 0.71 3.24 8.55 22.80 0.41 1.60 7.10 19.00 49.00
No IWDG
3.0 0.31 0.92 3.75 9.54 24.70 0.61 2.10 8.40 21.00 54.00
ULPMEN = 1
3.3 0.52 1.33 4.59 10.90 27.20 1.20 3.10 11.00 25.00 60.00
3.6 1.10 2.29 6.32 13.60 31.40 2.60 5.50 15.00 32.00 70.00
1.8 0.27 0.71 3.01 7.94 21.30 0.42 1.50 6.70 18.00 46.00
2.4 0.30 0.76 3.17 8.27 22.00 0.49 1.70 7.00 19.00 48.00
No IWDG 3.0 0.38 0.97 3.66 9.19 23.80 0.69 2.20 8.30 21.00 53.00
3.3 0.59 1.37 4.49 10.50 26.20 1.20 3.20 11.00 24.00 59.00
DS14216 Rev 5

Supply current in
Standby mode (backup 3.6 1.16 2.32 6.21 13.20 30.50 2.70 5.50 15.00 31.00 69.00
IDD(Standby) µA
registers retained), 1.8 0.50 0.94 3.29 8.28 21.60 0.56 1.60 6.50 15.00 46.00
RTC disabled
2.4 0.60 1.07 3.52 8.69 22.40 0.71 1.80 7.00 16.00 49.00
with IWDG
clocked by 3.0 0.76 1.36 4.09 9.68 24.30 0.98 2.40 8.20 18.00 53.00
LSI 32 kHz
3.3 1.01 1.80 4.95 11.10 26.70 1.60 3.40 11.00 21.00 59.00
3.6 1.62 2.79 6.70 13.70 31.00 3.00 5.80 15.00 28.00 69.00
1.8 0.37 0.83 3.21 8.39 24.20 0.53 1.70 7.10 21.00 46.00
2.4 0.41 0.89 3.37 8.73 25.00 0.61 1.90 7.50 22.00 49.00
with IWDG
clocked by 3.0 0.50 1.11 3.89 9.71 27.00 0.83 2.40 8.80 25.00 53.00
LSI 250 Hz
3.3 0.72 1.53 4.73 11.10 29.60 1.40 3.40 11.00 28.00 59.00
3.6 1.31 2.49 6.47 13.80 34.10 2.80 5.80 16.00 35.00 69.00

STM32U545xx
 Table 68. Current consumption in Standby mode (continued)

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.52 0.98 3.36 8.54 24.30 0.58 1.70 6.80 18.00 46.00
2.4 0.62 1.10 3.58 8.93 25.20 0.73 1.90 7.30 19.00 49.00
RTC(2) clocked
by LSI 32 kHz, 3.0 0.78 1.39 4.16 9.98 27.30 1.00 2.50 8.60 21.00 53.00
no IWDG(3)
3.3 1.03 1.84 5.04 11.40 29.90 1.60 3.50 11.00 25.00 59.00
3.6 1.66 2.84 6.82 14.10 34.40 3.10 5.90 15.00 31.00 69.00
1.8 0.37 0.83 3.20 8.40 24.20 0.54 1.70 7.20 21.00 46.00
2.4 0.41 0.90 3.37 8.72 25.00 0.61 1.90 7.50 22.00 49.00
RTC(2) clocked
by LSI 250 Hz, 3.0 0.50 1.11 3.89 9.70 27.00 0.83 2.40 8.80 25.00 53.00
no IWDG(3)
3.3 0.73 1.53 4.73 11.10 29.60 1.40 3.40 11.00 28.00 59.00
DS14216 Rev 5

Supply current in
IDD(Standby with Standby mode (backup 3.6 1.31 2.50 6.48 13.80 34.10 2.80 5.80 16.00 35.00 69.00
µA
RTC) registers retained), 1.8 0.51 0.98 3.38 8.59 24.50 0.70 1.90 7.30 21.00 47.00
RTC enabled
RTC(2) clocked 2.4 0.58 1.08 3.58 8.97 25.30 0.85 2.10 7.80 22.00 49.00
by LSE
3.0 0.73 1.36 4.17 10.00 27.40 1.20 2.70 9.10 25.00 53.00
bypassed at
32768 Hz 3.3 0.99 1.82 5.05 11.50 30.10 1.70 3.80 12.00 29.00 59.00
3.6 1.64 2.85 6.87 14.20 34.70 3.20 6.20 16.00 35.00 70.00
1.8 0.62 1.11 3.52 8.60 22.10 - - - - -
RTC(2) clocked 2.4 0.66 1.18 3.70 8.97 22.90 - - - - -
by LSE quartz

Electrical characteristics
3.0 0.76 1.40 4.23 9.92 24.80 - - - - -
in low-drive
mode 3.3 0.99 1.83 5.07 11.30 27.20 - - - - -
3.6 1.59 2.81 6.82 14.00 31.50 - - - - -
173/307
 Table 68. Current consumption in Standby mode (continued)
174/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.15 0.28 0.63 1.25 2.40 0.47 0.84 1.90 3.80 7.20
Supply current to be 2.4 0.15 0.24 0.63 1.26 2.50 0.45 0.71 1.90 3.80 7.50
added in Standby mode
IDD(BKPSRAM) - 3.0 0.15 0.24 0.64 1.31 2.60 0.47 0.74 2.00 4.00 7.80
when backup SRAM is
retained 3.3 0.14 0.26 0.64 1.30 2.50 0.44 0.78 2.00 3.90 7.50
3.6 0.14 0.29 0.65 1.30 2.50 0.42 0.87 2.00 3.90 7.50
1.8 1.67 4.59 12.79 27.06 55.90 5.10 14.00 39.00 82.00 170.00
Supply current to be 2.4 1.68 4.45 12.83 27.23 56.20 5.10 14.00 39.00 82.00 170.00
added in Standby mode
IDD(SRAM2) 3.0 1.52 3.82 12.84 27.21 56.10 4.60 12.00 39.00 82.00 170.00 µA
when full SRAM2 and
BKPSRAM are retained 3.3 1.51 3.85 12.81 27.30 56.30 4.60 12.00 39.00 82.00 170.00
DS14216 Rev 5

3.6 1.87 4.29 12.79 27.10 56.00 5.70 13.00 39.00 82.00 170.00
LDO
1.8 0.57 1.34 4.02 8.36 17.10 1.80 4.10 13.00 26.00 52.00
Supply current to be
2.4 0.64 1.35 4.04 8.33 17.20 2.00 4.10 13.00 25.00 52.00
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte 3.0 0.64 1.40 4.04 8.41 17.10 2.00 4.30 13.00 26.00 52.00
page 1 and BKPSRAM
3.3 0.66 1.39 3.98 8.40 17.20 2.00 4.20 12.00 26.00 52.00
are retained
3.6 0.75 1.41 3.89 8.20 16.70 2.30 4.30 12.00 25.00 51.00

STM32U545xx
 Table 68. Current consumption in Standby mode (continued)

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.85 2.12 6.70 14.46 29.30 2.60 6.40 21.00 44.00 88.00
Supply current to be 2.4 0.77 1.89 5.80 12.53 26.00 2.40 5.70 18.00 38.00 78.00
added in Standby mode
IDD(SRAM2) 3.0 0.65 1.58 4.89 10.51 21.90 2.00 4.80 15.00 32.00 66.00
when full SRAM2 and
BKPSRAM are retained 3.3 0.62 1.45 4.48 9.70 20.20 1.90 4.40 14.00 30.00 61.00
3.6 0.57 1.31 3.99 8.90 18.70 1.80 4.00 12.00 27.00 57.00
SMPS µA
1.8 0.29 0.63 1.82 3.86 7.80 0.86 1.90 5.50 12.00 24.00
Supply current to be
2.4 0.29 0.63 1.78 3.73 7.80 0.87 1.90 5.40 12.00 24.00
added in Standby mode
IDD(SRAM2_8K) when SRAM2 8-Kbyte 3.0 0.25 0.51 1.47 3.11 6.50 0.76 1.60 4.50 9.40 20.00
page 1 and BKPSRAM
3.3 0.24 0.44 1.28 2.80 5.80 0.72 1.40 3.90 8.40 18.00
are retained
DS14216 Rev 5

3.6 0.22 0.36 0.99 2.30 5.00 0.66 1.10 3.00 6.90 15.00
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
3. Current consumption with IWDG enabled is similar.

Table 69. Current consumption during wake-up from Standby mode

Conditions Typ(1)
Symbol Parameter Unit
- VDD (V) 25°C

Electrical characteristics
Electrical charge consumed during wake-up from Wake-up clock is MSI 4 MHz
QDD(wakeup from Standby) 3.0 3.2 µAs
Standby mode Wake-up clock is MSI 1 MHz
1. Evaluated by characterization in worse case condition (VDD11 = 0.7 V before wake-up).
175/307
 Table 70. Current consumption in Shutdown mode
176/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.09 0.49 2.35 6.25 16.00 0.22 1.30 5.90 16.00 40.00
Supply current in 2.4 0.12 0.55 2.50 6.60 17.00 0.29 1.40 6.30 17.00 43.00
Shutdown mode (backup
IDD(Shutdown) registers retained), - 3.0 0.20 0.75 3.00 7.50 18.50 0.49 1.90 7.50 19.00 47.00
RTC disabled 3.3 0.40 1.15 3.80 8.85 21.00 0.99 2.90 9.50 23.00 53.00
3.6 0.97 2.10 5.50 11.50 25.00 2.50 5.30 14.00 29.00 63.00
1.8 0.32 0.75 2.70 6.90 18.50 0.48 1.60 6.30 17.00 43.00
2.4 0.40 0.86 2.90 7.25 19.00 0.61 1.80 6.70 18.00 45.00
RTC(2) clocked by
LSE bypassed at 3.0 0.56 1.15 3.50 8.25 21.50 0.89 2.40 8.10 20.00 50.00 µA
32768 Hz
3.3 0.80 1.60 4.35 9.65 24.00 1.50 3.40 11.00 24.00 56.00
DS14216 Rev 5

Supply current in
IDD(Shutdown Shutdown mode (backup 3.6 1.45 2.60 6.20 12.50 28.50 3.00 5.80 15.00 30.00 67.00
with RTC) registers retained), 1.8 0.44 0.88 2.85 6.85 17.00 - - - - -
RTC enabled
2.4 0.49 0.97 3.00 7.25 17.50 - - - - -
RTC(2) clocked by
LSE quartz in low- 3.0 0.59 1.20 3.55 8.20 19.50 - - - - -
drive mode
3.3 0.80 1.60 4.35 9.55 22.00 - - - - -
3.6 1.40 2.55 6.15 12.00 26.00 - - - - -
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration but RTC_CALR.LPCAL = 1.

Table 71. Current consumption during wake-up from Shutdown mode

Conditions Typ(1)
Symbol Parameter Unit

STM32U545xx
- VDD (V) 25°C

Electrical charge consumed during wake-up

QDD(wakeup from Shutdown) Wake-up clock is MSI 4 MHz 3.0 3.4 μAs
from Shutdown mode
1. Evaluated by characterization in worse case condition (VDD11 = 0.7 V before wake-up).
 Table 72. Current consumption in VBAT mode

STM32U545xx
Conditions Typ Max(1)
Symbol Parameter Unit
- VBAT (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.05 0.22 1.10 2.95 8.00 0.12 0.55 2.80 7.40 20.00
Supply current in 2.4 0.06 0.24 1.15 3.05 8.20 0.15 0.60 2.90 7.70 21.00
VBAT mode (backup
IDD(VBAT) registers retained), - 3.0 0.08 0.29 1.30 3.30 8.65 0.20 0.73 3.30 8.30 22.00
RTC disabled 3.3 0.15 0.40 1.50 3.60 9.15 0.37 1.00 3.80 9.00 23.00
3.6 0.31 0.66 1.90 4.25 10.00 0.77 1.70 4.80 11.00 25.00
1.8 0.28 0.47 1.50 3.40 8.60 0.37 0.83 3.20 7.90 21.00
2.4 0.30 0.50 1.65 3.60 8.90 0.41 0.89 3.50 8.30 22.00
RTC(2) clocked by LSE
3.0 0.33 0.56 1.85 3.95 9.40 0.47 1.10 3.90 9.00 23.00
bypassed at 32768 Hz
3.3 0.40 0.68 2.10 4.30 10.00 0.65 1.40 4.50 9.80 24.00
DS14216 Rev 5

3.6 0.58 0.96 2.65 5.00 11.00 1.10 2.00 5.60 12.00 27.00
µA
1.8 0.28 0.47 1.40 3.35 8.50 0.62 1.10 3.60 8.40 22.00
Supply current in 2.4 0.30 0.50 1.50 3.45 8.75 0.67 1.20 3.90 8.70 22.00
RTC(2) clocked by LSE
IDD(VBAT with VBAT mode (backup
bypassed at 32768 Hz, 3.0 0.32 0.56 1.70 3.75 9.25 0.74 1.40 4.30 9.50 24.00
RTC) registers retained),
RT C_CALR.LPCAL = 1
RTC enabled 3.3 0.40 0.68 1.95 4.10 9.80 0.93 1.70 5.00 11.00 25.00
3.6 0.58 0.96 2.40 4.80 11.00 1.40 2.40 6.20 13.00 28.00
1.8 0.45 0.65 1.60 3.50 8.75 - - - - -
2.4 0.51 0.73 1.70 3.65 9.00 - - - - -
RTC(2) clocked by LSE

Electrical characteristics
3.0 0.59 0.83 1.85 3.95 9.45 - - - - -
quartz in low-drive
3.3 0.69 0.98 2.10 4.30 10.00 - - - - -
3.6 0.89 1.30 2.60 5.00 11.00 - - - - -
177/307
 Table 72. Current consumption in VBAT mode (continued)
178/307

Electrical characteristics
Conditions Typ Max(1)
Symbol Parameter Unit
- VBAT (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 0.36 0.57 1.50 3.45 8.65 - - - - -

Supply current in RTC(2) clocked by LSE 2.4 0.39 0.60 1.55 3.55 8.85 - - - - -
IDD(VBAT with VBAT mode (backup quartz in low-drive
registers retained), 3.0 0.43 0.67 1.70 3.80 9.30 - - - - -
RTC) mode,
RTC enabled RT C_CALR.LPCAL = 1 3.3 0.51 0.80 1.95 4.15 9.85 - - - - -
3.6 0.70 1.10 2.40 4.80 11.00 - - - - -
µA
1.8 0.14 0.24 0.55 1.05 2.00 0.26 0.53 1.50 3.00 5.90
Supply current to be 2.4 0.15 0.24 0.55 1.05 2.30 0.27 0.54 1.50 3.00 6.80
IDD added in VBAT mode
- 3.0 0.15 0.23 0.50 1.05 2.35 0.27 0.51 1.40 3.00 6.90
(BKPSRAM) when backup SRAM
is retained 3.3 0.15 0.23 0.50 1.05 2.35 0.29 0.51 1.40 3.00 6.90
DS14216 Rev 5

3.6 0.16 0.24 0.55 1.05 2.50 0.31 0.56 1.50 3.00 7.40
1. Evaluated by characterization. Not tested in production.
2. RTC with default configuration except otherwise specified

STM32U545xx
STM32U545xx Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.15: I/O
port characteristics.
For the output pins, any internal or external pull-up or pull-down or external load must also
be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of the ADC input pins, that must be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the on-chip peripheral current consumption (see Table 73 for peripheral
current consumption in Run mode), the I/Os used by an application also contribute to the
current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal
and external) connected to the pin:

I SW = V DDIOx × f SW × C

where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
• VDDIOx is the I/O supply voltage.
• fSW is the I/O switching frequency.
• C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS.
• CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

DS14216 Rev 5 179/307

268
Electrical characteristics STM32U545xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the table below. The MCU is
placed under the following conditions:
• All I/O pins are in analog mode.
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• The ambient operating temperature and supply voltage conditions are summarized
in Table 33.
• The power consumption of the digital part of the on-chip peripherals is given in the table
below. The power consumption of the analog part of the peripherals (where applicable)
is indicated in each related section of the datasheet.

Table 73. Typical dynamic current consumption of peripherals

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2

AHB1 1.50 1.37 1.23 1.12 - 0.81 0.68 0.58 0.42 -

BKPSRAM 1.09 1.01 0.92 0.83 - 0.60 0.51 0.43 0.31 -
CORDIC 0.89 0.82 0.75 0.67 - 0.49 0.41 0.35 0.25 -
CRC 0.54 0.50 0.46 0.41 - 0.30 0.25 0.21 0.16 -
DCACHE1 0.65 0.60 0.55 0.49 - 0.36 0.30 0.25 0.19 -
FLASH 2.33 2.13 1.94 1.74 - 1.26 1.07 0.89 0.65 -
FMAC 2.18 1.99 1.82 1.64 - 1.18 1.00 0.84 0.61 -
AHB1

GPDMA1 3.19 2.91 2.64 2.39 - 1.72 1.46 1.23 0.89 -

GTZC1 0.13 0.13 0.12 0.11 - 0.08 0.06 0.05 0.04 -
ICACHE 0.46 0.43 0.39 0.35 - 0.26 0.21 0.18 0.13 -
µA/
MDF1 2.85 2.60 2.37 2.13 - 1.54 1.30 1.10 0.80 -
MHz
MDF1 indep(1) 0.57 0.52 0.47 0.43 - 0.31 0.26 0.22 0.16 -
RAMCFG 1.30 1.20 1.09 0.98 - 0.71 0.60 0.50 0.37 -
SRAM1 0.97 0.89 0.81 0.73 - 0.53 0.45 0.38 0.28 -
TSC 0.90 0.83 0.76 0.68 - 0.49 0.42 0.34 0.26 -
ADC1 2.32 2.13 1.93 1.74 - 1.25 1.06 0.91 0.65 -
ADC1 indep(1) 0.96 0.87 0.79 0.71 - 0.52 0.44 0.37 0.27 -
AES 2.34 2.13 1.93 1.74 - 1.26 1.06 0.90 0.66 -
AHB2

AHB2 1.36 1.26 1.13 1.02 - 0.74 0.63 0.53 0.39 -

DCMI 4.79 4.38 3.98 3.59 - 2.59 2.19 1.86 1.35 -
GPIOA 0.11 0.10 0.09 0.08 - 0.06 0.05 0.04 0.03 -

180/307 DS14216 Rev 5

STM32U545xx Electrical characteristics

Table 73. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2

GPIOB 0.04 0.04 0.03 0.03 - 0.03 0.02 0.01 0.01 -

GPIOC 0.15 0.14 0.13 0.11 - 0.09 0.07 0.06 0.04 -
GPIOD 0.05 0.05 0.05 0.04 - 0.03 0.02 0.02 0.01 -
GPIOE 0.06 0.05 0.05 0.04 - 0.03 0.03 0.02 0.02 -
GPIOG 0.22 0.20 0.18 0.16 - 0.12 0.10 0.08 0.06 -
GPIOH 0.09 0.08 0.07 0.07 - 0.05 0.04 0.03 0.02 -
HASH1 1.37 1.25 1.13 1.03 - 0.74 0.62 0.53 0.38 -
OCTOSPI1 1.02 0.93 0.84 0.76 - 0.55 0.46 0.39 0.29 -
OCTOSPI1
AHB2

1.08 0.97 0.88 0.79 - 0.58 0.49 0.41 0.30 -

indep(1)
OTFDEC1 2.01 1.83 1.66 1.49 - 1.09 0.91 0.77 0.56 -
PKA 7.09 6.48 5.89 5.31 - 3.82 3.24 2.74 2.00 -
RNG 0.96 0.88 0.80 0.72 - 0.52 0.44 0.37 0.27 -
(1)
RNG indep 0.08 0.06 0.06 0.05 - 0.04 0.04 0.03 0.03 -
SAES 3.34 3.05 2.77 2.50 - 1.80 1.52 1.29 0.94 -
µA/
SDMMC1 11.98 10.95 9.95 9.05 - 6.46 5.45 4.63 3.37 -
MHz
SDMMC1
1.37 1.26 1.13 0.01 - 0.76 0.63 0.53 0.01 -
indep(1)
SRAM2 1.23 1.12 1.01 0.91 - 0.66 0.56 0.48 0.34 -
ADC4 1.52 1.39 1.26 1.13 1.37 0.82 0.69 0.59 0.43 0.52
ADC4 indep(1) 2.07 1.90 1.71 1.55 1.56 1.12 0.95 0.81 0.58 0.59
ADF1 1.16 1.06 0.96 0.87 1.11 0.63 0.53 0.45 0.33 0.42
(1)
ADF1 indep 0.44 0.40 0.36 0.33 0.28 0.24 0.20 0.17 0.12 0.10
AHB3 0.29 0.28 0.26 0.23 - 0.17 0.15 0.12 0.09 -
DAC1 1.75 1.60 1.45 1.31 1.55 0.95 0.80 0.68 0.49 0.59
AHB3

DAC1 indep(1) 0.99 0.89 0.81 0.73 0.74 0.53 0.45 0.38 0.27 0.28
GTZC2 0.16 0.16 0.14 0.13 - 0.09 0.08 0.07 0.05 -
LPDMA1 0.35 0.32 0.29 0.26 0.49 0.19 0.16 0.14 0.10 0.19
LPGPIO1 0.06 0.05 0.05 0.04 0.27 0.03 0.03 0.02 0.02 0.11
PWR 0.24 0.22 0.19 0.18 - 0.13 0.11 0.09 0.07 -
SRAM4 0.46 0.43 0.39 0.35 0.23 0.25 0.21 0.18 0.13 0.09

DS14216 Rev 5 181/307

268
Electrical characteristics STM32U545xx

Table 73. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2

APB1 1.18 1.10 0.99 0.90 - 0.64 0.55 0.46 0.34 -

CRS 0.37 0.34 0.31 0.28 - 0.20 0.17 0.14 0.10 -
FDCAN1 5.29 4.84 4.41 4.04 - 2.84 2.41 2.04 1.49 -
FDCAN1
2.89 2.67 2.43 2.17 - 1.56 1.32 1.12 0.82 -
indep(1)
I2C1 0.90 0.82 0.75 0.68 - 0.49 0.41 0.34 0.25 -
I2C1 indep(1) 2.18 1.99 1.81 1.63 - 1.19 1.00 0.84 0.61 -
I2C2 3.08 2.80 2.56 2.30 - 1.66 1.40 1.18 0.86 -
(1)
I2C2 indep 2.24 2.05 1.86 1.68 - 1.21 1.02 0.86 0.63 -
I2C4 0.94 0.87 0.79 0.71 - 0.52 0.44 0.37 0.27 -
I2C4 indep(1) 2.28 2.09 1.89 1.71 - 1.24 1.04 0.88 0.64 -
LPTIM2 1.66 1.51 1.39 1.25 - 0.89 0.76 0.64 0.47 -
LPTIM2
4.15 3.79 3.45 3.11 - 2.24 1.90 1.61 1.17 -
indep(1)
SPI2 1.82 1.66 1.51 1.36 - 0.97 0.83 0.71 0.51 -
(1)
APB1

SPI2 indep 0.63 0.57 0.51 0.47 - 0.33 0.28 0.24 0.18 - µA/
MHz
TIM2 4.27 3.91 3.57 3.21 - 2.29 1.95 1.65 1.20 -
TIM3 4.03 3.69 3.37 3.03 - 2.16 1.84 1.56 1.14 -
TIM4 4.09 3.74 3.41 3.06 - 2.18 1.86 1.58 1.15 -
TIM5 3.92 3.59 3.27 2.94 - 2.10 1.79 1.52 1.11 -
TIM6 0.93 0.85 0.78 0.69 - 0.50 0.42 0.36 0.26 -
TIM7 0.91 0.83 0.76 0.68 - 0.49 0.42 0.35 0.26 -
UART4 2.03 1.85 1.68 1.51 - 1.08 0.93 0.78 0.57 -
UART4
3.54 3.23 2.93 2.64 - 1.91 1.62 1.36 0.99 -
indep(1)
UART5 2.11 1.92 1.75 1.57 - 1.13 0.97 0.81 0.59 -
UART5
3.54 3.23 2.94 2.64 - 1.91 1.62 1.37 0.99 -
indep(1)
USART3 2.35 2.14 1.95 1.75 - 1.26 1.07 0.90 0.66 -
USART3
4.36 3.97 3.62 3.25 - 2.33 1.98 1.68 1.22 -
indep(1)
WWDG 0.37 0.34 0.31 0.28 - 0.20 0.17 0.14 0.11 -

182/307 DS14216 Rev 5

STM32U545xx Electrical characteristics

Table 73. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2

APB2 0.94 0.87 0.79 0.72 - 0.51 0.44 0.37 0.27 -

SAI1 1.96 1.79 1.63 1.47 - 1.05 0.89 0.76 0.55 -
(1)
SAI1 indep 1.45 1.32 1.20 0.01 - 0.80 0.66 0.56 0.01 -
USBFS 3.71 3.40 3.09 2.85 - 1.99 1.70 1.43 1.05 -
USBFS
1.48 1.34 1.23 0.01 - 0.78 0.68 0.57 0.01 -
indep(1)
SPI1 2.00 1.83 1.66 1.50 - 1.06 0.91 0.77 0.56 -
SPI1 indep(1) 0.89 0.81 0.74 0.66 - 0.49 0.41 0.34 0.25 -
APB2

µA/
TIM1 6.26 5.72 5.21 4.70 - 3.36 2.86 2.43 1.77 - MHz

TIM15 3.49 3.20 2.91 2.62 - 1.87 1.60 1.35 0.98 -

TIM16 2.53 2.33 2.11 1.90 - 1.35 1.15 0.98 0.71 -
TIM17 2.83 2.59 2.35 2.19 - 1.52 1.29 1.09 0.80 -
TIM8 6.51 5.95 5.41 4.96 - 3.51 2.96 2.52 1.83 -
USART1 2.28 2.09 1.89 1.70 - 1.22 1.04 0.88 0.64 -
USART1
4.73 4.32 3.93 3.53 - 2.53 2.16 1.82 1.33 -
indep(1)

DS14216 Rev 5 183/307

268
Electrical characteristics STM32U545xx

Table 73. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2

APB3 0.40 0.39 0.35 0.32 - 0.23 0.19 0.16 0.12 -

COMP 0.22 0.20 0.19 0.16 0.01 0.12 0.10 0.08 0.06 0.01
I2C3 0.70 0.64 0.58 0.53 0.53 0.38 0.32 0.27 0.20 0.20
(1)
I2C3 indep 1.70 1.55 1.40 1.27 1.27 0.91 0.78 0.65 0.48 0.48
LPTIM1 1.09 0.99 0.90 0.81 0.82 0.59 0.49 0.42 0.31 0.31
LPTIM1
2.88 2.62 2.41 2.15 2.19 1.58 1.32 1.12 0.82 0.83
indep(1)
LPTIM3 1.03 0.94 0.85 0.76 0.77 0.56 0.46 0.40 0.29 0.29
LPTIM3
2.99 2.75 2.46 2.22 2.24 1.70 1.36 1.13 0.84 0.85
indep(1)
LPTIM4 0.64 0.59 0.53 0.48 0.48 0.35 0.29 0.25 0.18 0.18
APB3

µA/
LPTIM4 MHz
1.74 1.60 1.42 1.29 1.32 0.90 0.82 0.68 0.49 0.50
indep(1)
LPUART1 1.39 1.26 1.15 1.03 1.03 0.75 0.62 0.53 0.39 0.39
LPUART1
2.06 1.87 1.70 1.52 1.53 1.12 0.93 0.79 0.57 0.58
indep(1)
OPAMP 0.21 0.20 0.18 0.16 0.16 0.11 0.09 0.08 0.06 0.06
RTC 2.96 2.69 2.44 2.21 2.22 1.59 1.34 1.14 0.83 0.84
SPI3 1.55 1.41 1.28 1.15 1.15 0.84 0.70 0.60 0.43 0.44
(1)
SPI3 indep 0.57 0.51 0.46 0.42 0.42 0.30 0.26 0.22 0.16 0.16
SYSCFG 0.38 0.35 0.32 0.29 - 0.20 0.18 0.14 0.11 -
VREFBUF 0.12 0.11 0.10 0.09 0.09 0.07 0.05 0.04 0.04 0.04
1. indep stands for independent clock domain.

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5.3.7 Wake-up time from low-power modes and voltage scaling

transition times
The wake-up times given in the table below are the latency between the event and the
execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned).
The device goes in low-power mode after the WFE (wait for event) instruction.

Table 74. Low-power mode wake-up timings on LDO(1)

Typ Max
Mode Parameter Conditions Unit
(3 V, 30 °C) (3 V)

Nb of
Wake-up time from SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
Sleep to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.1 8.8
Wake-up in FLASH,
range 4, FLASHFWU = 1
MSI 24 MHz 2.35 2.5
and SRAM4FWU = 1 in
PWR_CR2
Wake-up in FLASH, MSI 24 MHz 11.0 12.0
Wake-up time from
range 4, FLASHFWU = 0
twu(Stop 0) Stop 0 to Run mode HSI 16 MHz 11.0 12.0
and SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 37.0 39.0
Wake-up in SRAM2, MSI 24 MHz 4.75 5.00
range 4, FLASHFWU = 0
HSI 16 MHz 6.75 7.4
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 34.0 36.0 µs
Wake-up in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 13.0 15.0
SRAM4FWU = 1 in
PWR_CR2
Wake-up in FLASH, MSI 24 MHz 22.0 24.0
Wake-up time from
FLASHFWU = 0 and
twu(Stop 1) Stop 1 to Run mode HSI 16 MHz 21.5 24.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 48.0 51.0
Wake-up in SRAM2, MSI 24 MHz 15.5 18.0
range 4, FLASHFWU = 0
HSI 16 MHz 17.5 20.0
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 45.0 48.0

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Table 74. Low-power mode wake-up timings on LDO(1) (continued)

Typ Max
Mode Parameter Conditions Unit
(3 V, 30 °C) (3 V)

Wake-up in FLASH,
SRAM4FWU = 1 in MSI 24 MHz 20.0 23.0
PWR_CR2
MSI 24 MHz 23.0 25.0
Wake-up in FLASH,
Wake-up time from
SRAM4FWU = 0 in HSI 16 MHz 22.5 25.0
twu(Stop 2) Stop 2 to Run mode
PWR_CR2
All SRAMs retained MSI 1 MHz 57.0 60.0
MSI 24 MHz 16.5 19.0
Wake-up in SRAM2,
range 4, SRAM4FWU = 0 HSI 16 MHz 18.5 21.0
in PWR_CR2
MSI 1 MHz 54.0 57.0
Wake-up in FLASH,
MSI 24 MHz 68.0 130
FSTEN = 0 in PWR_CR3
MSI 24 MHz 28.5 37.0
Wake-up in FLASH,
Wake-up time from HSI 16 MHz 28.0 36.0
FSTEN = 1 in PWR_CR3
twu(Stop 3) Stop 3 to Run mode
MSI 1 MHz 68.5 91.0 µs
All SRAMs retained
Wake-up in SRAM2, MSI 24 MHz 22.5 31.0
range 4, FLASHFWU = 0
HSI 16 MHz 24.0 32.0
and SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 64.5 85.0
Wake-up in FLASH,
MSI 4 MHz 64.5 110
Wake-up time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2
with SRAM2) Wake-up in FLASH, MSI 4 MHz 64.5 83.0
to Run mode
FSTEN = 1 in PWR_CR3 MSI 1 MHz 155 240
Wake-up in FLASH,
MSI 4 MHz 340 420
FSTEN = 0 in PWR_CR3
Wake-up time from
twu(Standby)
Standby to Run mode Wake-up in FLASH, MSI 4 MHz 100 130
FSTEN = 1 in PWR_CR3 MSI 1 MHz 210 290
Wake-up time from
twu(Shutdown) - MSI 4 MHz 610 710
Shutdown to Run mode
1. Evaluated by characterization and not tested in production, unless otherwise specified.

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Table 75. Low-power mode wake-up timings on SMPS(1)

Typ
Max
Mode Parameter Conditions (3 V, Unit
(3 V)
30 °C)

Nb of
Wake-up time from Sleep SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.1 8.8
Wake-up in FLASH, range 4,
FLASHFWU = 1 and
MSI 24 MHz 2.35 2.5
SRAM4FWU = 1 in
PWR_CR2
Wake-up in FLASH, range 4, MSI 24 MHz 11.0 12.0
Wake-up time from
FLASHFWU = 0 and
twu(Stop 0) Stop 0 to Run mode HSI 16 MHz 11.0 12.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 37.0 39.0
Wake-up in SRAM2, range 4, MSI 24 MHz 4.75 5.0
FLASHFWU = 0 and
HSI 16 MHz 6.75 7.4
SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 34.0 36.0
Wake-up in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 7.65 8.3
SRAM4FWU = 1 in
PWR_CR2
Wake-up in FLASH MSI 24 MHz 16.5 18.0 µs
Wake-up time from
FLASHFWU = 0 and
twu(Stop 1) Stop 1 to Run mode HSI 16 MHz 16.0 18.0
SRAM4FWU = 0 in
All SRAMs retained PWR_CR2 MSI 1 MHz 42.5 45.0
Wake-up in SRAM2, range 4, MSI 24 MHz 10.0 11.0
FLASHFWU = 0 and
HSI 16 MHz 12.0 13.0
SRAM4FWU = 0 in
PWR_CR2 MSI 1 MHz 39.5 42.0
Wake-up in FLASH
SRAM4FWU = 1 in MSI 24 MHz 17.5 19.0
PWR_CR2
MSI 24 MHz 20.5 22.0
Wake-up in FLASH
Wake-up time from
SRAM4FWU = 0 in HSI 16 MHz 20.0 22.0
twu(Stop 2) Stop 2 to Run mode
PWR_CR2
All SRAMs retained MSI 1 MHz 54.0 70.0
MSI 24 MHz 14.0 16.0
Wake-up in SRAM2, range 4,
SRAM4FWU = 0 in HSI 16 MHz 16.0 18.0
PWR_CR2
MSI 1 MHz 51.5 74.0

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Table 75. Low-power mode wake-up timings on SMPS(1) (continued)

Typ
Max
Mode Parameter Conditions (3 V, Unit
(3 V)
30 °C)

Wake-up in FLASH,
MSI 24 MHz 130 160
FSTEN = 0 in PWR_CR3
MSI 24 MHz 32.5 37.0
Wake-up in FLASH,
Wake-up time from HSI 16 MHz 32.0 36.0
FSTEN = 1 in PWR_CR3
twu(Stop 3) Stop 3 to Run mode
MSI 1 MHz 72.5 94.0
All SRAMs retained
MSI 24 MHz 26.5 31.0
Wake-up in SRAM2, range 4 HSI 16 MHz 28.0 32.0
MSI 1 MHz 68.5 89.0
Wake-up in FLASH, µs
MSI 4 MHz 61.5 80.0
Wake-up time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2 to
with SRAM2) Wake-up in FLASH, MSI 4 MHz 61.5 80.0
Run mode
FSTEN = 1 in PWR_CR3 MSI 1 MHz 150 240
Wake-up in FLASH,
MSI 4 MHz 340 420
FSTEN = 0 in PWR_CR3
Wake-up time from
twu(Standby)
Standby to Run mode Wake-up in FLASH, MSI 4 MHz 100 130
FSTEN = 1 in PWR_CR3 MSI 1 MHz 210 290
Wake-up time from
twu(Shutdown) - MSI 4 MHz 610 710
Shutdown to Run mode
1. Evaluated by characterization. Not tested in production.

Table 76. Regulator mode transition times(1)

Symbol Parameter Conditions Typ (3 V, 30 °C) Max (3 V) Unit

Range 4 16.0 20.0

Range 3 15.0 17.0
tLDO(2) SMPS to LDO transition time
Range 2 14.0 18.0
Range 1 14.0 16.0
µs
Range 4 14.0 16.0
Range 3 17.0 20.0
tSMPS(2) LDO to SMPS transition time
Range 2 16.0 19.0
Range 1 16.0 19.0

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Table 76. Regulator mode transition times(1) (continued)

Symbol Parameter Conditions Typ (3 V, 30 °C) Max (3 V) Unit

LDO 19.0 21.0

Range 4 to range 3
SMPS 25.0 38.0
LDO 13.0 15.0
Range 3 to range 2
SMPS 13.0 23.0
tVOST(3) µs
LDO 12.0 14.0
Range 2 to range 1
SMPS 12.0 17.0
LDO 42.0 47.0
Range 4 to range 1
SMPS 48.0 76.0
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Time to REGS change in PWR_SVMSR.
3. Time to VOSRDY = 1 in PWR_VOSR.

Table 77. Wake-up time using USART/LPUART(1)

Symbol Parameter Typ Max Unit

Wake-up time needed to calculate the maximum USART/LPUART baudrate

tWUUSART (2)
that is needed to wake up from Stop mode when the USART/LPUART kernel - μs
tWULPUART
clock source is HSI16/MSI.
1. Specified by design. Not tested in production.
2. This wake-up time is the HSI16 (see Table 82) or the MSI (see Table 83) oscillator maximum startup time.

5.3.8 External clock timing characteristics

High-speed external user clock generated from an external source
In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15: I/O port
characteristics. However, the recommended clock input waveform is shown in the figure
below.

Table 78. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Digital mode
(HSEBYP = 1, - - 55
HSEEXT = 1) Voltage scaling
User external clock Analog mode range 1, 2, 3
fHSE_ext MHz
source frequency (HSEBYP = 1, 4(2) - 50
HSEEXT = 0)
Voltage scaling
- 4(2) - 25
range 4

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Table 78. High-speed external user clock characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

OSC_IN input pin

VHSEH - 0.7 × VDD - VDD
high-level voltage
V
OSC_IN input pin low
VHSEL - VSS - 0.3 × VDD
level voltage
Digital mode
(HSEBYP = 1, Voltage scaling
7 - -
tw(HSEH) OSC_IN high or low HSEEXT = 1) range 1, 2, 3
ns
tw(HSEL) time Voltage scaling
18 - -
range 4
DuCyHSE OSC_IN duty cycle - 45 - 55 %
VHSE_ext_ OSC_IN peak-to-peak
- 0.2 - 2/3 VDD
PP amplitude V
Analog mode
VHSE_ext OSC_IN input range (HSEBYP = 1, - 0 - VDD
HSEEXT = 0)
tr(HSE), OSC_IN rise and fall 0.05 / 0.3 /
- - ns
tf(HSE) time fHSE_ext fHSE_ext
1. Specified by design. Not tested in production.
2. Only for Analog mode. No minimum value in digital mode.

Figure 27. AC timing diagram for high-speed external clock source (digital mode)
VHSE
tw(HSEH)

VHSEH
70%
30%
VHSEL
t
THSE tw(HSEL)
MSv67850V3

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Figure 28. AC timing diagram for high-speed external clock source (analog mode)
VHSE_ext

90%

VHSE_ext_PP

10%

tf(HSE) tr(HSE)
t

tHSE_ext = 1/fHSE_ext
MSv71538V1

Low-speed external user clock generated from an external source

In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15: I/O port
characteristics. However, the recommended clock input waveform is shown in Figure 29
and Figure 30.

Table 79. Low-speed external user clock characteristics(1)

Symbol Parameter Min Typ Max Unit

fLSE_ext User external clock source frequency 5 32.768 40 kHz

VLSE_ext_PP OSC32_IN peak-to-peak amplitude 0.3 - VSW
V
VLSE_ext OSC32_IN input range 0 - VSW
tw(LSEH)
OSC32_IN high or low time for square signal input 10 - - μs
tw(LSEL)
1. Specified by design. Not tested in production.

Figure 29. AC timing diagram for low-speed external square clock source
VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
30%
VLSEL
t
tLSE = 1/fLSE_ext tw(LSEL)
MSv67851V3

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Figure 30. AC timing diagram for low-speed external sinusoidal clock source

VLSE_ext

VLSE_ext_PP

tLSE_ext = 1/fLSE_ext
MSv69160V1

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in the table below.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins, in order to minimize the output distortion and startup
stabilization time. Refer to the crystal resonator manufacturer for more details on the
resonator characteristics (frequency, package, accuracy).

Table 80. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 8 mA
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 4 MHz - 790 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 8 MHz - 910 -
HSE current
IDD(HSE) VDD = 3 V, Rm = 45 Ω, CL = 10 pF @ 8 MHz - 930 -
consumption μA
VDD = 3 V, Rm = 30 Ω, CL = 5 pF @ 48 MHz - 1430 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 48 MHz - 1960 -
VDD = 3 V, Rm = 30 Ω, CL = 20 pF @ 48 MHz - 3000 -
Maximum critical crystal
Gmcritmax Startup - - 1.5 mA/V
transconductance Gm
tsu(HSE)
(4) Startup time VDD stabilized - 2 - ms

1. Specified by design. Not tested in production.

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2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 31. Typical application with a 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

MS19876V1

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in the table below. In the application,
the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 81. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

LSEDRV[1:0] = 00, low-drive capability - 410 -

LSE current LSEDRV[1:0] = 01, medium low-drive capability - 450 -

IDD(LSE) nA
consumption LSEDRV[1:0] = 10, medium high-drive capability - 590 -
LSEDRV[1:0] = 11, high-drive capability - 700 -
LSEDRV[1:0] = 00, low-drive capability - - 0.5

Maximum critical LSEDRV[1:0] = 01, medium low-drive capability - - 0.75

Gmcritmax µA/V
crystal Gm LSEDRV[1:0] = 10, medium high-drive capability - - 1.7
LSEDRV[1:0] = 11, high-drive capability - - 2.7

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Table 81. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

Internal stray
CS_PARA parasitic - - 3 - pF
capacitance(3)
tSU(LSE)(4) Startup time VDD is stabilized - 2 - s
1. Specified by design. Not tested in production.
2. Refer to the note below this table.
3. CS_PARA is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic
capacitances.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 32. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors
CL1
OSC32_IN fLSE
32.768 kHz resonator Drive
CS programmable
amplifier

OSC32_OUT
CL2
Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins
equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance. MSv70418V1

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

5.3.9 Internal clock timing characteristics

The parameters given in the table below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33. The provided curves
are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 82. HSI16 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 VDD = 3.0 V, TJ = 30 °C 15.92 16 16.08

TJ = –10 °C to 100 °C,
HSI16 frequency after factory 15.84 - 16.16
1.58 ≤ VDD ≤ 3.6 V MHz
fHSI16(1) calibration
TJ = –40 °C to 130 °C,
15.65 - 16.25
1.58 ≤ VDD ≤ 3.6 V
TRIM(2) HSI16 user trimming step - 18 29 40 kHz

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Table 82. HSI16 oscillator characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit
(2)
DuCy(HSI16) Duty cycle - 45 - 55 %
tsu(HSI16)(2) HSI16 oscillator startup time - - 2.5 3.6
μs
tstab(HSI16)(2) HSI16 oscillator stabilization time At 1% of target frequency - 4 6
IDD(HSI16)(2) HSI16 oscillator power consumption - - 150 210 μA
1. Evaluated by characterization. Not tested in production. It does not take into account package and soldering effects.
2. Specified by design. Not tested in production.

Figure 33. HSI16 frequency versus temperature and VDD

16.25
16.25
16.2
16.2
16.17
16.16
16.15
16.15
16.11
16.1 16.08

16.05

16
Frequency (MHz)

15.95

15.9 15.92
15.91

15.85 15.87
15.85
15.8
15.8
15.75

15.7

15.65 15.68
15.65
-40 -20 0 20 40 60 80 100 120
Temperature (°C)

+/-1% HSI16 min freq HSI16 max freq temp +/-1% -2%

MSv75106V1

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Multi-speed internal (MSI) RC oscillator

Table 83. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

MSI range 0
47.74 48 48.70
(MSIRC0)
MSI range 1 23.87 24 24.35
MSI range 2 15.91 16 16.23
MSI range 3 11.93 12 12.17
MSI range 4
3.98 4 4.06
(MSIRC1)
MSI range 5 1.99 2 2.03 MHz
MSI range 6 1.33 1.33 1.35
MSI range 7 0.99 1 1.01
MSI mode
MSI range 8
3.05 3.08 3.12
(MSIRC2)
MSI range 9 1.53 1.54 1.56
MSI range 10 1.02 1.03 1.04
MSI range 11 0.76 0.77 0.78
MSI range 12
397.68 400 405.71
(MSIRC3)
MSI frequency
VDD = 3 V MSI range 13 198.84 200 202.86
fMSI after factory kHz
TJ = 30 °C
calibration MSI range 14 132.56 133 135.24
MSI range 15 99.42 100 101.43
MSI range 0
- 48.005 -
(MSIRC0)
MSI range 1 - 24.003 -
MSI range 2 - 16.002 -
MSI range 3 - 12.001 -
MSI range 4
- 3.998 -
PLL (MSIRC1)
mode(2) MSI range 5 - 1.999 - MHz
XTAL =
32.768 kHz MSI range 6 - 1.333 -
MSI range 7 - 0.999 -
MSI range 8
- 3.08 -
(MSIRC2)
MSI range 9 - 1.54 -
MSI range 10 - 1.027 -
MSI range 11 - 0.77 -

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Table 83. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

MSI range 12
- 393 -
(MSIRC3)
MSI frequency PLL mode
VDD = 3 V MSI range 13 - 196.6 -
fMSI (cont’d) after factory XTAL = kHz
TJ = 30 °C
calibration 32.768 kHz MSI range 14 - 131 -
MSI range 15 - 98.3 -
MSI range 0, 4, 8, or 12 38 - 62
(3)
DuCy(MSI) Duty cycle MSI range 2, 6, 10, or 14 31 - 69
Other MSI ranges 48 - 52
User trimming
TRIM - - 0.4 -
step
MSI oscillator
frequency drift
(4) over
∆TEMP(MSI) MSI mode TJ = –40 to 130 °C -4 - 2
temperature
(reference is
30 °C)

MSI range 1.58 ≤ VDD ≤ 3.6 V -4 - 1

%
0 to 3 2.4 ≤ VDD ≤ 3.6 V -1 - 1

MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

MSI oscillator
4 to 7 2.4 ≤ VDD ≤ 3.6 V -1 - 1
frequency drift
∆VDD(MSI)(4) MSI mode
over VDD 1.58 ≤ VDD ≤ 3.6 V -3 - 1
MSI range
(reference is 3V)
8 to 11 2.4 ≤ VDD ≤ 3.6 V -1 - 1

MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

12 to 15 2.4 ≤ VDD ≤ 3.6 V -1 - 1
MSI frequency
∆FSAMPLING variation in
(3)(4) MSI mode TJ = –40 to 130 °C - - 0.2
(MSI) sampling mode
(MSIBIAS = 1)
MSI range 0 - 60 -
RMS MSI range 4 - 160 -
CC
cycle-to-cycle PLL mode
jitter(MSI)(3) MSI range 8 - 200 -
jitter
MSI range 12 - 1100 -
ps
MSI range 0 - 40 -
MSI range 4 - 130 -
P jitter(MSI)(3) RMS period jitter PLL mode
MSI range 8 - 170 -
MSI range 12 - 800 -

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Table 83. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

13
MSIRC0
MSI range 0 to 3 - - cycles +
11 MSI
cycles
4
MSIRC1
MSI range 4 to 7 - - cycles +
11 MSI
MSI oscillator cycles
tsu(MSI)(3)
startup time(5) 4

cycles
MSIRC2
MSI range 8 to 11 - - cycles +
11 MSI
cycles
4
MSIRC3
MSI range 12 to 15 - - cycles +
11 MSI
cycles
3
MSI oscillator destina-
tswitch(MSI)(3) - - -
transition time(6) tion MSI
cycles
Continuous
- - 10
Normal mode(7)
Final frequency µs
mode Sampling
- - 200
mode(8)
MSI oscillator PLL mode,
tstab(MSI)(3) All MSI 1% of final
stabilization time MSIPLL - - 0.8 ms
ranges frequency
FAST = 0
PLL mode,
cycles
MSIPLL All MSI ranges 2
FAST = 1
MSI range 0 to 3 - 6.6 -
MSI range 4 to 7 - 1.6 -
MSI PLL-mode LDO
oscillator power MSI range 8 to 11 - 1.4 -
MSIPLL
consumption MSI range 12 to 15 - 0.8 -
IDD(MSI_OFF EN = 1 and
(3) when MSI is µA
_PLLFAST) MSIPLL MSI range 0 to 3 - 4.7 -
disabled with
FAST = 1
PLL accuracy MSI range 4 to 7 - 1.4 -
retention SMPS
MSI range 8 to 11 - 1.3 -
MSI range 12 to 15 - 0.8 -

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Table 83. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

21 + 2.5
MSI range 0 to 3 - -
µA/MHz
LDO
19 + 2.5
MSI range 4 to 15 - -
Continuous µA/MHz
mode(7) 21 + 1,3
MSI range 0 to 3 - -
µA/MHz
SMPS(9)
19 + 1,3
MSI range 4 to 15 - -
MSI oscillator µA/MHz
IDD(MSI)(3) power 3 + 2.5 µA
consumption Range 0 to 3 - -
µA/MHz
LDO 1+
Range 4 to 15 - 2.5µA/ -
Sampling MHz
mode(8)
3+1
Range 0 to 3 - -
µA/MHz
SMPS
1+1
Range 4 to 15 - -
µA/MHz
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. In PLL mode, the MSI accuracy is the LSE crystal accuracy.
3. Specified by design. Not tested in production.
4. This is a deviation for an individual part once the initial frequency has been measured.
5. The MSI startup time is the time when the four MSIRCs are in power down.
6. This delay is the time to switch from one MSIRC to another one. In case the destination MSIRC is in power down, the total
delay is tsu(MSI) + tswitch(MSI).
7. The MSI is in continuous mode when the internal regulator is in voltage range 1, 2 or 3.
8. The MSI is in sampling mode when MSIBIAS = 1 in RCC_ICSCR1, and the regulator is in voltage range 4, or when the
device is in Stop 1 or Stop 2 mode.
9. SMPS efficiency in range 1, based on VCORE typical current.

High-speed internal 48 MHz (HSI48) RC oscillator

Table 84. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 frequency after factory calibration VDD = 3.0 V, TJ = 30 °C 47.5 48 48.5 MHz

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Table 84. HSI48 oscillator characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit
(1)
TRIM User trimming step - - 0.12 0.18
USER TRIM
User trimming coverage ±63 steps ±4.5 ±7.56 -
COVERAGE(2)
DuCy(HSI48)(1) Duty cycle - 45 - 55
Accuracy of the HSI48 oscillator over %
ACCHSI48_REL 1.58 V ≤ VDD ≤ 3.6 V,
(2) temperature (factory calibrated) -3 - 2
TJ = –40 to 125 °C
Reference is 3 V and 30 °C(3).
3.0 V ≤ VDD ≤ 3.6 V - 0.025 0.05
∆VDD(HSI48)(1) HSI48 frequency drift with VDD(4)
1.58 V ≤ VDD ≤ 3.6 V - 0.05 0.1
Next transition jitter
NT jitter(1) - - ±0.15 -
Accumulated jitter on 28 cycles(5)
ns
Paired transition jitter
PT jitter(1) - - ±0.25 -
Accumulated jitter on 56 cycles(5)
tsu(HSI48)(1) HSI48 oscillator startup time - - 2.5 6 μs
(1)
IDD(HSI48) HSI48 oscillator power consumption - - 350 400 μA
1. Specified by design. Not tested in production.
2. Evaluated by characterization. Not tested in production.
3. ∆fHSI = ACCHSI48_REL + ∆VDD.
4. These values are obtained with one of the following formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or
(Freq(3.6 V) - Freq(1.58 V)) / Freq(1.58 V).
5. Jitter measurements are performed without clock source activated in parallel.

Figure 34. HSI48 frequency versus temperature

MSv69123V1

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Secure high-speed internal (SHSI) RC oscillator

Table 85. SHSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fSHSI SHSI frequency - - 48 - MHz

tSU(SHSI) SHSI oscillator startup time - - 2.5 6 μs
IDD(SHSI) SHSI oscillator power consumption - - 350 400 μA
1. Specified by design. Not tested in production.

Low-speed internal (LSI) RC oscillator

Table 86. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0 31.4 - 32.6

fLSI LSI frequency VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1 0.245 - 0.255 kHz
1.58 V≤ VDD ≤ 3.6 V, TJ = –40 to 125 °C 30.4(1) - 33.6(1)
DuCy(LSI) LSI duty cycle LSIPREDIV = 1 - 50 - %
tSU(LSI) (2) LSI oscillator startup time - - 230 260
μs
(2)
tSTAB(LSI) LSI oscillator stabilization time 5% of final frequency - 230 260

LSI oscillator power LSIPREDIV = 0 - 140 255

IDD(LSI)(2) nA
consumption LSIPREDIV = 1 - 130 240
1. Evaluated by characterization. Not tested in production.
2. Specified by design. Not tested in production.

5.3.10 PLL characteristics

The parameters given in the table below are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 33.

Table 87. PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock - 4 - 16 MHz

fPLL_IN PLL input clock
- 10 - 90 %
duty cycle
Voltage scaling range 1 1 - 160(2)
PLL P, Q, R
fPLL_OUT Voltage scaling range 2 1 - 110
output clock
Voltage scaling range 3 1 - 55 MHz
Voltage scaling range 1, 2 128 - 544
fVCO_OUT PLL VCO output Voltage scaling range 3 128 - 330
Duty cycle with division 1 40 - 60 %

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Table 87. PLL characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Integer mode - 25 50
tLOCK(3)(4) PLL lock time μs
Fractional mode - 40 65

RMS cycle-to- Integer mode, VCO = 544 MHz - 20 -

cycle jitter Fractional mode, VCO = 544 MHz - 70 -
Integer mode, VCO = 544 MHz - 35 -
Jitter RMS period jitter ±ps
Fractional mode, VCO = 544 MHz - 45 -
Long-term Integer mode, VCO = 544 MHz - 160 -
jitter(5),
fPLL_IN = 8 MHz Fractional mode, VCO = 544 MHz - 170 -

VCO freq = 160 MHz,

Range 1 - 370 -
1 clock output
VCO freq = 160 MHz,
Range 1 - 390 -
3 clock outputs
PLL power Range 1 - 460 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2 - 435 -
VDD 1 clock output
with LDO Range 3 - 410 -
VCO freq = 336 MHz,
Range 1 - 710 -
1 clock output
VCO freq = 544 MHz,
Range 1 - 1100 -
1 clock output
μA
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 260 -
1 clock output
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 270 -
3 clock outputs
PLL power Range 1, IVCORE(6) = 19.4 mA - 320 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2, IVCORE(6) = 11.7 mA - 300 -
VDD 1 clock output
with SMPS Range 3, IVCORE(6) = 5.74 mA - 290 -
VCO freq = 336 MHz,
Range 1, IVCORE(6) = 19.4 mA - 470 -
1 clock output
VCO freq = 544 MHz,
Range 1, IVCORE(6) = 19.4 mA - 730 -
1 clock output
1. Specified by design and not tested in production, unless otherwise specified.
2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.
3. Evaluated by characterization. Not tested in production.
4. Lock time is the duration until PLLxRDY flag (2% of final frequency).
5. Measured on 5000 cycles.
6. SMPS efficiency based on CoreMark RUN current on VCORE at max frequency of each voltage range.

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5.3.11 Flash memory characteristics

Table 88. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max(2) Unit

Normal mode 118 118

tprog 128-bit programming time µs
Burst mode 48 48
fAHB = 160 MHz, normal mode 60.2 -
tprog_page One 8-Kbyte page programming time
fAHB = 160 MHz, burst mode 24.5 -
fAHB = 160 MHz, normal mode 7710 -
tprog_bank One 1-Mbyte bank programming time
fAHB = 160 MHz, burst mode 3140 -
ms
10 k endurance cycles 1.5 2.4
tERASE One 8-Kbyte page erase time
100 k endurance cycles 1.7 3.4
Mass erase time (one bank) 49 77
tME 10 k endurance cycles
Mass erase time (two banks) 98 154
Write mode 2.1 -
Average consumption from VDD
Erase mode 1.3 -
IDD(3) mA
Write mode 2.6 -
Maximum current (peak)
Erase mode 3.0 -
1. Specified by design. Not tested in production.
2. Evaluated by characterization after cycling. Not tested in production.
3. Evaluated by characterization. Not tested in production.

Table 89. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –40 to 125 °C 100 kcycles

TA = 85 °C after 1 kcycle(2) 30
TA = 105 °C after 1 kcycle(2) 15
(2)
TA = 125 °C after 1 kcycle 10
TA = 55 °C after 10 kcycles(2) 30
Whole bank
(2)
tRET Data retention TA = 85 °C after 10 kcycles 15 Years
TA = 105 °C after 10 kcycles(2) 10
(2)
TA = 55 °C after 100 kcycles 30
TA = 85 °C after 100 kcycles(2) 15
TA = 105 °C after 100 kcycles(2) 10
1. Evaluated by characterization. Not tested in production.
2. Cycling performed over the whole temperature range.

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5.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through the
I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The
failure is indicated by the LEDs as follows:
• Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in the table below. They are based on the EMS levels and classes
defined in application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).

Table 90. EMS characteristics

Level/
Symbol Parameter Conditions
Class

Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VFESD 3B
induce a functional disturbance LQFP100 conforming to IEC 61000-4-2
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VEFTB applied through 100 pF on VDD and VSS pins 5A
LQFP100 conforming to IEC 61000-4-4
to induce a functional disturbance

Designing hardened software to avoid noise problems

The EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. Note that good EMC performance is
highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened

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to prevent unrecoverable errors occurring. See application note Software techniques for
improving microcontrollers EMC performance (AN1015) for more details.

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard that specifies the test board and the pin loading.

Table 91. EMI characteristics for fHSE = 8 MHz and fHCLK = 160 MHz
Monitored frequency
Symbol Parameter Conditions Value Unit
band

0.1 MHz to 30 MHz 19

30 MHz to 130 MHz 14
Peak(1) VDD = 3.6 V, TA = 25 °C,
SEMI LQFP100 package compliant 130 MHz to 1 GHz 18 dBμV
with IEC 61967-2
1 GHz to 2 GHz 14
Level(2) 0.1 MHz to 2 GHz 3.5
1. Refer to the EMI radiated test section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
2. Refer to the EMI level classification section of the application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).

5.3.13 Electrical sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 92. ESD absolute maximum ratings(1)

Sym Max
Ratings Conditions Packages PINs Class Unit
bol value

Electrostatic discharge
VESD TA = 25 °C, conforming to
voltage (human body All All 2 2000
(HBM) model) ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge All except
VESD TA = 25 °C, conforming to C2a 500
voltage (charge device All PC15
(CDM) model) ANSI/ESDA/JEDEC JS-002
PC15 C1 250
1. Evaluated by characterization. Not tested in production.

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Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.

Table 93. Electrical sensitivities(1)

Symbol Parameter Conditions Class

LU Static latch-up class TA = +130 °C conforming to JESD78 Class II level A

1. Evaluated by characterization. Not tested in production.

5.3.14 I/O current injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating-input mode. While this current is injected
into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset
occurrence or oscillator frequency deviation).
The characterization results are given in the table below. The negative induced leakage
current is caused by the negative injection. The positive induced leakage current is caused
by the positive injection.

Table 94. I/O current injection susceptibility(1)(2)

Functional susceptibility
Symbol Description Unit
Negative injection Positive injection

Injected current on PA4 and PA5 pins 0 0

Injected current on other PA1, PA6, PA7, PB0,
IINJ 0 N/A mA
and PB1 pins
Injected current on all other pins 5 N/A
1. Evaluated by characterization. Not tested in production.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

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5.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the conditions summarized in Table 33. All I/Os are designed as
CMOS- and TTL-compliant.
Note: For information on GPIO configuration, refer to the application note ‘STM32 GPIO
configuration for hardware settings and low-power consumption’ (AN4899).

Table 95. I/O static characteristics(1)

Symbol

Unit
Parameter Conditions Min Typ Max

1.08 V ≤ VDDIOx ≤ 3.6 V - - 0.3 VDDIOx

I/O input
VIL(2) low-level All I/Os except FT_c - - 0.38 VDDIOx(3)
voltage
FT_c I/Os - - 0.3 VDDIOx
1.08 V ≤ VDDIOx ≤ 3.6 V 0.7 VDDIOx - - V
I/O input
VIH 0.5 VDDIOx
high-level All I/Os except FT_c - -
(2) + 0.2(3)
voltage
FT_c I/Os 0.7 VDDIOx - -
Vhys Input
(3) TT_xx, FT_xx I/Os - 250 - mV
hysteresis

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Table 95. I/O static characteristics(1) (continued)

Symbol

Unit
Parameter Conditions Min Typ Max

VIN ≤ Max (VDDXXX)(5) - - 150

all I/Os except FT_c, Max (VDDXXX) < VIN
- - 2000
FT_d, FT_o, FT_t, ≤ Max (VDDXXX) + 1 V(6)
FT_u,TT_xx
Max (VDDXXX) + 1 V < VIN
- - 500
≤ 5.5 V(6)
VIN ≤ Max (VDDXXX)(5) - - 1500
FT_c I/Os
(6)
Max (VDDXXX) < VIN ≤ 5 V - - 2000
VIN ≤ Max (VDDXXX)(5) - - 1500
FT_d I/Os
Max (VDDXXX) < VIN ≤ 5.5 V(6) - - 5000
VIN ≤ Max (VDDXXX )(5) - - 50

Input Max (VDDXXX) < VIN

Ilkg - - 500
FT_o I/Os ≤ Max (VDDXXX) + 1 V(6)
(3)(4) leakage
current Max (VDDXXX) + 1 V < VIN
- - 200
≤ 5.5 V(6)
nA
VIN ≤ Max (VDDXXX)(5) - - 200
Max (VDDXXX) < VIN
- - 2500
FT_u I/Os ≤ Max (VDDXXX) + 1 V(6)
Max (VDDXXX) + 1 V < VIN
- - 500
≤ 5.5 V(6)
VIN ≤ Max (VDDXXX)(5) - - 300
Max (VDDXXX) < VIN
- - 3000
FT_t I/Os ≤ Max (VDDXXX) + 1 V(6)
Max (VDDXXX) + 1 V < VIN
- - 600
≤ 5.5 V(6)
TT_xx I/Os except
Input OPAMPx_VINM VIN ≤ Max (VDDXXX)(5) - - 500
Ilkg (x = 1, 2)
(3)(4) leakage
current OPAMPx_VINM (x = 1, 2) dedicated input leakage (7)
- -
current
Weak
RPU pull-up - 30 40 50
equivalent
Weak kΩ
pull-down
RPD - 30 40 50
equivalent
resistor(8)
I/O pin
CIO - - 5 - pF
capacitance
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

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2. Refer to Figure 35: I/O input characteristics (all I/Os except BOOT0 and FT_c).
3. Specified by design. Not tested in production.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg max.
5. Max (VDDXXX) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as
described in Table 26: Legend/abbreviations used in the pinout table.
6. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.
7. Refer to Ibias in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in the figure below.

Figure 35. I/O input characteristics (all I/Os except BOOT0 and FT_c)

MSv69136V1

Output driving current

The GPIOs (except PC13, PC14, PC15) can sink or source up to ±8 mA, and sink or source
up to ± 20 mA (with a relaxed VOL/VOH). PC13, PC14, PC15 are limited in source capability:
+3 mA shared between the three I/Os. These GPIOs have the same sink capability than
other GPIOs.
In the user application, the number of I/O pins tat can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2: Absolute maximum ratings:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 31: Current characteristics).

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• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS
(see Table 31: Current characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 33. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

Table 96. Output voltage characteristics (all I/Os except FT_c,

FT_t in VBAT mode, and FT_o I/Os(1))(2)(3)
Symbol Parameter Conditions Min Max Unit

VOL Output low-level voltage CMOS port(4), |IIO| = 8 mA, - 0.4

VOH Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 -
VOL(5) Output low-level voltage TTL port(4),|IIO| = 8 mA, - 0.4
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V 2.4 -
VOL(5) Output low-level voltage All I/Os, |IIO| = 20 mA, - 1.3
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 1.3 -
VOL(5) Output low-level voltage |IIO| = 4 mA, - 0.4
VOH(5) Output high-level voltage 1.58 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 - V
VOL(5) Output low-level voltage |IIO| = 1 mA, - 0.4
VOH(5) Output high-level voltage 1.08 V ≤ VDDIOx <3.6 V VDDIOx - 0.4 -
|IIO| = 20 mA,
- 0.4
2.7 V ≤ VDDIOx ≤ 3.6 V
Output low-level voltage for |IIO| = 10 mA,
VOLFM+(5) - 0.4
a FT_f I/O pin in FM+ mode 1.58 V ≤ VDDIOx ≤ 3.6 V
|IIO| = 2 mA,
- 0.4
1.08 V ≤ VDDIOx < 3.6 V
1. FT_t I/O characteristics are degraded only in VBAT mode (refer to Table 97).
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 31:
Current characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
4. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
5. Specified by design. Not tested in production.

Table 97. Output voltage characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)
Symbol Parameter Conditions Min Max Unit

VOL Output low-level voltage - 0.4

|IIO| = 0.5 mA, 2.7 V ≤ VSW ≤ 3.6 V
VOH Output high-level voltage VSW - 0.4 -
V
VOL Output low-level voltage - 0.4
|IIO| = 0.25 mA, 1.58 V ≤ VSW ≤ 3.6 V
VOH Output high-level voltage VSW - 0.4 -

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1. Specified by design. Not tested in production.

Output AC characteristics
The definition and values of output AC characteristics are given in Figure 36: Output AC
characteristics definition and in the table below respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 33.

Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os(1))(2)(3)(4)
Speed Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5

CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5

Maximum frequency CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1
00
CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 17
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33

Output rise and fall time CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 85
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 25
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 50
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 2.5

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5
CL = 10 pF, 1.08 V ≤ VDDIOx ≤<1.58 V - 2.5
01
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 5.8
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 18
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 4.2
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 7.5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 12

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Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os(1))(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit

CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V (5)

- 100
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
10
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 13.3
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.2
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)
Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
Fmax MHz
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 140(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5

11
FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 166(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 13.3
tr/tf All I/Os except FT_c, FT_v, ns
and TT_v CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V 2.0(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V 9.2

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Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os(1))(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit
(5)
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2.5
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.0(5)

11 Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 11
tr/tf ns
(cont’d) FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 1.66(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 7
Fmax Maximum frequency CL = 550 pF, 1.08 V ≤ VDDIOx < 3.6 V - 1 MHz
CL = 100 pF, 1.58 V ≤ VDDIOx < 3.6 V - 50
Fm+ CL = 100 pF, 1.08 V ≤ VDDIOx < 1.58 V - 80
tf Output fall time(6) ns
CL = 550 pF, 1.58 V ≤ VDDIOx < 3.6 V - 100
CL = 550 pF, 1.08 V ≤ VDDIOx < 1.58 V - 220
1. FT_t I/O characteristics are degraded only in VBAT mode (refer to Table 101).
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO
port configuration register.
4. Specified by design. Not tested in production.
5. Compensation system enabled.
6. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

Table 99. Output AC characteristics, HSLV ON (all I/Os except FT_c)(1)(2)(3)(4)

Speed Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10

CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 15
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
00
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 18
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 32
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 21

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Table 99. Output AC characteristics, HSLV ON (all I/Os except FT_c)(1)(2)(3)(4) (continued)
Speed Symbol Parameter Conditions Min Max Unit

CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50

CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 67
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
01
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.3
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10.6
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5.6
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
10
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4.7
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
11 Fmax MHz
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 110(5)

Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 25

FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 150(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 25
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5)
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V 4.7
11 tr/tf ns
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.0(5)

Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 6.6
FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 1.6(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 3.4
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.

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3. Specified by design. Not tested in production.

4. FT_t I/O characteristics are degraded in VBAT mode (refer to Table 101).
5. Compensation system enabled.

Table 100. Output AC characteristics for FT_c I/Os(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 10

Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
00
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 33
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 66
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 25
Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10
01
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 13
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 40
Fmax Maximum frequency MHz
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 20
1x
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 8
tr/tf Output rise and fall time ns
All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 17
1. Specified by design. Not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.

Table 101. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)
Symbol Parameter Conditions Min Max Unit

CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V - 0.5

Fmax Maximum frequency MHz
CL = 50 pF, 1.58 V ≤ VSW < 2.7 V - 0.25
CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V - 400
tr/tf Output rise and fall time ns
CL = 50 pF, 1.58 V ≤ VSW < 2.7 V - 900
1. Specified by design. Not tested in production.

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Figure 36. Output AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.

5.3.16 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized
in Table 33.

Table 102. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low-level voltage - - - 0.3 x VDDIOx

V
VIH(NRST) NRST input high-level voltage - 0.7 x VDDIOx - -
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
tF(NRST) NRST input filtered pulse - - - 50
1.71 V ≤ VDD ≤ 3.6 V 330 - - ns
tNF(NRST) NRST input not-filtered pulse
1.58 V ≤ VDD ≤ 3.6 V 1000 - -
1. Specified by design. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).

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Figure 37. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF(3)

MS19878V4

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table.
Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.17 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 103. EXTI input characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

1. Specified by design. Not tested in production.

5.3.18 Analog switches booster

Table 104. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.6 1.8 3.6 V

tSU(BOOST) Booster startup time - - 50 µs
IDD(BOOST) Booster consumption - - 125 µA
1. Specified by design. Not tested in production.

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5.3.19 14-bit analog-to-digital converter (ADC1) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 33.
Note: It is recommended to perform a calibration after each power-up.

Table 105. 14-bit ADC1 characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog power supply for

VDDA - 1.62 - 3.6
ADC ON

Positive reference VDDA ≥ 2 V 2 - VDDA

VREF+ V
voltage VDDA < 2 V VDDA
Negative reference
VREF- - VSSA
voltage
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 5(3) - 55 MHz
fADC
ADC clock ratio - 45 - 55 %
Resolution = 14 bits 0.23 - 2.5
Resolution = 12 bits 0.25 - 2.75
fs Sampling rate Msps
Resolution = 10 bits 0.28 - 3.05
Resolution = 8 bits 0.31 - 3.44
tTRIG External trigger period Resolution = 14 bits 26 - - 1/fADC
Conversion voltage
VAIN(4) - 0 - VREF+
range
V
Common mode input
VCIMV - VREF+/2 - 10% VREF+/2 VREF+/2 + 10%
voltage
Resolution = 14 bits
- - 1000
Tj = 130 °C
Resolution = 12 bits
- - 1000
External input Tj = 130 °C
RAIN(5) Ω
impedance Resolution = 10 bits
- - 4700
Tj = 130 °C
Resolution = 8 bits
- - 22000
Tj = 130 °C
Internal sample and
CADC - - 5 - pF
hold capacitor
tADCVREG_
ADC LDO startup time - - - 17 µs
STUP

tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
Offset and linearity
tCAL - 31849
calibration time 1/fADC
tOFF_CAL Offset calibration time - 885

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Table 105. 14-bit ADC1 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Trigger conversion PRESC = 0 3

latency for regular and
PRESC = 1 7
tLATR injected channels,
without aborting the
PRESC = 2 13
conversion
Trigger conversion PRESC = 0 4
latency Injected 1/fADC
tLATRINJ PRESC = 1 9
channels aborting a
regular conversion PRESC = 2 17
ts Sampling time - 5 - 814
Total conversion time
tCONV (including sampling Resolution = N bits ts + N + 3
time)
fs = 2.5 Msps,
- 970 -
resolution = 14 bits
fs = 1 Msps,
- 550 -
resolution = 14 bits
fs = 10 ksps,
- 130 -
ADC consumption on resolution = 14 bits
IDDA_D(ADC)
VDDA Differential mode fs = 2.5 Msps,
- 940 -
resolution = 12 bits
fs = 2.5 Msps,
- 840 -
resolution = 10 bits
fs = 2.5 Msps,
- 730 -
resolution = 8bits
µA
fs = 2.5 Msps,
- 140 -
resolution = 14 bits
fs = 1 Msps,
- 80 -
resolution = 14 bits
fs = 10 ksps,
- 13 -
ADC consumption on resolution = 14 bits
IDDV_D(ADC)
VREF+ Differential mode f = 2.5 Msps,
s - 140 -
resolution = 12 bits
fs = 2.5 Msps,
- 140 -
resolution = 10 bits
fs = 2.5 Msps,
- 120 -
resolution = 8bits

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Table 105. 14-bit ADC1 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fs = 2.5 Msps,
- 980 -
resolution = 14 bits
fs = 1 Msps,
- 550 -
resolution = 14 bits
fs = 10 ksps,
ADC consumption on - 130 -
resolution = 14 bits
IDDA_s(ADC) VDDA Singe-ended
mode fs = 2.5 Msps,
- 900 -
resolution = 12 bits
fs = 2.5 Msps,
- 840 -
resolution = 10 bits
fs = 2.5 Msps,
- 770 -
resolution = 8bits
µA
fs = 2.5 Msps,
- 160 -
resolution = 14 bits
fs = 1 Msps,
- 90 -
resolution = 14 bits
fs = 10 ksps,
ADC consumption on - 15 -
resolution = 14 bits
IDDV_s(ADC) VREF+ Single-ended
mode fs = 2.5 Msps,
- 150 -
resolution = 12 bits
fs = 2.5 Msps,
- 150 -
resolution = 10 bits
fs = 2.5 Msps,
- 150 -
resolution = 8bits
1. Specified by design. Not tested in production.
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Degraded differential linearity error below 10 MHz.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
5. The maximum value of Rain is specified to keep leakage induced offset within the specified tolerance. The tolerance is
4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.

The maximum value of RAIN can be found in the table below.

Table 106. Maximum RAIN for 14-bit ADC1(1)(2) (3)

Resolution(4) RAIN max (Ω)(5) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz

47 142
14 bits 68 145 5 12
100 170

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Table 106. Maximum RAIN for 14-bit ADC1(1)(2) (3) (continued)

Resolution(4) RAIN max (Ω)(5) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz

47 135
68 135
100 140
12 bits 150 145
220 150
330 155
470 180
47 128
12
68 130
100 132
150 134
220 140
10 bits 330 146
470 160
680 176
1000 200
1500 240 5
20
2200 320
47 123
68 124
100 125
150 128
220 130
12
330 137
470 140
8 bits 680 157
1000 178
1500 204
2200 250
20
3300 313
4700 400
36
6800 546
10000 830 68
1. Specified by design. Not tested in production.
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.

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4. The tolerance is 2 LSBs for 14 bits and 1 LSB for other resolutions.
5. The maximum value of RAIN is obtained in a worst-case scenario: channel conversion in scan mode with channel i
connected to VREF+ and channel i + 1 connected to VREF-.

Table 107. 14-bit ADC1 accuracy(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Single ended - ±6 ± 12
ET Total unadjusted error
Differential - ±3 ±6
Single ended - ±6 ±12(5)
EO Offset error
Differential - ±2 ±6(5)
Single ended - ±5 ±10
EG Gain error
Differential - ±2.5 ±5
LSB
Single ended -
fADC ≥ 10 MHz -0.9/+1.5 -0.9/+2.5
Differential -
ED Differential linearity error
Single ended -
fADC < 10 MHz -0.9/+1.5 -1/+3
Differential -
Single ended - ±3 ±7
EL Integral linearity error
Differential - ±2 ±5
Single ended 11 12 -
ENOB Effective number of bits bits
Differential 11.8 12.8 -

Signal-to-noise and Single ended 68 74 -

SINAD
distortion ratio Differential 73 78 -
Single ended 68 74 -
SNR Signal-to-noise ratio dB
Differential 73 78 -
Single ended - -84 -80
THD Total harmonic distortion
Differential - -95 -89
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. Extended calibration mode activated.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). The booster is disabled when VDDA ≥ 2.4 V. Resolution = 14 bits, no oversampling.
5. This parameter may degrade in case of digital activity on adjacent I/Os.

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Figure 38. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 39. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to the ADCx characteristic table for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(refer to Table 95: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the
conversion accuracy. To remedy this, fADC must be reduced.
3. Refer to Table 95: I/O static characteristics for the values of Ilkg.
4. Refer to Section 5.1.6: Power supply scheme.

General PCB design guidelines

The power-supply decoupling must be performed as shown in the corresponding
power-supply scheme. The 100 nF capacitor must be ceramic (good quality) and must be
placed as close as possible to the chip.

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5.3.20 12-bit analog-to-digital converter (ADC4) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 33.
Note: It is recommended to perform a calibration after each power-up.

Table 108. 12-bit ADC4 characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog power supply for ADC

VDDA - 1.62 - 3.6
ON
V
VREF+ Positive reference voltage - 1 - VDDA
VREF- Negative reference voltage - VSSA
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 0.14 - 55 MHz
fADC
ADC clock duty cycle - 45 - 55 %
Resolution = 12 bits 0.01 - 2.75
Resolution = 10 bits 0.012 - 3.05
fs Sampling rate Msps
Resolution = 8 bits 0.014 - 3.43
Resolution = 6 bits 0.0175 - 3.92
tTRIG External trigger period Resolution = 12 bits 16 - - 1/fADC
(3)
VAIN Conversion voltage range - 0 - VREF+ V
Resolution = 12 bits - - 2.2

External input impedance Resolution = 10 bits - - 6.8

RAIN(4) kΩ
Tj = 130 °C Resolution = 8 bits - - 33.0
Resolution = 6 bits - - 47.0
Internal sample and hold
CADC - - 5 - pF
capacitor
tADCVREG_
ADC LDO startup ready flag time - - - 25 µs
STUP

tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
tOFF_CAL Offset calibration time - - 123 -
WAIT = 0, AUTOFF = 0,
4
DPD = 0, fADC = HCLK
WAIT = 0, AUTOFF = 0,
tLATR Trigger conversion latency 4 1/fADC
DPD = 0, fADC = HCLK/2
WAIT = 0, AUTOFF = 0,
3.75
DPD = 0, fADC = HCLK/4
ts Sampling time - 1.5 - 814.5

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Table 108. 12-bit ADC4 characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Resolution = N bits,
ts + N + 0.5
VREFPROTEN = 0
Resolution = N bits,
Total conversion time (including VREFPROTEN = 1 ts + N + 0.5 - ts + N + 1.5
tCONV 1/fADC
sampling time) VREFSECSMP = 0
Resolution = N bits,
VREFPROTEN = 1 ts + N + 0.5 - ts + N + 2.5
VREFSECSMP = 1
fs = 2.5 Msps - 360 -
fs = 1 Msps - 180 -
fs = 10 ksps - 10 -
IDDA(ADC) ADC consumption on VDDA
AUTOFF = 1, DPD = 0,
- 9 -
no conversion
AUTOFF = 1, DPD = 1,
- 0.1 -
no conversion
µA
fs = 2.5 Msps - 18 -
fs = 1 Msps - 10.2 -
fs = 10 ksps - 0.12 -
IDDV(ADC) ADC consumption on VREF+
AUTOFF = 1, DPD = 0,
- 0.01 -
no conversion
AUTOFF = 1, DPD = 1,
- 0.01 -
no conversion
1. Specified by design. Not tested in production.
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
4. The maximum value of Rain is specified to keep leakage induced offset within the specified tolerance. The tolerance is
2 LSBs.

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The maximum value of RAIN can be found in the table below.

Table 109. Maximum RAIN for 12-bit ADC4(1)(2)(3)

Resolution(4) RAIN max (Ω)(5) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

47 276
68 288
12.5 19.5
100 306
150 336
220 377
330 442 19.5
39.5
470 526
680 650
1000 840 39.5
12 bits 79.5
1500 1134
2200 1643 79.5
3300 2395
4700 3342
6800 4754 814.5
10000 6840 814.5
15000 9967
22000 14068
33000 19933 N/A
47 86
68 90 3.5
100 95
7.5
150 108
220 116
330 136 7.5
470 161
10 bits 12.5
680 212
1000 276 12.5 19.5
1500 376 39.5
19.5
2200 516
3300 735 79.5
39.5
4700 1012
6800 1423 79.5 814.5

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Table 109. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

Resolution(4) RAIN max (Ω)(5) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

10000 2040
15000 2978
10 bits
22000 4356 814.5 814.5
(cont’d)
33000 6443
47000 8925
47 45
68 46
100 48 3.5
150 53 3.5
220 59
330 69
470 81
7.5
680 101
1000 130 7.5
8 bits 1500 177 12.5
2200 242
12.5 19.5
3300 345
4700 475 19.5
39.5
6800 670
39.5
10000 963
79.5
15000 1417
79.5
22000 2040
33000 2995 814.5
814.5
47000 4158
47 32
68 32
100 33
6 bits 1.5 3.5
150 35
220 37
330 41

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Table 109. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

Resolution(4) RAIN max (Ω)(5) Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

470 49
3.5
680 61 3.5
1000 79
7.5
1500 106
2200 146 7.5
12.5
3300 207
6 bits (cont’d)
4700 286 12.5 19.5
6800 404 19.5
39.5
10000 584 39.5
22000 1250 79.5
79.5
33000 1853
814.5
47000 2607 814.5
1. Specified by design. Not tested in production.
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.
4. The tolerance is 2 LSBs for 14 bits and 1 LSB for other resolutions.
5. The maximum value of RAIN is obtained in a worst-case scenario: channel conversion in scan mode with channel i
connected to VREF+ and channel i + 1 connected to VREF-.

Table 110. 12-bit ADC4 accuracy(1)(2) (3)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - - ±3 ±7.5

EO Offset error - - ±2 ±5.5
EG Gain error - - ±2 ±6.5 LSB
ED Differential linearity error - - -0.9/+1 -0.9/+1.5
EL Integral linearity error - - ±2 ±3.5
ENOB Effective number of bits - 9.9 10.9 - bits
SINAD Signal-to-noise and distortion ratio - 61.4 67.4 -
SNR Signal-to-noise ratio - 61.6 67.5 - dB
THD Total harmonic distortion - - -74 -70
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). This switch is disabled when VDDA ≥ 2.4 V. Resolution = 12 bits, no oversampling.

See Figure 38: ADC accuracy characteristics, Figure 39: Typical connection diagram when
using the ADC with FT/TT pins featuring analog switch function and General PCB design
guidelines.

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5.3.21 Temperature sensor characteristics

Table 111. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - - 1.3 °C

(1)
Avg_Slope Average slope 2 2.5 3.0 mV/°C
V30(2) Voltage at 30°C (±5 °C) 700 752 800
∆(Vcontinuous - Difference of voltage between continuous and mV
- - –10/+4
Vsampling)(3) sampling modes(4)
tSTART
(3) Sensor buffer startup time - 1 10
(TS_BUF)
µs
tS_temp (3) ADC sampling time when reading the temperature 13 - -

Temperature sensor consumption from VDD, when

IDD(TS)(3) - 14 20 µA
selected by ADC
1. Evaluated by characterization. Not tested in production.
2. Measured at VREF+ = VDDA = 3.0 V ±10 mV. The V30 A/D conversion result is stored in the TS_CAL1 byte. Refer to
Table 16: Temperature sensor calibration values.
3. Specified by design. Not tested in production.
4. The temperature sensor is in continuous mode when the regulator is in range 1, 2 or 3. The temperature sensor is in
sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 mode.

5.3.22 VCORE monitoring characteristics

Table 112. VCORE monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

ADC sampling time when reading the VCORE

tS_VCORE 1 - - µs
voltage
1. Specified by design. Not tested in production.

5.3.23 VBAT monitoring characteristics

Table 113. VBAT monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 4 × 25.6 - kΩ

Q Ratio on VBAT measurement - 4 - -
(2)
Er Error on Q -5 - 5 %
tS_VBAT(2) ADC sampling time when reading the VBAT 5 - - µs
1. 1.58 V ≤ VBAT ≤ 3.6 V
2. Specified by design. Not tested in production.

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Table 114. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -

5.3.24 Digital-to-analog converter characteristics

Table 115. DAC characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA - 1.6 - 3.6
DAC ON

VREF+ Positive reference voltage - 1.6 - VDDA V

VREF- Negative reference voltage - - VSSA -

connected to VSSA 5 - -
DAC output
RL Resistive load connected to
buffer ON 25 - -
VDDA
RO Output impedance DAC output buffer OFF 10 13 16
Output impedance sample VDDA = 2.7 V - - 1.5 kΩ
RBON and hold mode, output
buffer ON VDDA = 2.0 V - - 2.5

Output impedance sample VDDA = 2.7 V - - 16.5

RBOFF and hold mode, output
buffer OFF VDDA = 2.0 V - - 17.5

CL DAC output buffer OFF - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF

Voltage on DAC_OUT DAC output buffer ON 0.2 - VDDA - 0.2

VDAC_OUT V
output DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3.05
Settling time (full scale: for Normal mode
a 12-bit code transition ±1 LSB - 1.90 3
DAC output
between the lowest and the buffer ON ±2 LSB - 1.85 2.85
highest input codes when CL ≤ 50 pF,
tSETTLING ±4 LSB - 1.80 2.8
DAC_OUT reaches the RL ≥ 5 kΩ
final value of ±0.5 LSB, ±8 LSB - 1.75 2.65
±1 LSB, ±2 LSB, ±4 LSB,
Normal mode DAC output µs
or ±8 LSB) - 1.7 3
buffer OFF, ±1 LSB, CL = 10 pF
Normal mode DAC output buffer
Wake-up time from off state ON - 4.2 7.5
tWAKEUP (setting the ENx bit in the CL ≤ 50 pF, RL = 5 kΩ
(2) DAC control register) until
the final value ±1 LSB Normal mode DAC output
- 2 5
buffer OFF, CL ≤ 10 pF

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Table 115. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode DAC output buffer

DC VDDA supply rejection
PSRR ON - -80 -28 dB
ratio
CL ≤ 50 pF, RL = 5 kΩ
DAC output buffer
- 0.7 1.9
DAC_OUT ON, CSH = 100 nF
Sampling time in sample pin ms
DAC output buffer
and hold mode, connected OFF, CSH = - 10.5 15
CSH = 100 nF
100 nF
(code transition between
tSAMP
the lowest input code and DAC_OUT
the highest input code pin not
when DACOUT reaches connected DAC output buffer
- 2 8 µs
the final value ±1 LSB) (internal OFF
connection
only)

(3)
Ileak Output leakage current - - - nA

Internal sample and hold

CIint - 7 9.2 11 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs

Middle code offset for VREF+ = 3.6 V - 1520 -

Voffset µV
1 trim code step VREF+ = 1.6 V - 680 -
No load, middle
- 330 510
DAC output code (0x800)
buffer ON No load, worst
- 470 680
code (0xF1C)

DAC consumption No load,

IDDA(DAC) DAC output µA
from VDDA middle/worst code - - 0.3
buffer OFF
(0x800)
330 × TON 680 × TON
Sample and hold mode, /(TON + /(TON +
-
CSH = 100 nF TOFF) TOFF)
(4) (4)

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Table 115. DAC characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

No load, middle
- 170 240
DAC output code (0x800)
buffer ON No load, worst
- 300 400
code (0x0E4)
No load,
DAC output
middle/worst code - 145 180
buffer OFF
(0x800)
DAC consumption
IDDV(DAC) µA
from VREF+ 170 × TON 400 × TON
Sample and hold mode, buffer /(TON + /(TON +
-
ON, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)

145 × TON 180 × TON

Sample and hold mode, buffer /(TON + /(TON +
-
OFF, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)

1. Specified by design. Not tested in production.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. Refer to Table 95: I/O static characteristics.
4. TON is the refresh phase duration. TOFF is the hold phase duration (see the product reference manual for more details).

Figure 40. 12-bit buffered/non-buffered DAC

Buffered/non-buffered DAC

Buffer(1)

RLOAD

12-bit DAC_OUTx
digital-to-analog
converter
CLOAD

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register. MSv47959V2

Table 116. DAC accuracy(1)

Symbol Parameter Conditions Min Typ Max Unit

Differential DAC output buffer ON - - ±2

DNL LSB
non-linearity(2) DAC output buffer OFF - - ±2
- Monotonicity 10 bits guaranteed -

Integral DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4

INL LSB
non-linearity(3) DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±4

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Table 116. DAC accuracy(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Offset error at code

Offset DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±8
0x800(3)
Offset error at code
Offset1 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±5
0x001(4) LSB
Offset error at code VREF+ = 3.6 V - - ±5
DAC output buffer ON,
OffsetCal 0x800(3)
CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.6 V - - ±5
after calibration
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5
Gain Gain error(5) %
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±0.5
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±10
TUE Total unadjusted error DAC output buffer ON, C ≤ 50 pF, R ≥ 5 kΩ, LSB
L L - - ±14
after calibration
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ,
- 70.6 -
Signal-to-noise 1 kHz, BW = 500 kHz
SNR
ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz,
- 72 -
BW = 500 kHz
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -79 - dB
Total harmonic
THD
distortion(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - -81 -

Signal-to-noise and DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.1 -
SINAD
distortion ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 71.5 -

Effective number DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.3 -
ENOB bits
of bits DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 11.6 -
1. Specified by design. Not tested in production.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at code i and the value measured at code i on a line drawn between code 0 and
last code 4095.
4. Difference between the value measured at code (0x001) and the ideal value.
5. Difference between the ideal transfer-function slope and the measured slope computed from code 0x000 and 0xFFF when
the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5 dBFS with Fsampling = 1 MHz.

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5.3.25 Voltage reference buffer characteristics

Table 117. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 000 1.8 -

VRS = 001 2.1 -
Normal mode 3.6
VRS = 010 2.4 -

Analog supply VRS = 011 2.8 -

VDDA
voltage VRS = 000 - 1.8

Degraded VRS = 001 - 2.1

1.62
mode(2) VRS = 010 - 2.4
VRS = 011 - 2.8
VRS = 000 1.496 1.5 1.504
Normal mode at
VRS = 001 1.795 1.8 1.805 V
VDDA = 3 V,
TJ = 30 °C, VRS = 010 2.042 2.048 2.054
Iload = 10 µA
VRS = 011 2.493 2.5 2.507

VREFBUF Min (VDDA - 0.15

Voltage reference VRS = 000 - 1.504
_OUT
;1.496)
(3) buffer output
Min (VDDA - 0.15
VRS = 001 - 1.805
Degraded ;1.795)
mode(2) Min (VDDA - 0.15
VRS = 010 - 2.054
;2.042)
Min (VDDA - 0.15
VRS = 011 - 2.507
;2.493)
TRIM Trim step - 0.1 0.175 0.25 %
CL Load capacitor(4) - 0.5 1.10 1.50 µF
CL equivalent serial
esr - - - 2 Ω
resistor
Iload Static load current - - - 4 mA
RPD Pull-down resistance - - - 400 Ω
VDDAmin ≤ VDDA ≤ 3.6 V,
Iline_reg Line regulation Normal mode, ±0.016 ±0.033 ±0.053 %
500 µA ≤ Iload ≤ 4 mA
Normal mode, ppm/
Iload_reg Load regulation(5) - 50 400
500 μA ≤ Iload ≤ 4 mA mA
Temperature Tcoeff_vrefint ppm/
TCoeff –40 °C < TJ < +130 °C - -
coefficient + 50 °C

Power supply DC - 65 -
PSRR dB
rejection 100 kHz - 30 -

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Table 117. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CL = 0.5 µF - 110 200

tSTART Startup time CL = 1.1 µF - 240 350 µs
CL = 1.5 µF - 320 500
Control of DC
current drive on
IINRUSH VREFBUF_ - - 8 11 mA
OUT during startup
phase (6)
Iload = 0 µA - 14 18
IDDA VREFBUF
(VREFBUF consumption from Iload = 500 µA - 16 20 µA
) VDDA
Iload = 4 mA - 42 50
1. Specified by design and not tested in production, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not accurately maintain the output voltage (VDDA - drop voltage).
3. Evaluated by characterization. Not tested in production.
4. The capacitive load must include a 100 nF capacitor in order to cut off the high-frequency noise.
5. The load regulation value only takes into account the die and package resistance. The parasitic resistance on PCB
degrades this value.
6. To correctly control the VREFBUF inrush current during startup phase and scaling change, the VDDA voltage must be in the
range of [1.8 V-3.6 V], [2.1 V-3.6 V], [2.4 V-3.6 V] and [2.8 V-3.6 V] for VRS = 000, 001, 010 and 011 respectively.

Figure 41. VREFBUF_OUT versus temperature (VRS = 000)

MSv69705V1

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Figure 42. VREFBUF_OUT versus temperature (VRS = 001)

MSv69706V1

Figure 43. VREFBUF_OUT versus temperature (VRS = 010)

MSv69707V1

Figure 44. VREFBUF_OUT versus temperature (VRS = 011)

MSv69708V1

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5.3.26 Comparator characteristics

Table 118. COMP characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA - 1.58 - 3.6
COMP ON
Comparator input voltage V
VIN - 0 - VDDA
range
VREFINT(3) Scaler input voltage - (3)

VSC Scaler offset voltage - - ±5 ±10 mV

(4)
Scaler static consumption Scaler bridge disabled - 0.20 0.25
IDDA(SCALER) µA
from VDDA Scaler bridge enabled(5) - 0.7 1
tSTART_SCALER Scaler startup time - - 130 220
High-speed mode - - 5
Comparator startup time to µs
tSTART reach propagation delay Medium mode - - 25
specification
Ultra-low-power mode - - 80
High-speed mode - 40 100 ns
Propagation delay for
tD(6) 200 mV step with 100 mV Medium mode - 0.5 1
overdrive µs
Ultra-low-power mode - 2 7
Voffset Comparator offset error Full common mode range - ±5 ±20
No hysteresis - 0 -
Low hysteresis - 15 - mV
Vhys Comparator hysteresis
Medium hysteresis - 30 -
High hysteresis - 45 -
Comparator input bias (7)
Ibias - nA
current
High-speed mode, static - 48 90
High-speed mode, with 50 kHz,
- 50 -
±100 mV overdrive square signal
Medium mode, static - 3 6
Comparator consumption
IDDA(COMP) Medium mode, with 50 kHz, ±100 mV µA
from VDDA - 3.75 -
overdrive square signal
Ultra-low-power mode, static - 0.3 1
Ultra-low-power mode, with 50 kHz,
- 0.65
±100 mV overdrive square signal
1. Specified by design and not tested in production, unless otherwise specified.
2. The input capacitance is negligible compared to the I/O capacitance.
3. Refer to Table 37: Embedded internal voltage reference.
4. No VREFINT division, includes only buffer consumption.
5. VREFINT division, includes resistor bridge and buffer consumption.

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6. Evaluated by characterization. Not tested in production.

7. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 95: I/O static characteristics.

5.3.27 Operational amplifiers characteristics

Table 119. OPAMP characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage

VDDA - 1.60 - 3.6
range for OPAMP ON
V
Common mode input
CMIR - 0 - VDDA
range
TJ = 30 °C, no load on output,
- - ±3
Normal mode
TJ= 30 °C, no load on output,
- - ±3
Low-power mode
VIOFFSET Input offset voltage mV
All voltages and temperature,
- - ±7
Normal mode
All voltages and temperature,
- - ±11.5
Low-power mode

Input offset voltage drift Normal mode - ±7 -

∆VIOFFSET μV/°C
over temperature Low-power mode - ±15 -
Offset trim step at low
TRIMOFFSETP
common input voltage - - 1.05 1.25
TRIMLPOFFSETP
(0.1 × VDDA)
mV
Offset trim step at high
TRIMOFFSETN
common input voltage - - 1.05 1.25
TRIMLPOFFSETN
(0.9 × VDDA)
Normal mode - - 500
ILOAD Drive current
Low-power mode - - 100
μA
Normal mode - - 450
ILOAD_PGA Drive current in PGA mode
Low-power mode - - 50

Resistive load (connected Normal mode 3.9 - -

RLOAD kΩ
to VSSA or VDDA) Low-power mode 20 - -
CLOAD Capacitive load - - - 50 pF

Common mode rejection Normal mode - 79 -

CMRR
ratio Low-power mode - 69 -
CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ(3), 35 75 - dB
mode
Power supply rejection DC
PSRR
ratio C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20 kΩ(3), 32 69 -
mode
DC

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Table 119. OPAMP characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Normal mode 0.4 2 3.1

GBW Gain bandwidth product MHz
Low-power mode 0.23 0.5 0.76
Normal
Standard speed 0.5 1 3.2
mode
mode
Low-power (OPAHSM = 0)
0.14 0.25 0.75
Slew rate (from 10% and mode
(3)
SR V/µs
90% of output voltage) Normal
1.4 3.2 5.6
mode High speed mode
Low-power (OPAHSM = 1)
0.38 0.82 1.5
mode
Normal mode 72 105 -
AO Open loop gain dB
Low-power mode 77 106 -
Normal mode 54 67 -
φm Phase margin °
Low-power mode 54 65 -
Normal mode - 9 -
GM Gain margin dB
Low-power mode - 17 -
Normal VDDA
ILOAD max or - -
mode - 100
VOHSAT(3) High saturation voltage RLOAD min,
Low-power Input at V VDDA
DDA - -
mode - 50
mV
Normal
ILOAD max or - - 100
mode
VOLSAT(3) Low saturation voltage RLOAD min,
Low-power Input at 0 V
- - 50
mode
CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ, - 4 10
mode
Wake-up time from follower config.
tWAKEUP µs
OFF state C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20kΩ, - 20 40
mode
follower config.
General purpose input (all (4)
- -
packages except UFBGA)
TJ ≤ 75 °C - - 7
Ibias OPAMP input bias current Dedicated nA
input TJ ≤ 85 °C - - 9
(UFBGA TJ ≤ 105 °C - - 18
only)
TJ ≤ 125 °C - - 25

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Table 119. OPAMP characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

PGA_GAIN[1:0] = 00 - 2 -
PGA_GAIN[1:0] = 01 - 4 -
PGA gain(3) Non-inverting gain value -
PGA_GAIN[1:0] = 10 - 8 -
PGA_GAIN[1:0] = 11 - 16 -
PGA gain = 2 - 80/80 -
R2/R1 internal resistance PGA gain = 4 - 120/40 - kΩ/
Rnetwork values in non-inverting
PGA gain = 8 - 140/20 - kΩ
PGA mode(5)
PGA gain = 16 - 150/10 -
Resistance variation
Delta R - -18 - 18
(R1 or R2) %
PGA gain error PGA gain error - -1 - 1
PGA gain = 2 - GBW/2 -

PGA bandwidth for PGA gain = 4 - GBW/4 -

PGA BW MHz
different non inverting gain PGA gain = 8 - GBW/8 -
PGA gain = 16 - GBW/16 -
At 1 kHz,
Normal
output loaded with - 220 -
mode
3.9 kΩ
At 1 kHz,
Low-power
output loaded with - 350 - nV
en Voltage noise density mode
20 kΩ /√Hz
Normal At 10 kHz, output
- 190 -
mode loaded with 3.9 kΩ
Low-power at 10 kHz, output
- 210 -
mode loaded with 20 kΩ
Normal
no load, quiescent - 130 190
mode
mode,
Low-power standard speed
- 40 58
OPAMP consumption from mode
IDDA(OPAMP) µA
VDDA Normal
no load, quiescent - 138 205
mode
mode,
Low-power high-speed mode
- 42 60
mode
1. Specified by design and not tested in production, unless otherwise specified.
2. OPA_RANGE must be set to 1 in OPAMP1_CSR.
3. Evaluated by characterization. Not tested in production.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 95: I/O static characteristics.
5. R2 is the internal resistance between the OPAMP output and the OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

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Figure 45. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ

Figure 46. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ

5.3.28 Temperature and backup domain supply thresholds monitoring

The temperature and backup domain supply monitoring characteristics are provided
in the technical note STM32U54xxx/STM32U58xxx/STM32U5Axxx/STM32U5Gxxx MCUs
for PCI products (TN1333) (NDA required).

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5.3.29 ADF/MDF characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 120. ADF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Input clock frequency via

fCCKI ADF_CCK[1:0] pin, in SLAVE - - 25
SPI mode
Output clock frequency in
fCCKO - - 25
MASTER SPI mode 1.71 ≤ VDD ≤ 3.6 V MHz
Output clock frequency in
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
tHCCKI ADF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tadf_proc_ck(2)
tHCCKO ADF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tadf_proc_ck
tHCCKOLF ADF_CCK[1:0] output clock
In LF_MASTER SPI mode Tadf_proc_ck - -
tLCCKOLF high and low time
Data setup time with respect In SLAVE SPI mode:
tSUCCKI 4.5 - -
to ADF_CCK[1:0] input ADF_CCK[1:0] configured in
Data hold time with respect to input, measured on rising and
tHDCCKI falling edge 1.5 - - ns
ADF_CCK[1:0] input
Data setup time with respect In MASTER SPI mode:
tSUCCKO 5.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
Data hold time with respect to output, measured on rising and
tHDCCKO falling edge 3 - -
ADF_CCK[1:0] output
Data setup time with respect
In LF_MASTER SPI mode:
tSUCCKOLF 19.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
Data hold time with respect to output, measured on rising and
tHDCCKOLF falling edge 0 - -
ADF_CCK[1:0] output
1. Evaluated by characterization. Not tested in production.
2. Tadf_proc_ck is the period of the ADF processing clock.

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Figure 47. ADF timing diagram

fCCKI, fCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCCKI, tLCCKO, tHCCKI, tHCCKO,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKOLF tHCCKOLF

ADF_CCK (I/O)

ADF_SDIx (I)
MSv69124V1

Table 121. MDF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Input clock frequency via

fCKI MDF_CKIx pin, in - - 25
SLAVE SPI mode
Input clock frequency via
fCCKI MDF_CCK[1:0] pin, in - - 25
SLAVE SPI mode
1.71 ≤ VDD ≤ 3.6 V MHz
Output clock frequency in
fCCKO - - 25
MASTER SPI mode
Output clock frequency in
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
MDF_CKIx input clock high 2×
tHCKI tLCKI In SLAVE SPI mode - -
and low time Tmdf_proc_ck(2)
tHCCKI MDF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tmdf_proc_ck
ns
tHCCKO MDF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tmdf_proc_ck
tHCCKOLF MDF_CCK[1:0] output clock
In LF_MASTER SPI mode Tmdf_proc_ck - -
tLCCKOLF high and low time

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Table 121. MDF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Data setup time with respect

tSUCKI 1.5 - -
to MDF_CKIx input In SLAVE SPI mode, measured
Data hold time with respect on rising and falling edge
tHDCKI 2.5 - -
to MDF_CKIx input
Data setup time with respect In SLAVE SPI mode:
tSUCCKI 1.5 - -
to MDF_CCK[1:0] input MDF_CCK[1:0] configured in
Data hold time with respect input, measured on rising and
tHDCCKI falling edge 2.5 - -
to MDF_CCK[1:0] input
ns
Data setup time with respect In MASTER SPI mode:
tSUCCKO 3.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
Data hold time with respect output, measured on rising and
tHDCCKO falling edge 3 - -
to MDF_CCK[1:0] output
Data setup time with respect In LF_MASTER SPI mode,
tSUCCKOLF 19.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
Data hold time with respect output, measured on rising and
tHDCCKOLF falling edge 0 - -
to MDF_CCK[1:0] output
1. Evaluated by characterization. Not tested in production.
2. Tmdf_proc_ck is the period of the MDF processing clock.

Figure 48. MDF timing diagram

tSUCKI tHDCKI tSUCKI tHDCKI
fCKI, fCCKI, FCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCKI, tLCCKI, tHCKI, tHCCKI,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKO tHCCKO

MDF_CKIx (I)
MDF_CCK (I/O)

MDF_SDIx (I)
MSv69125V1

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5.3.30 DCMI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 122. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 64 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data hold time 1.5 -
tsu(HSYNC) ns
DCMI_HSYNC and DCMI_VSYNC input setup times 2 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC and DCMI_VSYNC input hold times 1 -
th(VSYNC)
1. Evaluated by characterization. Not tested in production.

Figure 49. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

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5.3.31 PSSI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1

Table 123. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

2.7 V ≤ VDD ≤ 3.6 V - 64(2)
PSSI_PDCK PSSI clock input MHz
1.71 V ≤ VDD ≤ 3.6 V - 48.5(2)
DPIXEL PSSI clock input duty cycle - 30 70 %
2.7 V ≤ VDD ≤ 3.6 V - 14
tOV(DATA) Data output valid time
1.71 V ≤ VDD ≤ 3.6 V - 21
tOH(DATA) Data output hold time 7 -
tOV(DE) DE output valid time 1.71 V ≤ VDD ≤ 3.6 V - 13.5 ns
tOH(DE) DE output hold time 6 -
tSU(RDY) RDY input setup time 0 -
1.71 V ≤ VDD ≤ 3.6 V
tH(RDY) RDY input hold time 0 -
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.

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Figure 50. PSSI transmit timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)

tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)

DEPOL=1

ts(RDY) th(RDY)
PSSI_RDY

RDYPOL=0
(input)

RDYPOL=1

MSv63437V1

Table 124. PSSI receive characteristics(1)

Symbol Parameter Conditions Min Max Unit

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 64 MHz
DPIXEL PSSI clock input duty cycle - 30 70 %
tSU(DATA) Data input setup time 2 -
tH(DATA) Data input hold time 2.5 -
tSU(DE) DE input setup time 1 -
1.71 V ≤ VDD ≤ 3.6 V ns
tH(DE) DE input hold time 2.5 -
tOV(RDY) RDY output valid time - 13
tOH(RDY) RDY output hold time 6 -
1. Evaluated by characterization. Not tested in production.

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Figure 51. PSSI receive timing diagram

tc(PDCK)

tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK

CKPOL=0
(input)

CKPOL=1

ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)

DEPOL=1

tv(RDY) tho(RDY)
PSSI_RDY

RDYPOL=0
(output)

RDYPOL=1

MSv63436V1

5.3.32 Timer characteristics

The parameters given in the following tables are specified by design, not tested in
production.
Refer to Section 5.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 125. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 160 MHz 6.25 - ns

Timer external clock frequency on - 0 fTIMxCLK/2

fEXT MHz
CH1 to CH4 fTIMxCLK = 160 MHz 0 80
TIMx (except TIM2/3/4/5) - 16
ResTIM Timer resolution bit
TIM2/3/4/5 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 160 MHz 0.007 409.6 µs

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 160 MHz - 26.843 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

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Table 126. IWDG min/max timeout period at 32 kHz (LSI)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full
RC period of uncertainty.

Table 127. WWDG min/max timeout value at 160 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.025 1.638
2 1 0.051 3.276
4 2 0.102 6.553
8 3 0.204 13.107
ms
16 4 0.409 26.214
32 5 0.819 52.428
64 6 1.638 104.858
128 7 3.276 209.715

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5.3.33 OCTOSPI characteristics

Unless otherwise specified, the parameters given in Table 128 toTable 130 are derived from
tests performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Delay block enabled for DTR (with DQS)/HyperBus
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1 unless otherwise specified
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.

Table 128. OCTOSPI characteristics in SDR mode(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V ≤ VDD ≤ 1.9 V

Voltage range 1 - - 93
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range1 - - 100 MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4 - - 25
CL = 15 pF
tw(CLKH) OCTOSPI clock high t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
and low time
tw(CLKL) (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock high -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1) + 0.5
Voltage range 1 2.5 - -
ts(IN) Data input setup time ns
Voltage range 4 6 - -
Voltage range 1 0.5 - -
th(IN) Data input hold time
Voltage range 4 1 - -
Voltage range 1 - 0.5 1
tv(OUT) Data output valid time
Voltage range 4 - 1.5 2.5
Voltage range 1 0.5 - -
th(OUT) Data output hold time
Voltage range 4 -0.25 - -
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.

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Table 129. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V ≤ VDD ≤ 1.9 V Voltage

- - 93(4)
range 1, CL = 15 pF
OCTOSPI clock 2.7 V ≤ VDD ≤ 3.6 V
f(CLK) - - 100(4) MHz
frequency Voltage range1, CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
- - 25(4)
Voltage range 4, CL = 15 pF
tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
high and low time
tw(CLKL) (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1) + 0.5

tsr(IN) Data input setup Voltage range 1 3.25 - -

tsf(IN) time Voltage range 4 3.75 - -

thr(IN) Data input hold Voltage range 1 1 - -

ns
thf(IN) time Voltage range 4 1.5 - -

Data output valid Voltage range 1 - 6 9.25

tvr(OUT) time, DHQC = 0 Voltage range 4 - 13.25 19.75
tvf(OUT)
Data output valid Voltage range 1 t(CLK)/4
- t(CLK)/4 + 1.5
time, DHQC = 1 All prescaler values (except 0) + 0.75

Data output hold Voltage range 1 4 - -

thr(OUT) time DHQC = 0 Voltage range 4 8 - -
thf(OUT)
Data output hold Voltage range 1
t(CLK)/4 - 0.5 - -
time DHQC = 1 All prescaler values (except 0)
1. Evaluated by characterization. Not tested in production.
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
4. Activating DHQC is mandatory to reach this frequency.

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Table 130. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

1.71 V ≤ VDD ≤ 1.9 V

Voltage range 1 - - 93(3)(4)
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range1 - - 100(3)(4) MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4 - - 25(4)
CL = 15 pF
tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
high and low time
tw(CLKL) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(even division)
(n/2) × t(CLK) (n/2) × t(CLK)
tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time ns
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
tw(CLKL) (odd division) -
/(n+1) - 0.5 /(n+1) + 0.5
tv(CLK) Clock valid time - - - t(CLK) + 2
th(CLK) Clock hold time - t(CLK)/2 - 0.5 - -
CLK, NCLK
VODr(CLK)
(5) crossing level on VDD = 1.8 V 1005 - 1065
CLK rising edge
mV
CLK, NCLK
VODf(CLK)
(5) crossing level on VDD = 1.8 V 950 - 1050
CLK falling edge
Chip select high
tw(CS) - 3 × t(CLK) - -
time
Data input valid
tv(DQ) - 0 - -
time
Data strobe input
tv(DS) - 0 - -
valid time
Data strobe input
th(DS) - 0 - -
hold time ns
Data strobe output
tv(RWDS) - - - 3 × t(CLK)
valid time

tsr(DQ) Data input setup Voltage range 1 -0.25 - t(CLK)/2 - 1.25(6)

tsf(DQ) time Voltage range 4 0 - t(CLK)/2 - 1.75(6)

thr(DQ) Data input hold Voltage range 1 1.25 - -

thf(DQ) time Voltage range 4 1.75 - -

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Table 130. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Data output valid Voltage range 1 - 6 9.5

time DHQC = 0 Voltage range 4 - 13 19.5
tvr(OUT)
tvf(OUT) Voltage range 1
Data output valid
All prescaler values - t(CLK)/4 + 0.5 t(CLK)/4 + 1.25
time DHQC = 1
(except 0)
ns
thr(OUT) Data output hold Voltage range 1 4 - -
thf(OUT) time DHQC = 0 Voltage range 4 7.75 - -
Voltage range 1
Data output hold
thr(OUT) All prescaler values t(CLK)/4 - 0.5 - -
time DHQC = 1
(except 0)
1. Evaluated by characterization. Not tested in production.
2. Delay block activated.
3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns.
4. Activating DHQC is mandatory to reach this frequency.
5. Crossing results are in line with specification, using pairs PB10/PE9 or PE10/PB12. It exceeds slightly the specification on
other CLK/NCLK pairs.
6. Data input maximum setup time does not take into account the data level switching duration.

Figure 52. OCTOSPI timing diagram - SDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V3

Figure 53. OCTOSPI timing diagram - DTR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5

MSv36879V4

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Figure 54. OCTOSPI HyperBus clock

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)

NCLK

VOD(CLK)
CLK
MSv47732V3

Figure 55. OCTOSPI HyperBus read

tw(CS)

NCS

tv(CLK) t ACC= Initial access th(CLK)

CLK, NCLK

tv(RWDS) tv(DS) th(DS)

RWDS

tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)

47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B

Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3

Figure 56. OCTOSPI HyperBus read with double latency

NCS

tRWR=Read/write recovery Additional latency tACC = Access

CLK, NCLK

tCKDS
RWDS High = 2x latency count
Low = 1x latency count
RWDS and data
are edge aligned
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
A B A B

Command address Memory drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS. MSv49351V3

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Figure 57. OCTOSPI HyperBus write

tw(CS)

NCS

Read write recovery Access latency

tv(CLK) th(CLK)

CLK, NCLK

tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS

Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)

Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3

5.3.34 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 131 and Table 132 are derived
from tests performed under the ambient temperature, fAHB frequency and VDD supply
voltage conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF, unless otherwise specified
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.

Table 131. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 100(3) MHz

tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

tISU Input setup time HS - 3.5 - -

tIH Input hold time HS - 1.5 - - ns
tIDW(5) Input valid window (variable window) - 4.5 - -

CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

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Table 131. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tOV Output valid time HS - - 5.5 7

ns
tOH Output hold time HS - 3 - -

CMD, D inputs (referenced to CK) in SD default mode

tISU Input setup time SD - 3.5 - -

ns
tIH Input hold time SD - 1.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOV Output valid default time SD - - 0.5 2

ns
tOH Output hold default time SD - 0 - -
1. Evaluated by characterization. Not tested in production.
2. For SDMMC2 in SD/e.MMC DDR mode, the clock OSPEEDRy[1:0] is set to 01 while data OSPEEDRy[1:0] remains at 10.
3. With capacitive load CL = 20 pF.
4. For SD 1.8 V support, an external voltage converter is needed.
5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 132. e•MMC characteristics (VDD = 1.71 V to 1.9 V)(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

All modes
fPP Clock frequency in data transfer mode - - 84 MHz
except DDR
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in e•MMC mode

tISU Input setup time HS - 2.5 - -

tIH Input hold time HS - 2 - - ns
tIDW(3) Input valid window (variable window) - 4 - -

CMD, D outputs (referenced to CK) in e•MMC mode

tOV Output valid time HS - - 5 5.5

ns
tOH Output hold time HS - 3 - -
1. Evaluated by characterization. Not tested in production.
2. With capacitive load CL = 20 pF.
3. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.

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Figure 58. SD high-speed mode

tC(CK)
tW(CKH) tW(CKL)

CK
tOH
tOV

D, CMD output
tIH
tISU

D, CMD input
MSv69709V1

Figure 59. SD default mode

CK
tOV tOH

D, CMD output MSv69710V1

Figure 60. SDMMC DDR mode

D input Valid data Valid data

tISU tIH tISU tIH

tW(CKH)

CK

tW(CKL)
tOV tOV
tOH tOH

D output Valid data Valid data

MSv69158V1

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5.3.35 Delay block characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
conditions summarized in Table 33.

Table 133. Delay block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

tinit Initial delay - 350 750 1550

ps
t∆ Unit delay - 34 41 51
1. Evaluated by characterization. Not tested in production.

5.3.36 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bitrate up to 100 Kbit/s
• Fast-mode (Fm): with a bitrate up to 400 Kbit/s
• Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s
The I2C timings requirements are specified by design, not tested in production, when the
I2C peripheral is properly configured (refer to the product reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output-current maximum requirement. Refer to Section 5.3.15: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics.

Table 134. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 115(3) ns
1. Specified by design. Not tested in production.
2. Spikes with widths below tAF min are filtered.
3. Spikes with width above tAF max are not filtered.

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5.3.37 USART (SPI mode) characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).

Table 135. USART (SPI mode) characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

SPI master mode, 1.71 V ≤ VDDIOX ≤ 3.6 V - - 20

SPI slave receiver,
- - 53
1.71 V ≤ VDDIOX ≤ 3.6 V
USART clock
fCK SPI slave transmitter, MHz
frequency - - 30
1.71 V ≤ VDDIOX ≤ 3.6 V
SPI slave transmitter,
- - 27
2.7 V ≤ VDDIOX ≤ 3.6 V
NSS setup
tsu(NSS) SPI slave mode Tker(2) + 2 - -
time
th(NSS) NSS hold time SPI slave mode 2 - -
tw(CKH) CK high and
SPI master mode 1/fCK / 2 - 1 1/fCK / 2 1/fCK / 2 + 1
tw(CKL) low time

Data input SPI master mode 15 - -

tsu(RX)
setup time SPI slave mode 2.5 - -
th(RX) SPI master mode 4 - - ns
Data input
th(RX) hold time SPI slave mode 1 - -
SPI slave mode, 2.7 V ≤ VDD ≤ 3.6 V - 13 16.5
tv(TX) Data output
SPI slave mode, 1.71 V ≤ VDD ≤ 3.6 V - 13 18.5
valid time
tv(TX) SPI master mode - 2.5 6.5
th(TX) Data output SPI slave mode 8.5 - -
th(TX) hold time SPI master mode 0.5 - -
1. Evaluated by characterization. Not tested in production.
2. Tker is the usart_ker_ck_pres clock period.

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Figure 61. USART timing diagram in SPI master mode

1/fCK
tw(CKH)
CPHA=0
CK output

CPOL=0

CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output

CPOL=0

CPHA=1
CPOL=1
tsu(RX) th(RX)

RX input MSB IN BIT6 IN LSB IN

TX output MSB OUT BIT1 OUT LSB OUT

tv(TX) th(TX) MSv65386V6

Figure 62. USART timing diagram in SPI slave mode

NSS input

1/fCK th(NSS)

tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input

CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

tsu(RX) th(RX)

RX input First bit IN Next bits IN Last bit IN

MSv65387V6

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5.3.38 SPI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 33.
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 136. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V,

- - 80
voltage range 1
Master mode, 1.71 V ≤ VDDIOX < 2.7 V 75
- -
voltage range 1 or 50(2)
Master transmitter mode,
- - 80
2.7 V ≤ VDDIOX ≤ 3.6 V, voltage range 1
Master transmitter mode, 75
- -
1.71 V ≤ VDDIOX ≤ 2.7 V, voltage range 1 or 50(2)
fSCK Slave receiver mode,
SPI clock frequency - - 100 MHz
1/tc(SCK) 1.71 V ≤ VDDIOX ≤ 3.6 V, voltage range 1
Slave mode transmitter/full duplex(3), 37
- -
1.71 V ≤ VDDIOX < 2.7 V, voltage range 1 or 25(4)
Slave mode transmitter/full duplex(3),
- - 35.5
2.7 V ≤ VDDIOX ≤ 3.6 V, voltage range 1
Master or slave mode,
- - 12.5
1.71 V ≤ VDDIOX ≤ 3.6 V, voltage range 4
Master or slave mode,
- - 15
1.08 V ≤ VDDIO2 ≤ 1.32 V(5)

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Table 136. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tsu(NSS) NSS setup time Slave mode 4 - -

th(NSS) NSS hold time Slave mode 3 - -
tw(SCKH) SCK high and low
Master mode tSCK(6)/2 - 1 tSCK/2 tSCK/2 + 1
tw(SCKL) time
tsu(MI) Master mode 4.5 - -
Data input setup time
tsu(SI) Slave mode 2.5 - -
th(MI) Master mode 3 - -
Data input hold time
th(SI) Slave mode 1 - -
Data output access
ta(SO) Slave mode 9 12 34
time
Data output disable
tdis(SO) Slave mode 9 10 16
time
ns
Slave mode, 2.7 V ≤ VDDIOX ≤ 3.6 V,
- 11.5 14
voltage range 1
Slave mode, 1.71 V ≤ VDDIOX < 2.7 V, 13.5
- 11.5
tv(SO) voltage range 1 or 20(4)
Data output valid
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V, 19.5
time - 17
voltage range 4 or 27(4)
Slave mode, 1.08 V ≤ VDDIO2 ≤ 1.32 V(5) - 23 25
3 or 9.5(7)
tv(MO) Master mode - 2.5
or 12.5(8)
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V 7 - -
th(SO)
Data output hold time Slave mode, 1.08 V ≤ VDDIO2 ≤ 1.32 V(5) 15 - -
th(MO) Master mode 0.5 - -
1. Evaluated by characterization. Not tested in production.
2. When using PA5, PA9, PC10, PB3, PB13.
3. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) that has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
4. When using PA11, PB4, PB14.
5. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.
6. tSCK = tspi_ker_ck × baudrate prescaler.
7. When using PA12.
8. When using PB15.

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Figure 63. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

Figure 64. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

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Figure 65. SPI timing diagram - master mode

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

5.3.39 SAI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized inTable 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK, SD, FS).

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Table 137. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

SAI main clock

fMCK - - 50
output
Master transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 26
Master transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18
MHz
SAI clock Master receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 21.5
fSCK
frequency(2) Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 27.5
Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18
Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 50
Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V - 16
tv(FS) FS valid time
Master mode 1.71 V ≤ VDDIOX ≤ 3.6 V - 23
th(FS) FS hold time Master mode 7 -
tsu(FS) FS setup time Slave mode 2.5 -
th(FS) FS hold time Slave mode 1 -
tsu(SD_A_MR) Data input setup Master receiver 4 -
t time Slave receiver 3 -
su(SD_B_SR)

th(SD_A_MR) Data input hold Master receiver 2 -

t time Slave receiver 1 -
h(SD_B_SR)
ns
Slave transmitter (after enable edge),
- 18
Data output valid 2.7 V ≤ VDDIOX ≤ 3.6 V
tv(SD_B_ST)
time Slave transmitter (after enable edge),
- 27.5
1.71 V ≤ VDDIOX ≤ 3.6 V
Data output hold
th(SD_B_ST) Slave transmitter (after enable edge) 8 -
time
Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 19
Data output valid
tv(SD_A_MT) Master transmitter (after enable edge),
time - 27.5
1.71 V ≤ VDD ≤ 3.6 V
Data output hold
th(SD_A_MT) Master transmitter (after enable edge) 8 -
time
1. Evaluated by characterization. Not tested in production.
2. APB clock frequency that must be at least twice SAI clock frequency.

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Figure 66. SAI master timing diagram

1/fSCK

SAI_SCK_X
(CKSTR = 0)

SAI_SCK_X
(CKSTR = 1)
th(FS)

SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
(transmit) Slot n Slot n+2

tsu(SD_MR) th(SD_MR)

SAI_SD_X
(receive) Slot n

MS32771V2

Figure 67. SAI slave timing diagram

1/fSCK

SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)

tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X
Slot n
(receive)
MS32772V2

5.3.40 USB_FS characteristics

Table 138. USB_FS characteristics

Symbol Parameter Conditions Min Typ Max Unit
(1)
VDDUSB USB transceiver operating supply voltage - 3.0 - 3.6 V
tSTARTUP(2) USB transceiver startup time - - - 1 μs

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Table 138. USB_FS characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

RPUI Embedded USB_DP pullup value during idle - 900 - 1575

RPUR Embedded USB_DP pullup value during reception - 1425 - 3090 Ω
(3)
ZDRV Output driver impedance High and low driver 28 36 44
1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range.
2. Guaranteed by design.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is
already included in the embedded driver.

5.3.41 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests
performed under the ambient temperature, fHCLKx frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.

Table 139. JTAG characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V - - 27.5

FTCK TCK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 20.5
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 3 - -
tisu(TDI) TDI input setup time - 3 - -
tih(TDI) TDI input hold time - 1 - - ns
2.7 V ≤ VDD ≤ 3.6 V - 14 18
tov(TDO) TDO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 14 24
toh(TDO) TDO output hold time - 10 - -
1. Evaluated by characterization. Not tested in production.

Table 140. SWD characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V ≤ VDD ≤ 3.6 V - - 66.5

FSWCLK SWCLK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 43

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Table 140. SWD characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tisu(SWDIO) SWDIO input setup time - 1 - -

tih(SWDIO) SWDIO input hold time - 2.5 - -
2.7 V ≤ VDD ≤ 3.6 V - 10.5 15 ns
tov(SWDIO) SWDIO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 10.5 23
toh(SWDIO) SWDIO output hold time - 7.5 - -
1. Evaluated by characterization. Not tested in production.

Figure 68. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

Figure 69. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

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6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

6.1 LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 70. LQFP48 - Outline(15)

BOTTOM VIEW

4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1

H
R2

B
B-
D 1/4

N
O
(6)

TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

5B_LQFP48_ME_V1

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Table 141. LQFP48 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 71. LQFP48 - Footprint example

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

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Device marking for LQFP48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 72. LQFP48 marking example (package top view)

Product
identification(1)

Y WW
Date code

Pin 1 identifier Revision code

MSv71546V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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6.2 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 73. UFQFPN48 – Outline

D1 EXPOSED PAD

E2 E1
e

PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE

C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW

A1 A
SEATING PLANE

ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA

TOP VIEW

A0B9_UFQFPN48_ME_V4

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.

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Table 142. UFQFPN48 – Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 74. UFQFPN48 – Footprint example

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3

1. Dimensions are expressed in millimeters.

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Device marking for UFQFPN48

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 75. UFQFPN48 marking example (package top view)

Product
identification(1)

Y WW
Date code

Pin 1 identifier Revision code

MSv71550V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

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6.3 WLCSP56 package information (B0H4)

This WLCSP is a 56-ball, 3.38 x 3.38 mm, 0.40 mm pitch, wafer level chip scale package.

Figure 76. WLCSP56 - Outline

F
e1
A1 BALL LOCATION bbb Z
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A1

G A

C DETAIL A
D
e2
E

F
e
G

e A
A2
BOTTOM VIEW

SIDE VIEW

A3

FRONT VIEW
BUMP

eee Z

E Z
b (56x)
A1 ORIENTATION
ccc Z X Y
REFERENCE
ddd Z
SEATING PLANE

DETAIL A
aaa ROTATED 90
Y (not in scale)
(4X)
D

TOP VIEW

B0H4_WLCSP56_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.

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Table 143. WLCSP56 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.59 - - 0.0243

A1 - 0.18 - - 0.0071 -
A2 - 0.38 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0010 -
(4)
b 0.22 0.25 0.28 0.0087 0.0098 0.0110
D 3.36 3.38 3.40 0.1323 0.1330 0.1338
E 3.36 3.38 3.40 0.1323 0.1330 0.1338
e - 0.40 - - 0.0157 -
e1 - 2.60 - - 0.1024 -
e2 - 2.42 - - 0.0952 -
F(5) - 0.390 - - 0.0153 -
G(5) - 0.478 - - 0.0188 -
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
ccc(6) - - 0.10 - - 0.0039
(7)
ddd - - 0,05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place.
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.

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Figure 77. WLCSP56 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 144. WLCSP56 - Example of PCB design rules

Dimension Values

Pitch 0.400 mm
Dpad 0,250 mm
Dsm 0.325 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.325 mm
Stencil thickness 0.100 mm

Device marking for WLCSP56

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

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Figure 78. WLCSP56 marking example (package top view)

Ball A1 identifier

Product
identification(1)

Y WW Revision code

Date code

MSv71543V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.4 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 79. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 145. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 80. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 81. LQFP64 marking example (package top view)

Product
identification(1)

Y WW
Date code

Revision code
Pin 1 identifier

MSv71547V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.5 UFBGA64 package information (A019)

This UFBGA is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package.
Note: See list of notes in the notes section.

Figure 82. UFBGA64 – Outline(13)

E1

e SE

H
G
SD F
E e
D1
D
C
B
A

1 2 3 4 5 6 7 8
Øb (N balls)
A1 ball pad corner Ø eee M C A B
Ø fff M C
Mold resin
ccc C

Substrate

Detail A A
SIDE VIEW Seating plane

(8)

A1 A2
B C
E A Detail A
A1 ball pad corner ddd C
(9) Solder balls

(DATUM A)

(DATUM B)

aaa C
TOP VIEW (4X)
A019_UFBGA64_ME_V2

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Table 146. UFBGA64 – Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.23 0.28 0.33 0.0090 0.0110 0.0130
(6)
D 5.00 BSC 0.1969 BSC
D1 3.50 BSC 0.1378 BSC
E 5.00 BSC 0.1969 BSC
E1 3.50 BSC 0.1378 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(11) 64
SD(12) 0.25 BSC 0.0098 BSC
SE(12) 0.25 BSC 0.0098 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ultra profile fine pitch ball grid array: 0.5 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 83. UFBGA64 – Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 147. UFBGA64 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.5 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

Device marking for UFBGA64

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

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Figure 84. UFBGA64 marking example (package top view)

Product
identification(1)

Y WW Revision code

Date code

Ball A1 identifier

MSv71548V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.6 WLCSP72 package information (B0HK)

This WLCSP is a 72-ball, 3.38 x 3.38 mm, 0.35 mm pitch, wafer level chip scale package.

Figure 85. WLCSP72 - Outline

F A2 BALL
e1 LOCATION
bbb Z
15 13 11 9 7 5 3 1 A1
16 14 12 10 8 6 4 2

G
A

B
C
DETAIL A
D
E e2
F

e G
H

e A
A2
BOTTOM VIEW

SIDE VIEW

A3

FRONT VIEW

BUMP

eee Z

E b (72x) Z

ccc Z XY SEATING
A2 ORIENTATION ddd Z PLANE
REFERENCE
DETAIL A
ROTATED 90°

Y bbb
D

TOP VIEW

B0HK_WLCSP72_ME_V1

1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.

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Table 148. WLCSP72 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.58 - - 0.0228

A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0010 -
(4)
b 0.20 0.23 0.25 0.0079 0.0090 0.0098
D 3.36 3.38 3.40 0.1323 0.1330 0.1338
E 3.36 3.38 3.40 0.1323 0.1330 0.1338
e - 0.35 - - 0.0138 -
e1 - 2.63 - - 0.1035 -
e2 - 2.42 - - 0.0952 -
F(5) - 0.378 - - 0.0149 -
G(5) - 0.478 - - 0.0188 -
N 72
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
(6)
ccc - - 0.10 - - 0.0039
(7)
ddd - - 0,05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place.
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.

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Figure 86. WLCSP72 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 149. WLCSP72 - Example of PCB design rules

Dimension Values

Pitch 0.35 mm
Dpad 0,200 mm
Dsm 0.275 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.275 mm
Stencil thickness 0.100 mm

Device marking for WLCSP72

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

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Figure 87. WLCSP72 marking example (package top view)

Ball A1 identifier

Product
identification(1)

Y WW Revision code

Date code

MSv71544V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.7 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 88. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

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Table 150. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 89. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier
location. The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.

Figure 90. LQFP100 marking example (package top view)

Product
identification(1)

Y WW Revision code

Date code

Pin 1 identifier

MSv71545V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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6.8 UFBGA100 package information (A0C2)

This UFBGA is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 91. UFBGA100 - Outline(13)

E1

e SE

M
L
K
SD J
H
G
D1
F
E
D
C
e
B
A

A1 ball pad 1 2 3 4 5 6 7 8 9 10 11 12
corner Øb (N balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C

DETAIL A

Mold resin
A ccc C
SIDE VIEW
C
Substrate

B E
A
A1 ball pad
corner
(9)
Seating plane
(8)

(DATUM A) A1 A2
C
Detail A
D ddd C
Solder balls

(DATUM B)

aaa C
TOP VIEW (4X)
A0C2_UFBGA_ME_V8

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Table 151. UFBGA100 - Mechanical data

millimeters(1) inches(12)
Symbol
Min. Typ. Max. Min. Typ. Max.

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.23 0.28 0.33 0.0090 0.0110 0.0130
(6)
D 7.00 BSC 0.2756 BSC
D1 5.50 BSC 0.2165 BSC
E 7.00 BSC 0.2756 BSC
E1 5.50 BSC 0.2165 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(11) 100
SD(12) 0.25 BSC 0.0098 BSC
SE(12) 0.25 BSC 0.0098 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ulta profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 92. UFBGA100 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 152. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm

Device marking for UFBGA100

The following figure gives an example of topside marking versus ball A1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

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Figure 93. UFBGA100 marking example (package top view)

Product
identification(1)

Y WW Revision code

Date code

Ball A1 identifier

MSv71549V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

6.9 Package thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
where:
• TA max is the maximum ambient temperature in °C.
• ΘJA is the package junction-to-ambient thermal resistance in °C/W.
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
PI/O max = ∑(VOL × IOL) + ∑((VDDIOx - VOH) × IOH)
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.

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Table 153. Package thermal characteristics

Symbol Parameter Package Value Unit

LQFP48 (7 x 7 mm) 48.5

UFQFPN48 (7 x 7 mm) 27.7
WLCSP56 51.2
LQFP64 (10 x 10 mm) 41.8
ΘJA Thermal resistance junction-ambient
UFBGA64 (5 x 5 mm) 49.6
WLCSP72 49.8
LQFP100 (14 × 14 mm) 35.9
UFBGA100 (7 x 7 mm) 43.8
°C/W
LQFP48 (7 x 7 mm) 25.8
UFQFPN48 (7 x 7 mm) 12.1
WLCSP56 27.2
LQFP64 (10 x 10 mm) 24.1
ΘJB Thermal resistance junction-board
UFBGA64 (5 x 5 mm) 33
WLCSP72 25.9
LQFP100 (14 × 14 mm) 21.9
UFBGA100 (7 x 7 mm) 29.8
LQFP48 (7 x 7 mm) 12.3
UFQFPN48 (7 x 7 mm) 9
WLCSP56 2.3
LQFP64 (10 x 10 mm) 10.3
ΘJC Thermal resistance junction-top case °C/W
UFBGA64 (5 x 5 mm) 12.5
WLCSP72 22
LQFP100 (14 × 14 mm) 8.5
UFBGA100 (7 x 7 mm) 11.2

6.9.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air) available on www.jedec.org.
• For information on thermal management, refer to application note “Guidelines for
thermal management on STM32 applications” (AN5036) available on www.st.com.

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7 Ordering information

Example: STM32 U 545 V E T 6 Q TR

Device family

STM32 = Arm based 32-bit microcontroller

Product type

U = ultra-low-power

Device subfamily

545 = STM32U545xx with USB and hardware accelerator encryption

Pin count

C = 48 pins
N = 56 pins
R = 64 pins
J = 72 pins
V = 100 pins

Flash memory size

E = 512 Kbytes

Package

T = LQFP
I = UFBGA
U = UFQFPN
Y = WLCSP

Temperature range

6 = Industrial temperature range, –40 to 85 °C (105 °C junction)

3 = Industrial temperature range, –40 to 125 °C (130 °C junction)

Dedicated pinout

Q = Dedicated pinout including SMPS step-down converter

Packing

TR = tape and reel

xxx = programmed parts

For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.

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Important security notice STM32U545xx

8 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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9 Revision history

Table 154. Document revision history

Date Revision Changes

17-Feb-2023 1 Initial release.

Updated:
– Replaced PSA level 3 and SESIP level 3 certified by SESIP3 and PSA
Level 3 Certified Assurance Target in Security and cryptography
– Table 2: STM32U545xx features and peripheral counts
– Figure 1: STM32U545xx block diagram
– Section 3.9.1: Power supply schemes
– Figure 2: STM32U545xxxxQ power supply overview (with SMPS)
– Figure 3: STM32U545xx power supply overview (without SMPS)
– Section 3.9.3: Low-power modes
– Section 3.9.5: VBAT operation
– Section 3.10: Peripheral interconnect matrix
– Table 15: ADC features
– Section 5.1.6: Power supply scheme
– Figure 23: STM32U545xx power supply scheme (without SMPS)
– Figure 24: STM32U545xQ power supply scheme (with SMPS)
– Table 45: Current consumption in Sleep mode on SMPS, flash
memory in power down
– Table 52: Current consumption during wake-up from Stop 1 mode on
LDO
05-Jul-2023 2 – Table 54: Current consumption during wake-up from Stop 1 mode on
SMPS
– Table 57: Current consumption during wake-up from Stop 2 mode on
LDO
– Table 60: Current consumption during wake-up from Stop 2 mode on
SMPS
– Table 63: Current consumption during wake-up from Stop 3 mode on
LDO
– Table 66: Current consumption during wake-up from Stop 3 mode on
SMPS
– Table 68: Current consumption during wake-up from Standby mode
– Table 69: Current consumption in Shutdown mode
– Table 78: Low-speed external user clock characteristics
– Increased HSE consumption during startup from 8 µA to 8 mA in
Table 79: HSE oscillator characteristics
– Table 91: ESD absolute maximum ratings
– Table 96: Output voltage characteristics for FT_t I/Os in VBAT mode,
and for FT_o I/Os
– Table 100: Output AC characteristics for FT_t I/Os in VBAT mode, and
for FT_o I/Os
– Table 106: 14-bit ADC1 accuracy

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Table 154. Document revision history (continued)

Date Revision Changes

– tCAL and tOFF_CAL values in Table 104: 14-bit ADC1 characteristics

– tOFF_CAL values in Table 107: 12-bit ADC4 characteristics
– tHDCCKI and tHDCCKO values in Table 119: ADF characteristics
– tHDCKI, tHDCCKI,and tHDCCKO values in Table 120: MDF characteristics
– tsu(DATA) and th(DATA) values in Table 121: DCMI characteristics
– PSSI_PDCK and tOV(DE) values in Table 122: PSSI transmit
characteristics
– tH(DATA), tSU(DE), tH(DE), and tOV(RDY) values in Table 123: PSSI
receive characteristics
– Table 131: e•MMC characteristics (VDD = 1.71 V to 1.9 V)
– Table 134: USART characteristics
– Figure 61: USART timing diagram in master mode
– Figure 62: USART timing diagram in slave mode
– Table 135: SPI characteristics
– Figure 63: SPI timing diagram - slave mode and CPHA = 0
– Figure 64: SPI timing diagram - slave mode and CPHA = 1
– Figure 65: SPI timing diagram - master mode
– Figure 66: SAI master timing diagram
– Figure 67: SAI slave timing diagram
2
05-Jul-2023 – Table 138: JTAG characteristics
(cont’d)
– Table 134: USART characteristics
– Section 5.3.28: Temperature and backup domain supply thresholds
monitoring
Added:
– Section 5.3.4: SMPS characteristics
– Table 92: Electrical sensitivities
– Section 5.3.33: OCTOSPI characteristics
– Section 5.3.34: SD/SDIO/e•MMC card host interfaces (SDMMC)
characteristics
– Device marking for LQFP48
– Device marking for UFQFPN48
– Device marking for WLCSP56
– Device marking for LQFP64
– Device marking for UFBGA64
– Device marking for WLCSP72
– Device marking for LQFP100
– Device marking for UFBGA100
– Section 6.9: Package thermal characteristics
– Section 6.9.1: Reference documents

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Table 154. Document revision history (continued)

Date Revision Changes

Updated:
– Up to 19 communication peripherals
– Replaced “o” by “-” for Backup domain voltage and temperature
monitoring in Table 10: Functionalities depending on the working
mode
– Moved USB_DM(boot) and USB_DP(boot) from Alternate functions to
Additional functions in Table 27: STM32U545xx pin/ball definitions
– Typical values in Table 53: Current consumption during wake-up from
Stop 1 mode on LDO
– Typical values in Table 55: Current consumption during wake-up from
Stop 1 mode on SMPS
– Typical values in Table 58: Current consumption during wake-up from
Stop 2 mode on LDO
– Typical values in Table 61: Current consumption during wake-up from
Stop 2 mode on SMPS
– Typical values in Table 64: Current consumption during wake-up from
Stop 3 mode on LDO
– Typical values in Table 67: Current consumption during wake-up from
28-Nov-2023 3 Stop 3 mode on SMPS
– Typical values in Table 55: Current consumption during wake-up from
Stop 1 mode on SMPS
– Typical values in Table 69: Current consumption during wake-up from
Standby mode
– Typical values in Table 71: Current consumption during wake-up from
Shutdown mode
– Table 78: High-speed external user clock characteristics
– Table 92: ESD absolute maximum ratings
– Note added in Table 106: Maximum RAIN for 14-bit ADC1 and
Table 109: Maximum RAIN for 12-bit ADC4
– Figure 60: USART timing diagram in SPI master mode
– Figure 61: USART timing diagram in SPI slave mode
Added:
– SPI mode in Table 22: USART, UART, and LPUART features,
Section 3.42.1: Universal synchronous/asynchronous receiver
transmitter (USART/UART), and Section 5.3.37: USART (SPI mode)
characteristics
Updated:
– VDDUSB corrected to VDD in Figure 15: WLCSP56_SMPS ballout
21-Dec-2023 4
– Pin number A1 moved from VDDUSB to VDD line in Table 26:
STM32U535xx pin/ball definitions

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Table 154. Document revision history (continued)

Date Revision Changes

Updated:
– Section 3.9.1: Power supply schemes
– Notes in Section 5.2: Absolute maximum ratings
– Table 27: STM32U545xx pin/ball definitions
– Table 127: WWDG min/max timeout value at 160 MHz (PCLK)
– Table 52: Current consumption in Stop 1 mode on LDO
– Table 54: Current consumption in Stop 1 mode on SMPS
5-May-2025 5
– Table 56: Current consumption in Stop 2 mode on LDO
– Table 59: Current consumption in Stop 2 mode on SMPS
– Table 62: Current consumption in Stop 3 mode on LDO
– Table 65: Current consumption in Stop 3 mode on SMPS
Added:
– Sustainable technology logo in Features
– Figure 33: HSI16 frequency versus temperature and VDD

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© 2025 STMicroelectronics – All rights reserved

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