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35 views129 pagesColor Computer 3 - Service Manual
The document provides a comprehensive technical manual for the Tandy Color Computer 3, detailing its system description, specifications, assembly instructions, and troubleshooting guidelines. It includes information about the hardware components, memory map, input/output control registers, and various operational theories. Additionally, the manual covers the 512K expansion RAM card and includes diagrams, parts lists, and troubleshooting tips for both NTSC and PAL versions.
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0% found this document useful (0 votes)
35 views129 pagesColor Computer 3 - Service Manual
The document provides a comprehensive technical manual for the Tandy Color Computer 3, detailing its system description, specifications, assembly instructions, and troubleshooting guidelines. It includes information about the hardware components, memory map, input/output control registers, and various operational theories. Additionally, the manual covers the 512K expansion RAM card and includes diagrams, parts lists, and troubleshooting tips for both NTSC and PAL versions.
Uploaded by
raduvasilevalentin191Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 129
TANDY
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os
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COLOR COMPUTER 3
NTSC/PAL VERSION
with 512K Expansion RAM Card
Catalog Number: 26-3334
CUSTOM MANUFACTURED FOR RADIO SHACK, A DIVISION OF TANDY CORPORATION TABLE OF CONTENTS
SECTION I. GENERAL
Introduction «++-+44+
System Description ....
Memory Map .
1/0 Control Registers .
Chip Control Registers «5...
$BBO9E Vector Registers ..
1
1
1
1
1
1
SECTION II, SPECIFICATIONS
2.1 Technical ....,
2.2 Physical .
SECTION IIT, DISASSEMBLY/ASSEMBLY
3.1 Disassembly .....
3.2 Assembly «6.4 feeeeees
3.3 512K RAM Upgrade Instructions .
SECTION TV. BLOCK DIAGRAM
4.1 NTSC Version
4.2 PAL Version .
SECTION V, THEORY OF OPERATION
1 MC68B09E/MBL66B09E/HD68BO9E (IC1).
2 Memory (RAM) .ieeeee eee ee renee eee,
3 TCCLO14 (¥C2645QC) .
4 PAL Encoder (PAL Version Only)
5 BIAs (Ich and IC5) ..-.4
6 Keyboard Interface (105)
FROM (IC2) ce eseseeeereeeereaeee,
8
9
1
1
1
1
1
1
DAC Circuitry (IC7) .
SALT Circuitry seeeeees
Cassette Tape Format Information
RS-232C Connector (JK3)...
0
1
2 Cartridge Connector (GNI) -......
3 Power Transformer
a
5
Joysticks .
TV Switch Box (NISC Version Only)
SECTION VI, TROUBLESHOOTING
6.1 Introduction «
6.2 Video Problems ..seeseeeeeeeeee
No Display/No Sync/Noisy Video
Wrong Color
No Color -eeesseeeeeesesseeen eee
Random Character/Clear Sereen/No
RGB Problem... eeeeeren
Composite Video Signal Adjustment
(PAL Version Only) +... Keyboard Problems ..++ te
No Keyboard Entry/Wrong Character .
Processing Problem ...
Cassette Problems .
Motor Control Problem ...
Write Problem ....+5
Read Problem .,
RS-2320 Problem .
Sound Problen .
Joystick Problen
Cartridge Problen .
Power Supply Check -
NTSC Version ..+.
PAL Version ..
Major Waveforms
NTSC Version .
PAL Version «s+
SECTION VII. 512K EXPANSION RAM CARD
PCB VIEWS ....ss045
ELECTRICAL PARTS LIST
178.
79
SECTION VIII. NISC VERSION
PCB VIEWS vee. esses eee
ELECTRICAL PARTS LIST «4.444
+182,
vB
EXPLODED VIEW PARTS LIST. +90
EXPLODED VIEW seeeseeeeseeee +91
SEMICONDUCTOR INFORMATION. . +93,
SCHEMATIC DIAGRAM ..+4..400 +103
SECTION IX. PAL VERSION
PCB VIEWS ...,, settee eeeenee senses 108,
ELECTRICAL PARTS LIST .-......
EXPLODED VIEW PARTS LIST...
EXPLODED VIEW seeesseeeeeeeeeeceeeseee
SEMICONDUCTOR INFORMATION . 4.0.04
SCHEMATIC DIAGRAM ...,
fesse
fetes eee 1D
c12L
se eeeeel22
ve 126 LIST OF FIGURES
Color Computer 3 Installation «
Color Computer 3 Memory Map ss.ssscceeseceee 8
Memory Map for SAM Control Register ....-
Removal of Top Gover s+sy
Removal of Main PCB .
Block Diagram ...,
NISC Version
PAL Version .
MC6BBO9E Programming Model .
MCGBBO9E Pin Assignments .e..esessseeee
MC68BO9E Read/Write Timing at 0.89 Miz
DRAM Block Diagram ssseeeeeee
DRAM Timing .....e-5
Color Computer 3 Address Decoding ..
MMU Block Diagram .....
PIA Block Diagram ..... sees
Color Computer 3 Keyboard Array ..
DAC Block Diagram (IC7) ..
SALT Block Diagram (108) .
Golor Computer 3 Power Supply
1/0 Circuitry see.
RS-232C Connector Pinout vseceeseeee 248
Joystick Schematic .....+ se eeee ee ee D2
Antenna Switch Box Schematic ....ssssee 53
LIST OF TABLES
Line Printer Variables ... +50
Alternate Line Printer Variable Values ......50
Cartridge Connector Signals wee] SECTION I.
1,1 Introduction
The Color Computer 3 is a refined
version of Tandy's popular Color
Computer 2, It is designed to provide
the same reliable operation as its
predecessor, but it incorporates the
latest in electronic technology.
Figure 1-1 shows @ typical
installation of the Color Computer 3.
The Color Computer 3 contains an
interaal BASIC program in ROM which
is accessed when the unit is powered
up. Other program modules/cartridges
may be inserted into the receptacle
on the right side of the unit. an
optional Multi-pak Interface module
allows up to four progran paks to be
installed at the same time, with
selection of the specific module
active at any one time selected
either by software or by 2 switch on
the Multi-pak Interface. Additional
peripheral devices, such as an
exteraal disk drive, may be added to
the Color Computer 3 for additional
memory storage and retrieval.
ALL input and output ports for the
Color Computer 3, with the exception
of the program module/cartridge slot
and the RGB monitor output (for
(¥=8), are located on the rear panel
of the unit, These include the
joystick input ports (right and
left), Serial 1/0, Cassette I/0, TV
output jack (for standard color
television set and composite
monitor), POWER ON/OFF switch and
RESET switch. A recessed channel
switeh (for selecting either channel
on the TV - 3/4 for NISC and 1/2 for
PAL version) is also located on the
tear panel of the unit.
Note: Before installing any
peripheral device, always remember to
unplug the Color Computer's power
cord. This will prevent damage to the
device or to the Color Computer 3,
GENERAL
1.2 System Description
The primary fanctions of the Color
Computer 3 are performed by four
Large Scale Integration (LSI) chips,
plus Randon Access Memory (RAM) and
Read Only Memory (ROM). These four
chips are Labelad on the block
diagram as CPU, AGVG and two PIAS.
With only these four chips, plus
Random Access Memory (RAM), Read Only
Memory (ROM) and a power supply, the
Color Computer 3 will operate and
provide video output (RF, Composite,
Analog RGB). However, to’ allow
communication with the outside world,
T/O interfaces must be added.
The main component of any computer
system is the Central Processing Unit
(CPU, 161), It is the function of the
€PU to provide or request data and
select the proper address for this
data. In addition, the GPU is capable
of performing a limited set of
mathematical and logical operations
on the data.
ROM (1¢2) has the function of
Providing the CPU with a predefined
Set of instructions. Without ROM, the
PU would run wild and randonly
execute instructions. In normal
operation, the CPU jumps to the start
address in ROM, after the reset
switch has been pressed, and then
performs the reset program to set up
all of the programmable devices
Following this, the BASIC interpreter
tesiding in ROM is in control of the
cpu. RAM (IC16 - TCL9) provides storage
for the programs and/or data
currently being executed. In the
standard unit, these four ICs are 64K
x 4 but may be upgraded to sixteen
256K x 1 ICs as an option. (See
Paragraph 3.3 on page 28 for
instructions.) In addition, the same
RAM is used to generate the video
display. Normatly, no conflict will
be observed because the program will
use one portion of RAM and the
display will use another. During
normal usage, the BASIC interpreter,
located in ROM, will control the
execution of programs located in RAM.
A central component in the Color
Gomputer 3 is the Advanced Color
Video Chip (1C6). This chip provides
refresh and address multiplexing for
the RAM. It also provides all of the
system timing and device selection.
ACVC comprises the VDG (Video Display
Generator) function which supports
Wigh-Resolution mode, in addition to
sil other andes faciaded in the color
Computer 2, During High-Resolution
Geant at iris coe
AGVC can expand memory space up to
512K bytes. Having a built-in MMU
(Memory Management Unit), it can
support 2 banks of 256K-byte RAM,
each with a 9-line address bus, even
though the CPU possesses only 16
address Lines.
The remaining circuitry in the Color
Computer 3 is devoted to Input/Output
(1/0) communication, The most
important part of this circuitry is
the keyboard, which allows the
operator to enter information. Other
U0 circuits are provided to allow
joystick input, cassette input and
output, and RS-2320 input and output. woy3e{TPasuy € 1eInduoy soToD *T-T eAnBpa
OILSAOT *OlLSAOr
4437 AHO
ewo
HOLINOW @5u
DOTWNY
YOLINOW 1.3 Memory Map
Figure 1-2 shows the breakdown of the
large blocks of memory in the Color
Computer 3,
‘The rest of the section itemizes the
following registers:
* 1/0 Control Register
* Chip Control Register
© 685095 Vector Register
oT \e8809E vector,
‘ONTROL
s7ef00 | — —— frecister, vo
SUPER EXTENDED BASIC
s7€009—}_____|
‘CARTRIDGE ROM.
876000.
couoR aasic
s7A000—
EXTEND COLOR BASIC
s78000—} 4
‘70800 —} -—___|
‘STANDARD TEXT SCAEEN
70800
70000
's8€000—|—
HIGH RESOLUTION
TEKT SCREEN
s6co00— —
800c0—|
HIGH RESOLUTION
GRAPHIC SCREEN
50000 -
sc0000
Figure 1-2. Color Computer 3
Menory Map
ROM 324)
RAM (96K:
AM 612K {EXCEPT ROM. 110. CONTROL! 1.4 1/0 Control Registers
FFOO ~ FFO3 pra | 105
FFOO:
BIT 0 = KEYBOARD ROW 1 and right joystick switch 1
BIT 1 = KEYBOARD ROW 2 and left joystick switch 1
BIT 2 = KEYBOARD ROW 3 and right joystick switch 2
BIT 3 = KEYBOARD ROW 4 and Left joystick switch 2
BIT 4 = KEYBOARD ROW 5
BIT 5 = KEYBOARD ROW 6
BIT 6 = KEYBOARD ROW 7
BIT 7 = JOYSTICK COMPARISON INPUT
FFOL:
BIT 0 Gontrol of HSYNC (63.5ps) {° = 18Q* to OPU Disabled
Interrupt 1 = IRQ* to CPU Enabled
BIT 1 Control of Laterrupt 0 = Flag set on the
Polarity { falling edge of HS
1 = Flag set on the
rising edge of HS
BIT 2= Normally 1: 0 = Changes FFOO to the data direction register
BIT 3 = SEL 1: LSB of the two analog MUX select lines
BIT 4 = 1 Always
BIT 5 = 1 Always
BIT 6 = Not used
BIT 7 = Horizontal sync interrupt flag
FFO2:
BLT 0 = KEYBOARD COLUMN 1
BIT 1 = KEYBOARD COLUMN 2
BLT 2 = KEYBOARD COLUMN 3
BLT 3 = KEYBOARD COLUMN 4
BLT 4 = KEYBOARD COLUMN 5
BIT 5 = KEYBOARD COLUMN 6
BIT 6 = KEYBOARD COLUMN 7/RAM S{ZE OUTPUT
BIT 7 = KEYBOARD COLUMN 8
FFO3:
BIT 0 Control of VSYNC (16.667ms) 0 = IRQ* to CPU Disabled
Interrupt 1 = IRQ* to CPU Enabled
BIT 1 Control of Interrupt Polarity {0 2 sets flag on falling edge #8
1 = sets flag on rising edge FS
BLT 2 = NORMALLY 1; 0 = changes FFO2 to the data direction register
BIT 3 = SEL 2: MSB of the two analog MUX select Lines
BIT 4 = 1 Always
BIT 5 = 1 Always
BIT 6 = Not used
BIT 7 = Field syne interrupt flag FF20 - FR23
PIA rca
FF20:
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
Sourence
FF21:
BIT 0
BIT 1
BIT
BIT
BIT
BIT
BIT
BIT
FF22:
arr
BIT
BIT
BIT
BIT
BIT
BIT
BIT
°
1
2
3
4
5
6
7
FF23:
BIT 0
BIT 1
BIT
BIT
BIT
BIT
BIT
BIT
CASSETTE DATA INPUT
RS~232C DATA OUTPUT
6 BIT D/A 158
6 BIT D/A
6 BIT D/A
6 BIT D/A
6 BIT D/A
6 BIT D/A NSB
Control of the CD 0 = FIRQ* to CPU Disabled
(RS-2320 status) 1 = FIRQ* to CPU Enabled
Interrupt
Control of Interrupt [0 = sets Elag on falling edge CD
Polarity 1 = sets flag on rising edge cD
Normally 1: 0 = changes FF20 to the data direction register
Cassette Motor Control: 0 = OFF 1 = ON
1 Always
1 Always
Not Used
€D Interrupt Flag
RS~232¢ DATA INPUT
SINGLE BIT SOUND OUZPUT
RaM SIZE INPUT
RGB Monitor Sensing INPUT css
VG CONTROL OUTPUT GMO § UPPER/LOWER CASE*
WDC CONTROL OUTPUT M1 & INVERT
WG CONTROL OUTPUT ow
VDC CONTROL OUTPUT aa/G
Control of the Cartridge 0 = FIRQ* to CPU Disabled
Interrupt. 1 = FIRQ* to CPU Enabled
Control of Interrupt 0 = sets flag on falling edge CART*
Polarity 1 = sets flag on rising edge CART*
Normally 1: 0 = changes FF22 to the data direction register
Sound Enable
1 Always
1 Always
Not used
Cartridge Interrupt Flag
FP4O - FFBF; Not used
Note: FF22, FF23 are duplicated in tecl014 (¥02645QC), and V.D.G Control Bit
(Bit 3 through Bit 7) affects this 1c (TcC1OL4) only. 1,5 Chip Control Registers
FRO ~ FRDE acye 166
FF90: Initialization Register 0 (INITO)
BIT 7 = coco 1'= Color Computer 1 and 2 Compatible
BIT 6 = M/P 1 = MM enabled
BIT 5 = IEN 1 = Chip TRQ output enabled
BIT 4 = FEN 1 = Chip FIRQ output enabled
BIT 3 = MC3 1 = DRAM at XFEXX is constant
BIT 2 = KOZ 1 = Standard SCS
BIT 1 = mcL ROM map control (See table below)
BIT 0 = McO ROM map control (See table below)
vei] co ROM mapping
o} x 16K Internal, 16K External
1] o 32K Internal
fou 32K External (exeept for vectors)
FF9L: Initialization Register 1 (INITL)
BIT? =
BIT6 -
BIT 5 = TINS Timer Input Select: 1 = 70 asec / 0 = 63 psec
BIT4 =
BIT -
Bir2-
Bit)
BIT 0 = TR MMU Task Register Select
FF92: Interrupt Request Enable Register (IKQENR)
BIT7 =
BIT6 -
BIT 5 = TR Interrupt from Timer enabled
BIT 4 = BBORD Horizontal Border IRQ enabled
BIT 3 = YBORD Vertical Border IRQ enabled
BIT 2 = E12 Serial Data IRQ enabled
BIT 1 = 841 Keyboard IRQ enabled
BLT 0 = ETO Cartridge IRQ enabled
FP93: Fast Interrupt Request Enable Register (FIRQENR)
Bitz =
BIT6 -
BIT 5 = TuR Interrupt from Timer enabled
BIT 4 = MBORD Worizontal Border FIRQ enabled
BIT 3 = vBORD Vertical Border FIRQ enabled
BIT 2 = E12 Serial Data FIRQ enabled
BIT 1 = ETL Keyboard FIRQ enabled
BIT 0 = E10 Cartridge FIRQ enabled
“ie FF9G:
FF95:
E96:
BROT:
PROS:
FF99:
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
Buas
Timer Most Significant Nibble
Timer Least Significant Byte
TIMER: This ie a 12-bit interval timer. When a value is loaded into the
Reserved
Reserved
Video Mode Register
NSB, the count is automatically begun. The input clock is cither eo
14 Miz or horizontal syne, as selected by TINS (bit 5 of FF9L). As
the count falls through zero, an interrupt is generated (if
enabled), and the count is automatically reloaded.
Be 0 = alphanumeric, 1 = bit plane
Ber 1 = Burst phase inverted
Moc 1 = monochrome (on composite)
150 1 = 50 Hz vertical syne
TPR? Lines per row (See table below)
TPR! Lines per row (See table below)
LPRO Lines per row (See table below)
——
upr2| Lai) LeRo | Lines per character row
o jo | o | one (Graphics modes)
o yo |4 two (GoGo 1 and CoCo 2 onty)
0} t | o | three (GoGo 1 and CoCo 2 onty)
o fi ja eight
1 | 0 | 0 | nine
1 fo la (reserved)
+ | 1 | 0 | evetve (Gato 1 and Coco 2 only)
L 1 L (reserved) @
Video Resolution Register
LPeL
Horizontal resolution (See Video resolution on page
Lines per field (See table below)
LPFO Lines per field
uRES2
1?)
aRESL Horizontal resolution
RESO Horizontal resolution
CRESL Color resolution (See
CRESO Color resolution
LPFI| LPO! Lines per field
o | o 192
of. 200
1 jo Reserved
aia 225
“12+
Video resolution) FE9A:
RROD:
FFOE:
Border Register (All bits are 0 for CoCo 1 and CoCo 2 compatibility).
BIT
BIT
BIT
BIT
BIT
BT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
NOTE:
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
SOHN RuaS
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
NOTE:
REDL Most significant red bit
= GRRL Most significant green bit
= BLUL Most significant blue bit
REDO Least signifigant red bit
= GRNO Least significant green bit
= 5LU0 Least significant blue bit
Reserved
Vertical Scroll Register
= ysc3, (vert. Sero11)
= vsC2
= vscl
ysco
In the CoCo mode, the ¥SC's must be initialized to OF hex.
Vertical Offset 1 Regiater
= 118 (ert. Offset)
= 17
= ¥16
¥I5
ylé
= 113
v2
=v.
Vertical Offset 0 Register
Yo (ert. Offser)
yo
8
a)
¥6
YS
Ya
3
In CoCo mode, 15 - Y9 are not effective, and are controlled by
SAM bits F6 ~ FO. Also in CoCo mode, Y18 - YI6 should be 1, all others 0,
-13- FFOF:
Horizontal Offset 0 Register
BIT 7 = HVEN Horizontal Virtual Enable
BIT 6 = x6 Horizontal Offset address
BIT $ = x5 Horizontal Offset address
BIT 4 = x4 Horizontal Offset address
BIT 3 = x3 Horizontal Offset address
BIT 2 = x2 Horizontal Offset addres
BIT 1 = x1 Horizontal Offset address
BIT 0 = xo Horizontal Offset address
NOTE: HVEN enables a horizontal screan width of 128 bytes regardless of
the HRES bits and CRES bits selected. This will allow a "virtual" screen
somewhat larger than the displayed screen. The user can move the "window"
(the displayed sereen) by means of the horizontal offset bits. In
character mode, the screen width is 128 characters regardless of
attribute (or 64, if double-wide is selected).
“14- Memory Management Unit (40)
XEFAO - XFFAF, 6 bits (Write only)
‘The 8-bit CPU in the Color Gonputer 3 can directly address only 64K bytes of
memory with its 16 address lines (A0 ~ Al5), The memory management uait (MMU)
extends the address Lines to 19 (AO - Al8). This allows the computer to address
up to 512K bytes of memory ($00000 - $7FFFF),
The MMU consists of a multiplexer and a 16 x 6-bit of RAM array, Each of the
G-bit elements in this RAM array is an MMU task register, and the task
registers are used by the computer to determine the proper 8X segment of memory
to address, These registers are divided into 2 sets, 8 registers per set. The
TR bit of FF9] (task register select bit) determines which set is selected.
The relationship between the data in the task register and the generated
address is as follows:
Bit pS D4 03-2]
Corresponding
memory AIS AIT Al6 AlS AIG 413
address
bo-ps
(opu para) ~—.
AI3- Als. ——— ] Multiplexer
TR vit, ———> AI3- als
(Extended addresses?
AO- As
SELECT
When the CPU needs to access memory outside the standard 1/0 and control range
(XFF00 - XPFFF), CPU address lines Al3 - A15 and the TR bit determine the
address of the task register which the MMU will access vhile SELECT is low.
When the CPU writes data to the MMU, AQ - A3 determine the address of the task
register to be written to when SELECT goes high.
-15- ‘The data from the MMU is then used as the upper 6 address lines (A13 = A18) for
memory access, according to the following:
TR | AIS Al4 Al3 | (Address range) MMU location address ®
© foo 0 | xo000 = sires FeA0
8 fo 0 1 | x2000 = xR Fral
© | 0 1 0 | 4000 = xSP FEA2
0 7 0 1 1 | x6000 = SoeEe PEAS
© | t 00 | xa000 = xorrF FFAG
© | 1 0 t | xao0o = xBerr FFAS
0 | 1 10 | xc000 7 xDFRF Fras
o | 1 11 | R000 - xeFRF PFAT
1/0 oo | x0000 ~ xiner Fras
1/0 0 1 | x2000 = x3RFF 9
1) 9 40 | xé000 = xsreF FPA
1) 0 t 1 | x6000 = x7erF Fras
1 | too | xe000 * xoRre FPae
1) 1 0 L | xa000 = xBEFF FeAD
1) 1 10 | xc000 = xoerF Frag
1 | 111 | xt000 = xsree Fear
It is important to note that, in order for the MMU to function, the CoCo bit of
FE90 must be cleared, and the M/P bit of FF90 must be set. Prior to doing thia,
the desired addressing information for each Segment must be loaded into the
designated set of task registers. Por example, if a standard 64K map is desired
Matt Fecation | aca (Hex) Data (Bin) Address range
rao | 38 111000 70000 ~ 717FF
FFAL “39 1001 72000 = 73FFF
FFA A 11010 74000 = 15F8
eFA3 33 iio 76000 - 77888
FEAG “30 “i100 78000 - 79F#F
fas] aD nner 7A000 = 7BF#F
PFa6 a8 Lite 76000 ~ 7oRFF
rear oF uu 7H000 = JEFF
NOTE: Data loaded can be selected freely within che range of $00 - $3F,
=16- COLOR PALETTE
FFB0 - FFBF: 16 addresses, 6 bits each
@ rer vue Roo output, the bits are defined as follows:
Data Bit DS D4 D3 D2 D1 DO
Corresponding
RGB output | RI Gl BI RO CO BO
i
For the Composite output, the bits are defined as follows, where I is
intensity level and P is phas:
OO
Data Bit DS DA «D3 p2 DI DO
Corresponding
composite 1 10 P3 PZ PL PO
output,
Sone Color Examples
RcB Composite
Color
Binary Hex | Binary Hex
White qu (3F) | 110000 (30)
Black 00000 ¢a0) | oooo00 «00)
Bright Green 010010 (12) | 100010 (22)
e@ Medium Green 910000 (10) | oroo10 a2)
Dark Green 09010 (2) | 000010 (02)
Medium Magenta 101000 (28) | 910101 as)
For CoGo compatibility, the following values should be loaded upon
initialization. (NOTE: These are the RCB values.)
FRBO -- Green (12)
FEBL Yellow (36)
FFB2 Blue (09)
FRB3 Red (24)
EBS Bust Ge)
FEBS cyan (10)
FEB6 =~ Magenta (2D)
FEB? ~~ orange (26)
FEBB Black (00)
FBO Green (12)
FFBA Black (00)
EBB Buff (3k)
FBC Black (00)
FFBD Green (12)
FEBE Black (00)
FEBE =~ Orange (26)
NOTE: For the PAL version, ignore the table attributed to composite, VIDEO RESOLUTION
The combination of URES and CRES bits determine the resolution of the screen.
Alphanumeries: BP = 0, CoCo = 0
HRES2 ARES] HRESO CRES] CRESO
32 character} 9 - 0 - 1
40 character| 0 - 1 - L
80 character | 1 - 1 - 1
Graphics: BP = 1, GoGo = 0
Pixels | Colors | HRES2 HRESI HRESO CRESI CRESO
640 4 1 1 1 o 1
640 2 1 0 1 o 0
512 4 1 1 0 0 t
512 2 1 0 ° 0 0
320 16 1 1 1 1 0
320 4 1 ° 1 0 1
256 16 1 1 0 1 0
256 4 1 0 0 0 1
256 2 0 1 0 ° 9
160 16 1 0 1 1 0 @
In addition to the above modes, the previous CoCo modes are available.
COLOR COMPUTER MODE SELECTION
§MC6883 (SAM)
DISPLAY MODE REG. FF22
v2 vi vO 7 6 5 4 3
Alphanumerics o oo 0 o x x 0 ¢ss
Alphanumerics Inverted |0 0 0 o xX xk 0 css
Semigraphics - & o o 0 o xX x o x
64 X 64 Color Graphics | 0 0 1 1 0 0 0 css
128 X 64 Graphics o oo 1 1 0 0 1 oss
128 X 64 Cotor Graphics | 9 1 0 rr
128 X 96 Graphics o 1 1 too 4 1 oss
128K 96 Color Graphics | 1 0 rs er ee
128 X 192 Graphics 1 0 1 1 1 0 61 css
128 X 192 Golor Graphics| 1 1 0 rs
256 X 192 Graphics 1 1 0 1 o4 1 1 css
18 ALPHANUMERIC MODES
Text screen memory:
Even Byte (Character byte)
BIT
BIT
BIT
BIT.
BIT
BIT
BIT
BIT
odd
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
OeNesuar
Character
Character
Character
Character
Character
Character
Character
bit
bit
bie
bit
bit
bit
bit
Byte (Attribute byte)
erNurues
BLINK
UNDLN
FOND?
FGNDL
FGNDO
gunz
BoNDL
BaNDO
Characters
Characters
Foreground
Foreground
Foreground
Background
Background
Background
blink at 1/2 sec. rate
are underlined
color
color
color
color
color
color
bie
bic
dit
dit
dit
vic
NOTE: Attributes are not available when CoCo *
-19-
(pallette
(pallette
(pallette
(pallette
(pallette
(paltette
lL
addr.)
addr.)
addr.)
addr.)
addr.)
addr.) GRAPHICS MODES
16 Color Modes: (CRES1 = 1, CRESO = 0)
Byte from DRAM
Bit
Bit
Bie
Bie
Bit
Bit
Bit
Bit
4 Color Modes:
Byte from DRAM
Bit
Bit
Bit
Bit
Bic
Bic
Bit
Bit
2 Color Modes:
Byte from DRAM
Bit
Bic
Bic
Bir
Bic
Bit
Bit
Bir
PA, First Pixel
PA2, Firat Pixel
PAL, First Pixel
PAO, First Pixel
PA3, Second Pixel
PA2, Second Pixel
PAL, Second Pixel
PAO, Second Pixel
(ORESI = 0, CRESO = 1)
PAL, First Pixel
PAO, First Pixel
PAL, Second Pixel
PAO, Second Pixel
PAL, Third Pixel
PAO, Third Pixel
Pal, Fourth Pixel
PAO, Fourth Pixel
(CRESI = 0, CRESO = 0)
PaO, First Pixel
PAO, Second Pixel
PAO, Third Pixel
PAO, Fourth Pixel
PAO, Fifth Pixel
PAO, Sixth Pixel
PAO, Seventh Pixel
PAO, Eighth Pixel
Palette Addresses
PAS PAZ
PAL PAO Address of Contents Displayed
Pe eH ococore + coce
FFBO
EBL
FBZ
FEBS
FB
FFBS
FFB6
5PB7
FBS.
FEBS
FEBA
EBB
FEBC
FEBD
FFBE
FEBP
HH eoH-cornsoHHoo
Herorcrorererore SAM CONTROL REGISTERS: (FFCO - FFDF)
Clear Set
mee 2 me Seo ell Te
NOTE: These bits work Like the ones in the Motorola SAM chip
(1#6883/SN74L5785) in that by writing to the upper address of each two-address
group (data is don't care), the bit is set; by writing to the lower address,
the bit is cleared. The graphics modes and vertical offset bits are valid only
in the CoCo mode, but the other two bits are valid anytime. Note the only
semigraphics mode supported is Semi Four.
mer] 6 ae
FFDE| TYPE
r00| 3 ors
™ ile
FFD8 c RATE
OQ rast. 0,80
FEO? c 1. 78MH2
forts 1
roa |
eer [s , | otemtay || suena gett
weet Grvscr |) Ovoar lent ayo 0/2 ott
FFCC c i RG6, CGB
{BINARY} ”
reel 3} 7 acs
real 6 os
FFCOo |S Ft RG2
FCB c G2
reer [8 cas, net
ro
rece | —c [panne st
FFCS |S DISPLAY
@ Tali ts]ofofo]o
Frea | c MODE
beth.
etsy viafelel+|ifole
res ‘sa
ve TPO 1} O tT elri ge
@ wie
(S=Set Bit, C=Clear Bit, all Bits are cleared when SAM is reset)
Figure 1-3. Memory Map for SAM Control Register
21 1,6 688098 Vector Registers
FFEO ~ FFEF ceu Tel
FEFF: Reset vector 1S
FEFE: Reset vector HS
FFED: NMI vector LS
FEFC: NMI vector MS
FFFB: SWIL vector LS
FFFA: SWI vector MS
FFF9: IRQ vector 1S
FEF8: IRQ vector MS
FFE7: FIRQ vector LS
FRE6: — FIRQ vector MS
FFES: — SWI2 vector LS
FEP4: — SWI2 vector MS
FEF3: SWI3 vector LS
FEF2: — SWI3 vector MS
FEF1: Reserved
FFFO: Reserved
FFEF - FFE; Not used
LS: Least significant address byte
MS: Most significant address byte
=22- SECTION II,
e 2.1 Technical
cpu:
MEMORY SIZE:
KEYBOARD:
Number of keys:
Alphabetical
characters:
Numeric characters:
Space key:
Shift key:
Clear key:
Eater key:
Break (ESC) key:
Punctuation key:
Directional Control
key:
Function key:
SPECIFICATIONS
68B09E B-bit processor
Clock Speed ~ 0.89 Miz/1.78 Miz
ROM: 32K Byte (for BASIC)
RAM: 128K Byte (Expandable up to 512K)
57 Keys, microprocessor-scanned matrix
57 keys
26 keys (A to Z)
10 keys (0 to 9)
1 key
2 keys
1 key
1 key
1 key
7 keys
4 keys
2 keys (FI and F2)
Control key: 1 key
Alternate key: 1 key
57 keys
=23- VIDEO DISPLAY:
Character display:
Graphic display:
INTERFACE:
Serial interface:
Cassette interface:
Analog input inter~
face (for JOYSTICK):
512 (32 x 16) upper case characters
960 (40 x 24) upper/lower case characters
1920 (80 x 24) upper/lower case characters
256 x 192 dots 8 colors
320 x 192 dots 16 colors
640 x 192 dote 4 colors
RS-2320 4P-DIN
5P DIN 1500 baud
6P DIN x 2
Bus Line: 40 PIN connector for cartridge
CONTROLS:
Pover svitch: Push
Reset switch: Rey
Channel selector
switch: Slide
RE ouTPUT:
cH Frequency (Video) Frequency (Sound)
wtsc 3 61.25 + 0.25 Mie 4.5 + 0.02 Mite
467.25 + 0.25 mle 4.5 0.02 Miz
cH Frequency (Video) Frequency (Sound)
PAL 157.25 + 0.25 ute 5.5 + 0.02 Mite
264.25 4 0.25 wale 5.5 4 0.02 Mite
Output impedance: 75 ohm
RF Output terminal: RCA JACK
RF output Level: Esc 67°? aay
PAL 70 + SdBy
2h VIDEO/SOUND OUTPUT:
e Output terminal: RCA JACK
Output Level: lvp-p
Video: 0.719
O.1V (RL = 750bm)
Syne: 0.29,
O.1¥ (RL = 750hm)
Sound: Less than 1.0Vp-p (RL = 600ohm)
RGB (Analog)/Sound OUTPUT
Output terminal: lOpin pin header (Bottom
Output Level:
Red: 0.8(40.1) - 2.0(+0.2)¥de
NTSC 4 Green: 0.8(+0.1) = 2.0(+0.2)¥ée
Blue: 0,8(40.1)
2.0(40.2)¥de
Red: 0,6(40.1) - 1.8(40.2)vée
PAL Green: 0,6(+0.1)
e Blue: 0,6(40.1)
Hsyae: TTL level positive
1,8(40.2)Vde
1.8(40,2)vVde
Vsyac: TIL level positive
side)
(RL
(RL
(RL.
{RL
(RL,
(RL,
750bhm)
75obm)
750hm)
75ohm)
750hn)
750hm)
Sound: Less than .0Vp~p (RL = 6000hm)
POWER SUPPLY: NISC AC 120V/60Hz, 0.2 Amp RMS typical
PAL AC 240V/5OH2, 0,125 Amp RMS typical
2.2 Physicat
DIMENSIONS (Cabinet size):
Width: 14-3/4" (375 mm)
Height: 3-1/8" ( 79 mm)
Depth: 10-3/8" (264 mn)
NET WEIGHT: 4.85 Ibs (2.3 kg)
-25-
positive
positive
positive
positive
positive
positive SECTION III,
3.1 Di
embly
1, Disconnect power and remove signal
cables from the unit.
2. Remove cartridge from slot (if
applicable).
3, Turn the unit over and place it on
a soft surface to prevent danage
to the keyboard or top cover.
4. Loosen and renove the six (four
screws SI and two longer screws
$2) mounting screws which attach
the base to the top cover. (Figure
3-1)
5. Disconnect the cable from the wire
connector which is attached to the
keyboard (Figure 3-2).
6. Then disconnect the power
transformer at the 3-pin consector
on the main PCB (Figure 3-2).
7. Remove four (two screws $3 and evo
screws $4) screws which attach the
PCB to the bottom case cover
(Figure 3-2). If it is aecessary
to remove the shield from the PCB,
do so by removing the 16 rivets
which attach it to the PCB.
Figure 3-1, Removal of Top Cover
-26-
DISASSEMBLY /ASSEMBLY
3.2 Assembly
Assemble the Color Computer 3 in the
reverse order of disassembly. The PCB
shield is attached to the PCB with
metal rivets. These shields must be
in place to provide proper RFI
shielding.
Set the wire assembly from the
transformer and flat cable from the
keyboard to the connector on the PCB.
Two different types of screws are
used to mount the PCB and the top and
bottom cabinet. Ensure that the
correct type is used when reassembl~
ing,
‘The strain relief on the power cord
consists of wrapping the cord around
the plastic bosses on the rear side
of the unit. Ensure that the power
cord is properly routed to afford
strain relief to the trasformer
connections.
+ Removal of Main PCB 3.3 512K RAM Upgrade Instructions
To upgrade a 128K memory unit to a
512K memory unit, follow the
procedure below.
1. Remove the top cabinet as
described in 3.1, Remove four ICs
(IC16 - TC19) from the IC sockets
of the PCB (Figure 3-3),
unsolder C65 82 pF ceranic
capacitor and remove it,
2. Three aylon stand-offs are
packaged with the RAM card. Insert
then into corresponding holes of
the RAM card (Figure 3-4).
3. Align che pin socket of the RAM
card over CN4 through CN6, then
slowly lower the Board.
4. Snap each stand-off into the
corresponding hole on the computer
PCB.
5. Connect the computer's AC cord and
signal cables to a TV monitor and
run the following prograa to
verify proper operation of the new
monory chips.
6, Secure the top and bottom
cabinets.
