Slam Tool 130nm
technology
Training Guide
Confidential
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SERIAL No Heading
1 How to start slam tool on Linux/Windows
2 Bind-keys
3 Task
4 Golden guidelines
5 LVS
6 DRC
7 Steps follow to go ahead
8 Name of Cells
9 Basic concept on some terminologies
10 FEOL/BEOL
11
12
13
14
Open the Terminal
Run The command “ ssh –X arf1@192.168.1.107 ” and
put password:- arfdesign
The server address may change
After Putting password click “enter” and run
“ virtuoso & ” command to open virtuoso
Go to Admin then click on Configure and just tick √ mark the menus on graphic
window and apply it.
Go to Modify Configuration Provide details on popup window
And click on Replace cfg and click on done.
2 3
To create Library Go to Admin and create library , select the with cfg option as
shown below, Provide details to the pop-up window on create library.
1
2
Open this application on your WINDOW System/laptop
Run Ximing app to connect VPN server
You will get this dialog window by
opening the Putty app.
Now provide the details as same as it
has filled.
After filling all data , click on + mark
of SSH
Now You will gate X11 option , click
on it and then tick mark on
Enable X11 forwarding then click
Open
“terminal” will get open
In the terminal :-
Please follow the same steps
How to open in Linux
environment page.
Now All setting is done to start working on
SLAM tool
Go Ahead Now
Thank you
Serial no Commands Description
1 P Path Drawing
2 R Rectangular Drawing
3 A To Select the component
4 Ctrl+A All Select
5 Shift+A Area wise select
6 D De-select
7 Ctrl+D All De-select
8 Shift+D Area wise De-select
9 C Copy
10 S Stretch
11 M Move
12 K Scale
13 Shift+K Remove Scale
14 Q Edit Properties
Serial no Commands Description
15 I To Instance cell
16 O Contact/via/Pcon/Dcon
17 F Fit To Screen
18 N Straight Path
19 Shift+Z Zoom Out
20 Ctrl+Z Zoom In
21 C+F3 Multiple copy
22 Shift+U Redo
23 F2 / Ctrl+W Save
24 Shift+C Chop
25 Shift+T Rotation
26 Ctrl+I Create TLG (PMOS/NMOS Device)
27 Shift+X Highlight
28 Shift+S Line Stretch
29 Ctrl +S Split/bend
30 Shift+J Drawing
Serial no Commands Description
31 Shift+Q Close cellview
32 U Undo
Serial No Commands Description
1 E Expand the schematic hierarchy
2 Shift+E Go back from the schematic hierarchy
3
4
5
6
7
8
9
10
Drawing of Metals with different orientation.
Execute each and every commands on each
components.
Attaching Vias with different Metals.
Layers Identifications of PMOS and NMOS.
Draw each layers of PMOS and NMOS.
Know difference between PMOS and NMOS.
.
Training Theory Class will be taken By Trainer after
completion of TASK assignment.
Subject of the class will be
ALL ABOUT VLSI FABRICATION PROCESS
VLSI Industry Network.
Time To Market.
Different types of ICs.
Introduction to wafer .
Introduction to Layout.
Introduction to each layer of Layout.
Even Metal orientation Must be parallel to X-axis(horizontal).
Odd Metal orientation Must be parallel to Y-axis(vertical).
All standard cell height must be same.
Power/Ground line must be connected by M2.
All Layer must be placed by following “half drc” rule.
Never Draw Diffusion(OD) layer to fix DRC.
Must use 2 or more than 2 Vias
Height of Standard cell must be decided by keeping the components at minimum
DRC spacing.
Device should be placed at 1st quadrant.
Add dummy in schematic if you added in the layout.
Name the device by text layer to identify the device.
Add pr-boundary for every cell.
Add N-TAP for PMOS and P-TAP for NMOS.
Keep PMOS at TOP side and NMOS at BOTTOM side in the Layout.
Poly orientation must be vertical.
For the design of layout and to get exact in terms of
manufacturing process of the Chip (ICs), we must
go-ahead through a verification process.
There are Two verification process are there
1. LVS
2. DRC
What is LVS ?
LVS stands for Layout vs. Schematic, Basically it is comparison between
components given in the schematic and designed in the Layout.
Layout Versus Schematic (LVS) checking compares the extracted net-list from the
layout to the original schematic net-list to determine if they match means LVS
is clean.
The comparison check is considered clean if all the devices and nets of the
schematic match the devices and the nets of the layout. The device properties
can also be compared to determine if they match within a certain tolerance.
When properties are compared, all the properties must match as well to get a
clean comparison.
To Fire LVS Run Go to Verification and click on FLVS II , then a pop-up window will
come, Please see next slide
On this Pop-up window Please fill for
physical cell info :
Library name :- Your library name
Library path :- /home/arf1/workarea
Cell name :- Your cell name
View name :- lay
Logical cell info :
Cell name :- Your cell name
View :- sch (by-default it is hd1)
Inside LVS DECK please choose
option t013m9.flvs
Click Ok and then go to virtuoso to
get to know your LVS result
What is DRC ?
DRC stands for Design Rule check. The process technology has defined some
design rule for each layers which are valid in the layout for that technology to
get manufactured of the ICs, that rule has to meet to get DRC clean.
DRC check ensure the manufacture of chip will not result failure.
To Run DRC go to Verification option on virtuoso and click on DRC and then
click on FDRC II, will open a pop-up window
Provide the Library and cell name and press Ok
Then go to virtuoso to get to know your DRC results
Floor plan/Placement/Dumping of the device
Clean Base DRC
Routing
Clean Metal DRC
LVS
INVERTER • OR_X1
BUFFX1 • OR_X2
BUFFX2 • XOR_X1
BUFFX4 • XNOR2_X1
BUFFX8 • XNOR2_X2
NANDX1 • MUX
NANDX4 • MUX_4X1
NANDX8 • MUX_4X2
NOR • TIE-LO
NOR2X • TIE-HI
NOR3X
ORGATE2X
ANDX1
ANDX2
Half adder OSC_25KHz
Full adder DLY_4X1
Biasgen MUX_TELEMETRY
OpAmp Input Pair
Cascode Current Mirror
GPIO MUX
Vreg_amp
OVPFETDR
LVSHIFT2X
LVLSHIFT4X
Half DRC Rule
Half Cell
Full Cell
Unit Cell
Matching Concept
Floor plan/Placement
Routing
Std cell vs. Custom Std cell
FEOL Layer BEOL Layer
Front End Of Line Back End Of Line
NW M1 VIA1
PP M2 VIA2
NP M3 VIA3
OD/Diff/RX M4 VIA4
Poly M5 VIA5
DCON M6 VIA6
PCON M7 VIA7
M8 VIA8
M9
