F2838x Firmware Development Package

USER’S GUIDE

Copyright © 2024
Texas Instruments Incorporated
Copyright
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Revision Information
This is version 5.02.00.00 of this document, last updated on Sun Apr 7 02:08:58 IST 2024.

2 Sun Apr 7 02:08:58 IST 2024

 Table of Contents

Table of Contents
Copyright . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Detailed Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Getting Started and Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Project Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Debugging Dual Core Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4 Project: Adding Bit-field or DriverLib Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3 Interrupt Service Routine Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1 Interrupt Hardware Priority Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 PIE Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 Software Prioritization of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 CPU 1 Bit-field Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 ADC SOC Software Force (adc_soc_software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 ADC ePWM Triggering (adc_soc_epwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 ADC temperature sensor conversion (adc_soc_epwm_tempsensor) . . . . . . . . . . . . . . . . . . 53
4.4 ADC Synchronous SOC Software Force (adc_soc_software_sync) . . . . . . . . . . . . . . . . . . . 54
4.5 ADC Continuous Triggering (adc_soc_continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) . . . . . . . . . . . . . . . 54
4.7 ADC PPB Offset (adc_ppb_offset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.8 ADC PPB Limits (adc_ppb_limits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.9 ADC PPB Delay Capture (adc_ppb_delay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.10 CLA arcsine(x) using a lookup table (cla_asin_cpu01) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.11 CLA arctangent(x) using a lookup table (cla_atan_cpu01) . . . . . . . . . . . . . . . . . . . . . . . 56
4.12 Buffered DAC Enable (buffdac_enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.13 Buffered DAC Sine DMA (buffdac_sine_dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.14 DMA GSRAM Transfer (dma_gsram_transfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.15 ECAP APWM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.16 EMIF ASYNC module (emif1_16bit_asram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.17 EMIF1 SDRAM Module (emif1_16bit_sdram_far) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.18 EMIF1 SDRAM Module (emif1_16bit_sdram_dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.19 EMIF1 SDRAM Module (emif1_32bit_sdram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.20 EPWM Trip Zone Module (epwm_trip_zone) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.21 EPWM Action Qualifier (epwm_updown_aq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.22 EPWM Action Qualifier (epwm_up_aq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.23 EPWM dead band control (epwm_deadband) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.24 HRPWM Slider Test (hrpwm_slider) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.25 HRPWM Duty SFO (hrpwm_duty_sfo_v8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.26 HRPWM SFO Test (hrpwm_prdupdown_sfo_v8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.27 HRPWM Dead-Band Example (hrpwm_deadband_sfo_v8) . . . . . . . . . . . . . . . . . . . . . . . 62
4.28 External Interrupts (ExternalInterrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.29 External Interrupts Latency (ExternalInterruptLatency) . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.30 SCI Echoback (sci_echoback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.31 SDFM Filter Sync CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.32 SDFM Filter Sync CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.33 SDFM Filter Sync DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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4.34 SDFM PWM Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5 Dual Core Bit-field Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1 ADC & EPWM on CPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 DMA Transfer Shared Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3 Shared RAM management (CPU1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4 Shared RAM management (CPU2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5 SDFM Filter Sync CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.6 SDFM Filter Sync CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 C28x Driver Library Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1 ADC ePWM Triggering Multiple SOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 ADC Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 ADC Burst Mode Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.4 ADC SOC Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5 ADC PPB PWM trip (adc_ppb_pwm_trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.6 ADC High Priority SOC (adc_high_priority_soc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.7 ADC Interleaved Averaging in Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.8 ADC Open Shorts Detection (adc_open_shorts_detection) . . . . . . . . . . . . . . . . . . . . . . . 80
6.9 ADC Software Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.10 ADC ePWM Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.11 ADC Temperature Sensor Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.12 ADC Synchronous SOC Software Force (adc_soc_software_sync) . . . . . . . . . . . . . . . . . . . 82
6.13 ADC Continuous Triggering (adc_soc_continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.14 ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) . . . . . . . . . . . . . . . 83
6.15 ADC PPB Offset (adc_ppb_offset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.16 ADC PPB Limits (adc_ppb_limits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.17 ADC PPB Delay Capture (adc_ppb_delay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.18 BGCRC CPU Interrupt Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.19 BGCRC Example with Watchdog and Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.20 CLA-BGCRC Example in CRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.21 CLA-BGCRC Example in Scrub Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.22 CPU1 Secure Flash Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.23 CAN External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.24 CAN External Loopback with Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.25 CAN-A to CAN-B External Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.26 CAN External Loopback with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.27 CAN Transmit and Receive Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.28 CAN Error Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.29 CAN Remote Request Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.30 CAN example that illustrates the usage of Mask registers . . . . . . . . . . . . . . . . . . . . . . . . 90
6.31 CLA arcsine(x) using a lookup table (cla_asin_cpu01) . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.32 CLA arctangent(x) using a lookup table (cla_atan_cpu01) . . . . . . . . . . . . . . . . . . . . . . . 91
6.33 CLA background nesting task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.34 Controlling PWM output using CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.35 Just-in-time ADC sampling with CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.36 Optimal offloading of control algorithms to CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.37 Handling shared resources across C28x and CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.38 CLB Timer Two States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.39 CLB Interrupt Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.40 CLB Output Intersect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.41 CLB PUSH PULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.42 CLB Multi Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.43 CLB Tile to Tile Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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6.44 CLB based One-shot PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.45 CLB AOC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.46 CLB AOC Release Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.47 CLB Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.48 CLB XBARs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.49 CLB AOC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.50 CLB Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.51 CLB LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.52 CLB Lock Output Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.53 CLB INPUT Pipeline Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.54 CLB Clocking and PIPELINE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.55 CLB SPI Data Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.56 CLB SPI Data Export DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.57 CLB Trip Zone Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.58 CLB GPIO Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.59 CLB CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.60 CLB Auxilary PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.61 CLB PWM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.62 CLB Event Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.63 CLB Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.64 CLB State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.65 CLB External Signal AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.66 CLB Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.67 CLB Empty Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.68 C28x Common Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.69 CMPSS Asynchronous Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.70 CMPSS Digital Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.71 CPU Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.72 Buffered DAC Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.73 Buffered DAC Random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.74 Buffered DAC Sine (buffdac_sine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.75 DCC Single shot Clock verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.76 DCC Single shot Clock measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.77 DCC Continuous clock monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.78 DCC Continuous clock monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.79 DCC Detection of clock failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.80 DCSM Memory partitioning Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.81 Empty DCSM Tool Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.82 DMA GSRAM Transfer (dma_ex1_gsram_transfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.83 DMA GSRAM Transfer (dma_ex2_gsram_transfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.84 eCAP APWM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.85 eCAP Capture PWM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.86 eCAP APWM Phase-shift Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.87 eCAP Software Sync Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.88 Pin setup for EMIF module accessing ASRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.89 EMIF1 ASYNC module accessing 16bit ASRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.90 EMIF1 module accessing 16bit ASRAM as code memory. . . . . . . . . . . . . . . . . . . . . . . . 109
6.91 EMIF1 module accessing 16bit SDRAM using memcpy_fast_far(). . . . . . . . . . . . . . . . . . . . 110
6.92 EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power
Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.93 EMIF1 module accessing 32bit SDRAM using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.94 EMIF1 module accessing 16bit SDRAM using alternate address mapping. . . . . . . . . . . . . . . 111

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6.95 EMIF1 ASYNC module accessing 16bit ASRAM HIC FSI . . . . . . . . . . . . . . . . . . . . . . . . 111
6.96 EMIF1 ASYNC module accessing 8bit HIC controller. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.97 Empty Project Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.98 ePWM Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.99 EPWM Configure Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.100Realization of Monoshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.101EPWM Action Qualifier (epwm_up_aq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.102ePWM Trip Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.103ePWM Up Down Count Action Qualifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.104ePWM Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.105ePWM Digital Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.106ePWM Digital Compare Event Filter Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.107ePWM Valley Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.108ePWM Digital Compare Edge Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.109ePWM Deadband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.110ePWM DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.111Frequency Measurement Using eQEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.112Position and Speed Measurement Using eQEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.113ePWM frequency Measurement Using eQEP via xbar connection . . . . . . . . . . . . . . . . . . . 120
6.114Frequency Measurement Using eQEP via unit timeout interrupt . . . . . . . . . . . . . . . . . . . . . 121
6.115Motor speed and direction measurement using eQEP via unit timeout interrupt . . . . . . . . . . . . 122
6.116ERAD Profile Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.117ERAD Profile Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.118ERAD HWBP Monitor Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.119ERAD HWBP Monitor Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.120ERAD HWBP Stack Overflow Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.121ERAD HWBP Stack Overflow Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.122ERAD Profiling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.123ERAD Profiling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.124ERAD MEMORY ACCESS RESTRICT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.125ERAD INTERRUPT ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.126ERAD AND CLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.127ERAD PWM PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.128ERAD Profiling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.129ERAD Profile Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.130ERAD Stack Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.131ERAD Profile Interrupts CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.132Flash ECC Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.133Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly . . . . . . . . . . . . . . 133
6.134FSI daisy chain topology, lead device example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.135FSI daisy chain topology, node device example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.136FSI Loopback:CPU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.137FSI Loopback CLA control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.138FSI DMA frame transfers:DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.139FSI data transfer by external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.140FSI data transfers upon CPU Timer event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.141FSI and SPI communication(fsi_ex6_spi_main_tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.142FSI and SPI communication(fsi_ex7_spi_remote_rx) . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.143FSI P2Point Connection:Rx Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.144FSI P2Point Connection:Tx Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.145FSI star connection topology example. FSI communication using CPU control . . . . . . . . . . . . 142
6.146Device GPIO Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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6.147Device GPIO Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.148Device GPIO Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.149HRCAP Capture and Calibration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.150HRPWM Duty Control with SFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.151HRPWM Slider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.152HRPWM Period Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.153HRPWM Duty Control with UPDOWN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.154HRPWM Slider Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.155HRPWM Duty Up Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.156HRPWM Period Up-Down Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.157I2C Digital Loopback with FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.158I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.159I2C Digital External Loopback with FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.160I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.161I2C controller target communication using FIFO interrupts . . . . . . . . . . . . . . . . . . . . . . . . 150
6.162I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.163External Interrupts (ExternalInterrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.164Multiple interrupt handling of I2C, SCI & SPI Digital Loopback . . . . . . . . . . . . . . . . . . . . . 152
6.165CPU Timer Interrupt Software Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.166EPWM Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.167LED Blinky Example with DCSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.168Low Power Modes: Device Idle Mode and Wakeup using GPIO . . . . . . . . . . . . . . . . . . . . . 155
6.169Low Power Modes: Device Idle Mode and Wakeup using Watchdog . . . . . . . . . . . . . . . . . . 155
6.170Low Power Modes: Device Standby Mode and Wakeup using GPIO . . . . . . . . . . . . . . . . . . 155
6.171Low Power Modes: Device Standby Mode and Wakeup using Watchdog . . . . . . . . . . . . . . . . 156
6.172MCAN Loopback with Interrupts Example Using SYSCONFIG Tool . . . . . . . . . . . . . . . . . . 156
6.173McBSP loopback example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.174McBSP loopback with DMA example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.175McBSP loopback with interrupts example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.176McBSP loopback with interrupts example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.177McBSP loopback example using SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.178McBSP external loopback example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.179McBSP external loopback example using SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.180McBSP TDM-8 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.181Correctable & Uncorrectable Memory Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.182Empty SysCfg & Driverlib Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.183Tune Baud Rate via UART Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.184SCI FIFO Digital Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.185SCI Digital Loop Back with Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.186SCI Echoback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.187stdout redirect example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.188SDFM Filter Sync CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.189SDFM Filter Sync CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.190SDFM Filter Sync DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.191SDFM PWM Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.192SDFM Type 1 Filter FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.193SDFM Filter Sync CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.194SD FATFS Library Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.195SD FATFS Library Example with exFAT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.196SPI Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.197SPI Digital Loopback with FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.198SPI Digital External Loopback without FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 171

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6.199SPI Digital External Loopback with FIFO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.200SPI Digital Loopback with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.201SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.202SPI DMA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.203Missing clock detection (MCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.204XCLKOUT (External Clock Output) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.205CPU Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.206CPU Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.207USB HUB Host example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.208USB CDC serial example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.209USB HID Mouse Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.210USB Device Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.211USB Generic Bulk Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.212USB HID Mouse Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.213USB HID Keyboard Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.214USB Mass Storage Class Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.215USB Dual Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.216USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk) . . . . . . . . . . . . . . . . 178
6.217Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.218CM Empty Project Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.219CPU1 Empty Project Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.220Flash Programming Solution using SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.221LED Blinky Example (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.222CAN External Loopback with Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.223EMIF1 ASYNC module accessing 16bit ASRAM through CPU1 and CPU2. . . . . . . . . . . . . . 180
6.224EMIF1 ASYNC module accessing 16bit ASRAM trhough CPU1 and CPU2. . . . . . . . . . . . . . 180
6.225CM Empty Project Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.226Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly . . . . . . . . . . . . . . 181
7 Dual Core Driver Library Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.1 NMI handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.3 CLA arcsine(x) using a lookup table (cla_asin_cpu01) . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.4 CLA Arcsine Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.5 CLA 2 Pole 2 Zero Infinite Impulse Response Filter (cla_iir2p2z_cpu01) . . . . . . . . . . . . . . . . 184
7.6 CLA 2-pole 2-zero IIR Filter Example for F2837xD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.7 DCSM Memory Access control by CPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.8 DCSM Memory Access by CPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.9 DMA Transfer Shared Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.10 DMA Transfer Shared Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.11 CPU1 Empty Project Example >/h1> This example is an empty project setup for Driverlib development
for CPU1. CPU2 Empty Project Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.12 FSI Multi-Rx Tag-Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.13 FSI Multi-Rx Tag-Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.14 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.15 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.16 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 189
7.17 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 189
7.18 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.19 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.20 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 190
7.21 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 190
7.22 LED Blinky Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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7.23 LED Blinky Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.24 Shared RAM Management (CPU1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.25 Shared RAM Management (CPU2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.26 Shared RAM Management (CPU1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.27 Shared RAM Management (CPU2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.28 NMI handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.29 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.30 NMI handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.31 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.32 NMI handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.33 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8 C28x and CM Dual Driver Library Example Applications . . . . . . . . . . . . . . . . . . . . . . . 197
8.1 DCSM Memory Access by CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
8.2 DCSM Memory Access control by master CPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
8.3 Ethernet + IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . 198
8.4 Ethernet + IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . 199
8.5 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.6 IPC basic message passing example with interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.7 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 200
8.8 IPC message passing example with interrupt and message queue . . . . . . . . . . . . . . . . . . . 200
8.9 LED Blinky Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
9 CM Driver Library Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.1 AES ECB Encryption Example (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.2 AES ECB De-cryption Example (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.3 AES GCM Encryption Example (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.4 AES GCM Decryption Example (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.5 CAN Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.6 CAN External Loopback with Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.7 CAN-A to CAN-B External Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.8 CAN Transmit and Receive Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
9.9 Demonstrate DMPU usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
9.10 Demonstrate CM-MPU sub-region configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
9.11 Ethernet Low Latency Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
9.12 Ethernet MAC Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
9.13 Ethernet Basic Transmit and Receive PHY Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . 206
9.14 Ethernet Threshold mode with level PHY loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
9.15 Ethernet PTP Basic Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
9.16 Ethernet PTP Basic Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.17 Ethernet PTP Offload Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.18 Ethernet PTP Offload Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.19 Ethernet MAC CRC and Checksum Offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
9.20 Ethernet Transmit Segmentation Offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
9.21 Ethernet MAC Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.22 Ethernet RevMII Example MII side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.23 Ethernet RevMII Example RevMII side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.24 Flash ECC Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.25 GCRC example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.26 I2C Loopback with Slave Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.27 MCAN Internal Loopback with Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
9.28 MCAN External Loopback with Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
9.29 Demonstrate memconfig diagnostics and error handling. . . . . . . . . . . . . . . . . . . . . . . . . 213
9.30 Demonstrate CM4 MPU usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Sun Apr 7 02:08:58 IST 2024 9

Table of Contents

9.31 SSI Loopback example with interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

9.32 SSI Loopback example with UDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.33 Systick interrupt example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.34 CPU Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.35 UART Echoback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.36 UART Loopback example with UDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
9.37 uDMA RAM to RAM transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
9.38 uDMA RAM to RAM transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.39 USB Composite Serial Device (usb_dev_cserial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.40 USB HID Mouse Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.41 USB HID Keyboard Device (usb_dev_keyboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.42 USB Generic Bulk Device (usb_dev_bulk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.43 USB HID Mouse Host (usb_host_mouse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.44 USB HID Keyboard Host (usb_host_keyboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.45 USB Mass Storage Class Host (usb_host_msc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
9.46 USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk) . . . . . . . . . . . . . . . . 219
9.47 USB HUB Host example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
9.48 Windowed watchdog expiry with NMI handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
10 Device APIs for examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.2 API Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
IMPORTANT NOTICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

10 Sun Apr 7 02:08:58 IST 2024

 Introduction

1 Introduction
The Texas Instruments® F2838x Firmware development library is a group of example applications
and helper libraries that demonstrate the basics of getting started with a F2838x device.
The following chapter (chapter 2) provides a step by step guide for from scratch project
creation for each core as well as debug. It is highly recommended that users new to the
F2838x family of devices start by reading this section first.
Because the F2838x devices have three cores the example applications have been broken up to
distinguish which examples run on each core.

The driver library example applications which run exclusively on the C28x CPU core can be
found in the ∼/driverlib/f2838x/examples/c28x directory.
The driver library example applications which require both C28x CPU Cores to run can be
found in the ∼/driverlib/f2838x/examples/c28x_dual directory.
The driver library example applications which run exclusively on the CM core can be found in
the ∼/driverlib/f2838x/examples/cm directory.
The driver library example applications which require both cores of CM and C28x to run can
be found in the ∼/driverlib/f2838x/examples/c28x_cm directory.

The examples provided are built for controlCARD compatibility.

As users move past evaluation, and get started developing their own application, TI recommends
they maintain a similar project directory structure to that used in the example projects. Example
projects have a heirarchy as follows:

Main project directory

• C28x project folder (c28x)
* C28x project sources (∗.c, ∗.h)
* CCS folder (ccs)
· CCS project specific files
• C28x CM project folder (c28x_cm)
* CPU 2 project sources (∗.c, ∗.h)
* CCS folder (ccs)
· CCS project specific files
• C28x Dual project folder (c28x_dual)
* CPU 2 project sources (∗.c, ∗.h)
* CCS folder (ccs)
· CCS project specific files
• CM project folder (cm)
* CM project sources (∗.c, ∗.h)
* CCS folder (ccs)
· CCS project specific files

1.1 Detailed Revision History

V3.04.00.00

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Introduction

Updated Driver Library to v3.04.00.00

Added ERAD examples ported from F28004x
Added CLB Type 3 examples
Added new examples for I2C, SDFM, ADC
Added Flash linker command file with CRC

V3.03.00.00

Updated Driver Library to v3.03.00.00

Added projectspec for driverlib.
Updated compiler version to 20.2.1.LTS for all driverlib examples
Updated the examples to use the new pinmap macro names.
Added Sysconfig pinmux support to all examples
Added CLB Type2 examples- clb_ex18 to clb_ex23
Added DCSM Tool example- dcsm_security_tool
Added example for PWM trip through ADCxEVT- adc_ex10_ppb_pwm_trip
Added eCAP example to demonstrate generation of phase-shifted APWM outputs-
ecap_ex3_apwm_phase_shift
Added Example for Baud Tune via SCI- baud_tune_via_uart
Added CPU1-CPU2 IPC example- ipc_ex1_basic , ipc_ex2_msgqueue
Added ERAD examples-erad_ex8_hwbp_stack_threshold_detection ,
erad_ex9_ctm_max_load_profile_function
Add CPU1/CPU2/CM secure boot example-boot_ex1_cpu1_cpu2_cm_secure_flash
Updated examples to disable watchdog by default

V3.02.00.00

Updated Driver Library to v3.02.00.00

Updated driverlib examples: Examples for GPIO, SPI, I2C, SCI to use sysconfig
Updated DCC examples and DMA bitfield dual core for 25MHz clock
Added CAN Error Generation example

V3.01.00.00

Updated Driver Library to v3.01.00.00

New driverlib examples: Added pinumx examples with sysconfig support, daisy-chain exam-
ples.
CLB tool enhancements to support for 8 tiles on F2838x

V2.01.00.00

Updated Driver Library to v2.01.00.00

Several bug fixes in driverlib examples - details in release notes
New driverlib examples: C28x - ADC, CLB, DAC, DCC, DCSM , EPWM , Interrupt
, LED with DCSM , FLASH, C28xC M − DCSM, C28xd ual − DCSM, EM IF, CM −
F LASHU pdateddriverlibexamples : C28x − ADC, CLB, ERAD, LP M, C28xC M −
IP C, C28xd ual − DM A, CM − Ethernet, Stacksizeupdatesf orseveralexamples

12 Sun Apr 7 02:08:58 IST 2024

 Introduction

Several linker command files updated as part of bug fixes - details in release notes
Several bug fixes/ enhancement in bitfield commons - details in release notes

V2.00.00.03

Updated Driver Library to v2.00.00.03

Several bug fixes in driverlib examples - details in release notes
New driverlib examples: CLB, FSI, SDFM, CM-USB, EPWM and USB examples

V2.00.00.02

This version is the first release (packaged with development tools) of the F2838x header files,
bitfield commons, drivers and examples.

Sun Apr 7 02:08:58 IST 2024 13

Introduction

14 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

2 Getting Started and Troubleshooting

Project Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Project: Adding Bit-field or DriverLib Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Debugging Dual Core Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.1 Introduction
Because of the sheer complexity of the F2838x devices, it is not uncommon for new users to have
trouble bringing up the device their first time. This guide aims to give you, the user, a step by step
guide for how to create and debug projects from scratch. This guide will focus on the user of a
F2838x controlCARD, but these same ideas should apply to other boards with minimal translation.

2.2 Project Creation

A typical F2838x application consists of three separate CCS projects: one for CPU 1, one for CPU2
and one for CM. The three projects are completely independent and have no real linking between
them as far as CCS is concerned.

Sun Apr 7 02:08:58 IST 2024 15

Getting Started and Troubleshooting

CPU 1 Subsystem Project Creation

1. From the main CCS window select File -> New -> CCS Project. Select your Target as
"TMS320F28388D" and use the "C28XX [C2000]" Tab. Name your project and choose a
location for it to reside. Click Finish and your project will be created.

Figure 2.1: Creating a new C28 project

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 Getting Started and Troubleshooting

2. Before we can successfully build a project we need to setup some build specific settings. Right
click on your project and select Properties. Look at the Processor Options and ensure they
match the below image:

Figure 2.2: Project configuration dialog box

Sun Apr 7 02:08:58 IST 2024 17

Getting Started and Troubleshooting

3. In the C2000 Compiler entry look for and select the Include Options. Click on the
add directory icon to add a directory to the search path. Click the File System but-
ton to browse to the common\include folder of your C2000Ware installation (typically
C:\ti\c2000\C2000Ware_X_XX_XX_XX\device_support\f2838x\common\include).
Replace the ’X’s with your current C2000Ware version installation. Click ok to add this path,
and repeat this same process to add the headers\include directory and the driverlib
directory

Figure 2.3: Project configuration dialog box

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 Getting Started and Troubleshooting

4. Expand the Advanced Options and look for the Predefined Symbol entry. Add a Pre-define
NAME called "CPU1". This ensures that the header files build correct for this CPU.

Figure 2.4: Project configuration dialog box

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Getting Started and Troubleshooting

5. Click on the Linker File Search Path. Add these directories to the search path: common\cmd
and headers\cmd. Then you’ll also want to add the lib and linker command files

Figure 2.5: Project configuration dialog box

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 Getting Started and Troubleshooting

6. While you have this window open select the Symbol Management options under C2000 Linker
Advanced Options. Specify the program entry point to be code_start. Select ok to close
out of the Build Properties.

Figure 2.6: Symbol Management options

Sun Apr 7 02:08:58 IST 2024 21

Getting Started and Troubleshooting

7. In the project explorer, check that no linker command file got added during project setup. If so,
remove the linker command file that got added.
8. Next we need to link in a few files which are used by the header files. To do this right click on
your project in the workspace and select Add Files...
At this point your project workspace should look like the following:

Figure 2.7: Linking files to project

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 Getting Started and Troubleshooting

9. Create a new file by right clicking on the project and selecting New -> File. Name this file
main.c and copy the following code into it:
#include "device.h"
#include "driverlib.h"

void main(void)
{
uint32_t delay;

Device_init();

//
// Configure the LED pins
//
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD);

GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED2, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED2, GPIO_PIN_TYPE_STD);

//
// Set master core for LED2
//
GPIO_setMasterCore(DEVICE_GPIO_PIN_LED2, GPIO_CORE_CPU2);

//
// Send IPC flag to CPU2
//
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAGDEVICE_GPIO_PIN_LED1);

while(1)
{
//
// Toggle LED1
//
GPIO_togglePin(DEVICE_GPIO_PIN_LED1);

//
// Delay for a bit
//
for(delay = 0; delay < 2000000; delay++)
{
}
}
}
10. Save main.c, update it with the content needed and then attempt to build the project by right
click on it and selecting Build Project. Assuming the project builds try debugging this project
on a f2838x device. When the code runs you should see LED1 toggle.

Sun Apr 7 02:08:58 IST 2024 23

Getting Started and Troubleshooting

Figure 2.8: Create a new file

24 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

CPU 2 Subsystem Project Creation

1. From the main CCS window select File -> New -> CCS Project. Select your Target as
"TMS320F28388D" and use the "C28XX [C2000]" Tab. Name your project and choose a
location for it to reside. Click Finish and your project will be created.

Figure 2.9: Creating a new C28 project

Sun Apr 7 02:08:58 IST 2024 25

Getting Started and Troubleshooting

2. Before we can successfully build a project we need to setup some build specific settings. Right
click on your project and select Properties. Look at the Processor Options and ensure they
match the below image:

Figure 2.10: Project configuration dialog box

26 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

3. In the C2000 Compiler entry look for and select the Include Options. Click on the
add directory icon to add a directory to the search path. Click the File System but-
ton to browse to the common\include folder of your C2000Ware installation (typically
C:\ti\c2000\C2000Ware_X_XX_XX_XX\device_support\f2838x\common\include).
Replace the ’X’s with your current C2000Ware version installation. Click ok to add this path,
and repeat this same process to add the headers\include directory and the driverlib
directory

Figure 2.11: Project configuration dialog box

Sun Apr 7 02:08:58 IST 2024 27

Getting Started and Troubleshooting

4. Expand the Advanced Options and look for the Predefined Symbol entry. Add a Pre-define
NAME called "CPU2". This ensures that the header files build correct for this CPU.

Figure 2.12: Project configuration dialog box

28 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

5. Click on the Linker File Search Path. Add these directories to the search path: common\cmd
and headers\cmd. Then you’ll also want to add the lib and linker command files

Figure 2.13: Project configuration dialog box

Sun Apr 7 02:08:58 IST 2024 29

Getting Started and Troubleshooting

6. While you have this window open select the Symbol Management options under C2000 Linker
Advanced Options. Specify the program entry point to be code_start. Select ok to close
out of the Build Properties.

Figure 2.14: Symbol Management options

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 Getting Started and Troubleshooting

7. In the project explorer, check that no linker command file got added during project setup. If so,
remove the linker command file that got added.
8. Next we need to link in a few files which are used by the header files. To do this right click on
your project in the workspace and select Add Files...
At this point your project workspace should look like the following:

Figure 2.15: Linking files to project

Sun Apr 7 02:08:58 IST 2024 31

Getting Started and Troubleshooting

9. Create a new file by right clicking on the project and selecting New -> File. Name this file
main.c and copy the following code into it:
#include "device.h"
#include "driverlib.h"

void main(void)
{
uint32_t delay;

//
// Wait for IPC flag for CPU1
//
IPC_waitForFlag(IPC_CPU1_L_CPU2_R, IPC_FLAG31);

while(1)
{
//
// Toggle LED2
//
GPIO_togglePin(DEVICE_GPIO_PIN_LED2);

//
// Delay for a bit
//
for(delay = 0; delay < 2000000; delay++)
{
}
}
}
10. Save main.c,update it with the content needed and then attempt to build the project by right
click on it and selecting Build Project. Assuming the project builds try debugging both these
projects simultaneously on a f2838x device, otherwise carefully examine the error and the
above steps to determine what could have gone wrong. When the code runs you should see
LED2 toggle.

32 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

Figure 2.16: Create a new file

Sun Apr 7 02:08:58 IST 2024 33

Getting Started and Troubleshooting

CM Subsystem Project Creation

1. From the main CCS window select File -> New -> CCS Project. Select your Target as
"TMS320F28388D" and use the "Cortex M [ARM]" Tab. Name your project and choose a
location for it to reside. Click Finish and your project will be created.

Figure 2.17: Creating a new CM project

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 Getting Started and Troubleshooting

2. Before we can successfully build a project we need to setup some build specific settings. Right
click on your project and select Properties. Look at the Processor Options and ensure they
match the below image:

Figure 2.18: Project configuration dialog box

Sun Apr 7 02:08:58 IST 2024 35

Getting Started and Troubleshooting

3. In the C2000 Compiler entry look for and select the Include Options. Click on the
add directory icon to add a directory to the search path. Click the File System but-
ton to browse to the common\include folder of your C2000Ware installation (typically
C:\ti\c2000\C2000Ware_X_XX_XX_XX\device_support\f2838x\common\include).
Replace the ’X’s with your current C2000Ware version installation. Click ok to add this path,
and repeat this same process to add the driverlib directory.

Figure 2.19: Project configuration dialog box

36 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

Figure 2.20: Project configuration dialog box

Sun Apr 7 02:08:58 IST 2024 37

Getting Started and Troubleshooting

4. In the project explorer, check that no linker command file got added during project setup. If so,
remove the linker command file that got added.
5. Next we need to link in a few files which are used by the header files. To do this right click on
your project in the workspace and select Add Files...
At this point your project workspace should look like the following:

Figure 2.21: Linking files to project

38 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

6. Create a new file by right clicking on the project and selecting New -> File. Name this file
main.c.
7. Save main.c, update it with the content needed and then attempt to build the project by right
click on it and selecting Build Project. Assuming the project builds try debugging both these
projects simultaneously on a f2838x device, otherwise carefully examine the error and the
above steps to determine what could have gone wrong.

Figure 2.22: Create a new file

2.3 Debugging Dual Core Applications

1. Ensure CCS version 10.1 or newer is installed and up to date. You should have C2000 Code
Generation Tools version 20.2.1.LTS and TI ARM Compiler 20.2.1.LTS.
2. Connect a USB Mini cable from the computer to the USB port on the left hand side of the
controlCARD. Windows will enumerate and try to install drivers. As long as CCS is installed,
Windows should automatically find and install drivers for the emulator.
3. Apply power either via USB or the 5V DC in jack on the docking station. While the emulator
on the board is powered from the host computer’s USB port, the rest of the board is not.
The reason for this is that the JTAG connection on the F2838x controlCARDs is completely
electrically isolated. Because of the typical applications these devices will be used in, it is
neccessary to isolate the JTAG connection. However, for bench debug and evaluation (with
low voltages), both halves of the board can be powered from the same supply (i.e. USB). Each
power domain has an associated power LED which can be used to ensure that each domain
has power.
4. Launch CCS and pick the workspace you would like to debug in.
5. Create a new target configuration. Click File -> New -> Target Configuration File and name
the file appropriately (i.e. F2838x_xds100.ccxml). Select the emulator you intend to use
(XDS100v2) from the drop down list, and then select the device variant present on your board
(f2838x controlCARDs have a f2838xD). Save the target configuration and close the window.

Sun Apr 7 02:08:58 IST 2024 39

Getting Started and Troubleshooting

Figure 2.23: F2838x Card Target Configuration Setup

6. Import the desired example projects (or skip this step if you are using projects you created
in the Project Creation section). Click File -> Import, and in the CCS folder select Existing
CCS/CCE Eclipse Projects before clicking Next. With the "Select search-directory" radio but-
ton checked, browse to the root of your C2000Ware installation. Device specific software as
well as examples are stored in the driverlib/device_variant folders. Navigate to the
F2838x directory, and then to the examples/c28x directory. Click OK and CCS will parse
all of the projects in this directory. Import any projects you wish to run into the workspace.

40 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

Figure 2.24: Importing f2838x Projects

7. Build each of the example projects. Right click on each project title and select build project.

Figure 2.25: Building f2838x Projects

8. Launch the previously created target configuration. Click View -> Target Configurations. In
the window that opens, find the target configuration you created previously, right click on it and
select "Launch Target Configuration".

Sun Apr 7 02:08:58 IST 2024 41

Getting Started and Troubleshooting

Figure 2.26: Launching a CCS Target Configuration

9. Connect to the device. Right click on each core in the debug window and select "Connect
Target. This will connect CCS to the device and will allow you to load code and debug appli-
cations.

Figure 2.27: Connecting to a Target

Figure 2.28: After connection to both cores

10. Load code on each of the cores. Select one of the cores in the debug window and then click
Target -> Load Program. A dialog box is display which will allow you to select a program
to load. Be careful to ensure that you load the appropriate out file on the appropriate core.
Repeat this process for the other core by selecting it and following these same steps.

42 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

11. At this point both cores should have code loaded and be halted at main. From this point, users
should be able to debug code just as they are used to with CCS. Please keep in mind that any
action you take in CCS only has an effect on the core you currently have selected in the debug
window. For instance if CPU 1 is selected, the memory window will display the memory map
of of the system as seen by CPU 1. The opposite would be true if CPU 2 were selected and
similarly for CM.

Figure 2.29: Projects loaded on each core

STARTC 2000W AREO N LY

2.4 Project: Adding Bit-field or DriverLib Support

F2838x devices support two types of development software, driver library APIs and bit-field structures. Each
have their advantages and are implemented to be compatible together within the same user application. This
section details how to add driverlib support to a bit-field project as well as how to add bit-field support to a
driverlib project.
When combining bit-field and driverlib support, add a pre-defined symbol within the project properties called
"_DUAL_HEADERS". This is required to avoid having conflicting definitions (in enums/structs/macros) which
share the exact same names in both bit-field and driverlib headers.
Adding DriverLib Support

1. Add the following include directory path to the project:

driverlib\f2838x\driverlib
2. Include the following header file in the project main source file:
device_support\f2838x\common\include\driverlib.h
3. Add or link the driverlib.lib library to the project. Location of file:
driverlib\f2838x\driverlib\ccs\Debug

Adding Bit-field Support

1. Add the following include directory path to the project:

device_support\f2838x\headers\include
2. Include the following header file in the project main source file:
device_support\f2838x\headers\include\f2838x_device.h

Sun Apr 7 02:08:58 IST 2024 43

 Getting Started and Troubleshooting

3. Add or link the f2838x_globalvariabledefs.c file to the project. Location of file:

device_support\f2838x\headers\source
4. Add or link the f2838x_Headers_nonBIOS.cmd file to the project. Location of file:
device_support\f2838x\headers\cmd

ENDC 2000W AREO N LY

2.5 Troubleshooting
There are a number of things that can cause the user trouble while bringing up a debug session the first time.
This section will try to provide solutions to the most common problems encountered with the Delfino devices.
"I get a managed make error when I import the example projects"
This occurs when one imports a project for which he or she doesn’t have the code generation tools for.
Please ensure that you have at least C2000 Code Generation Tools version 18.9.0.STS and TI ARM Com-
piler 18.1.3.LTS or later.
"I cannot build the example projects"
This is caused by linked resources not being where the project expects them to be. For instance, if you imported
the projects and selected "Copy projects to workspace", the projects would no longer build because the files
they reference aren’t a part of your workspace. Always build and run the examples directly in the C2000Ware
directory tree.
"My F2838x device isn’t in the target configuration selection list"
The list of available device for debug is determined based on a number of factors, including drivers and tools
chains available on the host system. If you system has previously been used only for development on previous
C2000 devices, you may not have the required CCS device files. In CCS click on "Help, Check for updates" and
follow the dialog boxes to update your CCS installation.
"I cannot connect to the target"
This is most often times caused by either a bad target configuration, or simply the emulator being physically
disconnected. If you are unable to connect to a target check the following things:

1. Ensure the target configuration is correct for the device you have.
2. Ensure the emulator is plugged in to both the computer and the device to be debugged.
3. Ensure that the target device is powered.

"I cannot load code"

This is typically caused by an error in the GEL script or improperly linked code. If you are having trouble loading
code, check the linker command files and maps to ensure that they match the device memory map. If these
appear correct, there is a chance there is something wrong in one of your GEL scripts.
"When a core gets an interrupt, it faults"
Ensure that the interrupt vector table is where the interrupt controller thinks it is. On both cores the interrupt
vector table may be mapped to either RAM or flash. Please ensure that your vector table is where the interrupt
controller thinks it is.
"When the CPU1 comes up, it is not fresh out of reset"
F2838x devices support several boot modes, several of which allow program code to be loaded into and exe-
cuted out of RAM via one of the device many serial peripherals. If the boot mode pins are in the wrong state at

44 Sun Apr 7 02:08:58 IST 2024

 Getting Started and Troubleshooting

power up, one of these peripheral boot modes may be entered accidentally before the debugger is connected.
This leaves the chip in an unclean state with potentially several of the peripherals configured as well as the
interrupt vector table setup. If you are seeing strange behavior check to ensure that the "Boot to Flash" or "Boot
to RAM" boot mode is selected.
"\"Fapi_Error_InvalidHclkValue\" is returned afte execution of Fapi_setActiveFlashBank(Fapi_FlashBank0)
function." Occurs when using the Flash APIs in the code.
Please ensure that the correct frequency is passed as an input to the Fapi_initializeAPI function and the wait
states are correctly configured.

Sun Apr 7 02:08:58 IST 2024 45

Getting Started and Troubleshooting

46 Sun Apr 7 02:08:58 IST 2024

 Interrupt Service Routine Priorities

3 Interrupt Service Routine Priorities

Interrupt Hardware Priority Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
f2838x PIE Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Software Prioritization of Interrupts - The Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.1 Interrupt Hardware Priority Overview

With the PIE block enabled, the interrupts are prioritized in hardware by default as follows:
Global Priority (CPU Interrupt level):

CPU Interrupt Hardware Priority

Reset 1(Highest)
INT1 5
INT2 6
INT3 7
INT4 8
INT5 9
INT6 10
INT7 11
... ...
INT12 16
INT13 17
INT14 18
DLOGINT 19(Lowest)
RTOSINT 20
reserved 2
NMI 3
ILLEGAL -
USER1 -(Software Interrupts)
USER2 -
... ...

CPU Interrupts INT1 - INT14, DLOGINT and RTOSINT are maskable interrupts. These interrupts can be
enabled or disabled by the CPU Interrupt enable register (IER).
Group Priority (PIE Level):
If the Peripheral Interrupt Expansion (PIE) block is enabled, then CPU interrupts INT1 to INT12 are connected
to the PIE. This peripheral expands each of these 12 CPU interrupt into 8 interrupts. Thus the total possible
number of available interrupts in the PIE is 96. Note, not all of the 96 are used on a 2803x device.
Each of the PIE groups has its own interrupt enable register (PIEIERx) to control which of the 8 interrupts
(INTx.1 - INTx.8) are enabled and permitted to issue an interrupt.

Sun Apr 7 02:08:58 IST 2024 47

 Interrupt Service Routine Priorities

CPU PIE
Interrupt Group PIE Interrupts
Highest————–Hardware Priority Within the Group—————-Lowest
INT1 1 INT1.1 INT1.2 INT1.3 INT1.4 INT1.5 INT1.6 INT1.7 INT1.8
INT2 2 INT2.1 INT2.2 INT2.3 INT2.4 INT2.5 INT2.6 INT2.7 INT2.8
INT3 3 INT3.1 INT3.2 INT3.3 INT3.4 INT3.5 INT3.6 INT3.7 INT3.8
... etc ...
... etc ...
INT12 12 INT12.1 INT12.2 INT12.3 INT12.4 INT12.5 INT12.6 INT12.7 INT4.8

Table 3.1: PIE Group Hardware Priority

3.2 PIE Interrupt Priorities

The PIE block is organized such that the interrupts are in a logical order. Interrupts that typically require higher
priority, are organized higher up in the table and will thus be serviced with a higher priority by default.
The interrupts in a control subsystem can be categorized as follows (ordered highest to lowest priority):

1. Non-Periodic, Fast Response

These are interrupts that can happen at any time and when they occur, they must be serviced
as quickly as possible. Typically these interrupts monitor an external event.

On the f2838x devices, such interrupts are allocated to the first few interrupts within PIE
Group 1 and PIE Group 2. This position gives them the highest priority within the PIE group.
In addition, Group 1 is multiplexed into the CPU interrupt INT1. CPU INT1 has the highest
hardware priority. PIE Group 2 is multiplexed into the CPU INT2 which is the 2nd highest
hardware priority.

2. Periodic, Fast Response

These interrupts occur at a known period, and when they do occur, they must be serviced as
quickly as possible to minimize latency. The A/D converter is one good example of this. The
A/D sample must be processed with minimum latency.

On the f2838x devices, such interrupts are allocated to the group 1 in the PIE table. Group 1
is multiplexed into the CPU INT1. CPU INT1 has the highest hardware priority

3. Periodic
These interrupts occur at a known period and must be serviced before the next interrupt.
Some of the PWM interrupts are an example of this. Many of the registers are shadowed, so
the user has the full period to update the register values.

In the f2838x device’s PIE modules, such interrupts are mapped to group 2 - group 5. These
groups are multiplexed into CPU INT3 to INT5 (the ePWM and eCAP), which are the next
lowest hardware priority.

4. Periodic, Buffered
These interrupts occur at periodic events, but are buffered and hence the processor need
only service such interrupts when the buffers are ready to filled/emptied. All of the serial ports
(SCI / SPI / I2C / CAN) either have FIFOs or multiple mailboxes such that the CPU has plenty

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 Interrupt Service Routine Priorities

of time to respond to the events without fear of losing data.

In the f2838x device, such interrupts are mapped to INT6, INT8, and INT9, which are the next
lowest hardware priority.

3.3 Software Prioritization of Interrupts

The user will probably find that the PIE interrupts are organized where they should be for most applications.
However, some software prioritization may still be required for some applications.
Recall that the basic software priority scheme on the C28x works as follows:

Global Priority
This priority can be managed by manipulating the CPU IER register. This register controls the
16 maskable CPU interrupts (INT1 - INT16).

Group Priority
This can be managed by manipulating the PIE block interrupt enable registers (PIEIERx).
There is one PIEIERx per group and each control the 8-interrupts multiplexed within that group.

The F28 software prioritization of interrupt example demonstrates how to configure the Global priority (via IER)
and group priority (via PIEIERx) within an ISR in order to change the interrupt service priority based on user
assigned levels. The steps required to do this are:

1. Set the global priority

Modify the IER register to allow CPU interrupts with a higher user priority to be serviced.

2. Set the Group priority

Modify the appropriate PIEIERx register to allow group interrupts with a higher user set priority
to be serviced.

3. Enable interrupts

The software prioritized interrupts example provides a method using mask values that are configured during
compile time to allow you to manage this easily.
To setup software prioritization for the example, the user must first assign the desired global priority levels and
group priority levels.
This can be done as follows:

1. User assigns global priority levels

INT1PL - INT16PL
These values are used to assign a priority level to each of the 16 interrupts controlled by the
CPU IER register. A value of 1 is the highest priority while a value of 16 is the lowest. More
then one interrupt can be assigned the same priority level. In this case the default hardware
priority would determine which would be serviced first. A priority of 0 is used to indicate that
the interrupt is not used.

Sun Apr 7 02:08:58 IST 2024 49

 Interrupt Service Routine Priorities

2. User assigns PIE group priority levels

GxyPL (where x = PIE group number 1 - 12 and y = interrupt number 1 - 8)

These values are used to assign a priority level to each of the 8 interrupts within a PIE group.
A value of 1 is the highest priority while a value of 8 is the lowest. More then one interrupt can
be assigned the same priority level. In this case the default hardware priority would determine
which would be serviced first. A priority of 0 is used to indicate that the interrupt is not used.

Once the user has defined the global and group priority levels, the compiler will generate mask values that
can be used to change the IER and PIEIERx registers within each ISR. In this manner the interrupt software
prioritization will be changed. The masks that are generated at compile time are:

IER mask values

MINT1 - MINT16

The user assigned INT1PL - INT16PL values are used at compile time to calculate an IER
mask for each CPU interrupt. This mask value will be used within an ISR to allow CPU inter-
rupts with a higher priority to interrupt the current ISR and thus be serviced at a higher priority
level.
PIEIERxy mask values
MGxy (where x = PIE group number 1 - 12 and y = interrupt number 1 - 8)

The assigned group priority levels (GxyPL) are used at compile time to calculate PIEIERx
masks for each PIE group. This mask value will be used within an ISR to allow interrupts
within the same group that have a higher assigned priority to interrupt the current ISR and
thus be serviced at a higher priority level.

3.3.1 Using the IER/PIEIER Mask Values

Within an interrupt service routine, the global and group priority can be changed by software to allow other
interrupts to be serviced. The procedure for setting an interrupt priority using the mask values created in the
F28_SWPrioritizedIsrLevels.h is the following:

1. Set the global priority

Modify IER to allow CPU interrupts from the same PIE group as the current ISR.
Modify IER to allow CPU interrupts with a higher user defined priority to be serviced.
2. Set the group priority
Save the current PIEIERx value to a temporary register.
The PIEIER register is then set to allow interrupts with a higher priority within a PIE group
to be serviced.
3. Enable interrupts
Enable all PIE interrupt groups by writing all 1’s to the PIEACK register
Enable global interrupts by clearing INTM
4. Execute ISR. Interrupts that were enabled in steps 1-3 (those with a higher software priority)
will be allowed to interrupt the current ISR and thus be serviced first.
5. Restore the PIEIERx register
6. Exit

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 Interrupt Service Routine Priorities

3.3.2 Example Code

The sample C code below shows an EV-A Comparator 1 Interrupt service routine software prioritization written
in C. This interrupt is connected to PIE group 2 interrupt 1.

// Connected to PIEIER2_1 (use MINT2 and MG21 masks):

#if (G21PL != 0)
interrupt void EPWM1_TZINT_ISR(void) // EPWM1 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG21; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
asm(" NOP");
EINT;

// Insert ISR Code here.......

// for now just insert a delay
for(i = 1; i <= 10; i++) {}

// Restore registers saved:

DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;

// Add ISR to Trace

ISRTrace[ISRTraceIndex] = 0x0021;
ISRTraceIndex++;
}
#endif

CMP1INT_ISR:
ASP
ADDB SP,#1
CLRC OVM,PAGE0
MOVW DP,#0x0033
MOV AL,@36
MOV *-SP[1],AL
OR IER,#0x0002
AND IER,#0x0002
AND @36,#0x000E
MOV @33,#0xFFFF
CLRC INTM

User code goes here...

SETC INTM
MOV AL,*-SP[1]
MOV @36,AL
SUBB SP,#1

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Interrupt Service Routine Priorities

NASP
IRET

The interrupt latency is approx 22 cycles.

/∗!

52 Sun Apr 7 02:08:58 IST 2024

 CPU 1 Bit-field Example Applications

4 CPU 1 Bit-field Example Applications

These example applications show how to make use of various peripherals of a F2838x device. These applica-
tions are intended for demonstration and as a starting point for new applications.
All these examples contain two build configurations which allow you to build each project to run from either RAM
or Flash. To change how the project is built simply right click on the project and select "Build Configurations".
Then, move over to set the active build configuration, either RAM or Flash.
The examples provided are built for controlCARD compatibility.
Because CPU 1 is ultimately in control of the entire F2838x device and these applications contain no CPU 2
dependencies, these examples may be run completely on their own without any associated CPU2 program.
All of these examples reside in the device_support/F2838x/examples/cpu1 subdirectory of the
C2000Ware package.

4.1 ADC SOC Software Force (adc_soc_software)

This example converts some voltages on ADCA and ADCB based on a software trigger.
After the program runs, the memory will contain:

AdcaResult0 : a digital representation of the voltage on pin A2

AdcaResult1 : a digital representation of the voltage on pin A3
AdcbResult0 : a digital representation of the voltage on pin B2
AdcbResult1 : a digital representation of the voltage on pin B3

Note: The software triggers for the two ADCs happen sequentially, so the two ADCs will run asynchronously.

4.2 ADC ePWM Triggering (adc_soc_epwm)

This example sets up the ePWM to periodically trigger the ADC.
After the program runs, the memory will contain:

AdcaResults : A sequence of analog-to-digital conversion samples from pin A0. The time
between samples is determined based on the period of the ePWM timer.

4.3 ADC temperature sensor conversion (adc_soc_epwm_tempsensor)

This example sets up the ePWM to periodically trigger the ADC. The ADC converts the internal connection to
the temperature sensor, which is then interpreted as a temperature by calling the GetTemperatureC function.
After the program runs, the memory will contain:

sensorSample : The raw reading from the temperature sensor.

sensorTemp : The interpretation of the sensor sample as a temperature in degrees Celsius.

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 CPU 1 Bit-field Example Applications

4.4 ADC Synchronous SOC Software Force

(adc_soc_software_sync)
This example converts some voltages on ADCA and ADCB using input 5 of the input X-BAR as a software force.
Input 5 is triggered by toggling GPIO0, but any spare GPIO could be used. This method will ensure that both
ADCs start converting at exactly the same time.
After the program runs, the memory will contain:

AdcaResult0 : a digital representation of the voltage on pin A2

AdcaResult1 : a digital representation of the voltage on pin A3
AdcbResult0 : a digital representation of the voltage on pin B2
AdcbResult1 : a digital representation of the voltage on pin B3

4.5 ADC Continuous Triggering (adc_soc_continuous)

This example sets up the ADC to convert continuously, achieving maximum sampling rate.
After the program runs, the memory will contain:

AdcaResults : A sequence of analog-to-digital conversion samples from pin A0. The time
between samples is the minimum possible based on the ADC speed.

4.6 ADC Continuous Conversions Read by DMA

(adc_soc_continuous_dma)
This example sets up two ADC channels to convert simultaneously. The results will be transferred by the DMA
into a buffer in RAM.
After the program runs, the memory will contain:

adcData0 : a digital representation of the voltage on pin A3

adcData1 : a digital representation of the voltage on pin B3

4.7 ADC PPB Offset (adc_ppb_offset)

This example software triggers the ADC. Some SOCs have automatic offset adjustment applied by the post-
processing block.
After the program runs, the memory will contain:

AdcaResult : a digital representation of the voltage on pin A0

AdcaResult_offsetAdjusted : a digital representation of the voltage on pin A0, minus 100
LSBs of automatically added offset

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 CPU 1 Bit-field Example Applications

AdcbResult : a digital representation of the voltage on pin B0

AdcbResult_offsetAdjusted : a digital representation of the voltage on pin B0 plus 100 LSBs
of automatically added offset

4.8 ADC PPB Limits (adc_ppb_limits)

This example sets up the ePWM to periodically trigger the ADC. If the results are outside of the defined range,
the post-processing block will generate an interrupt.
The default limits are 1000LSBs and 3000LSBs. With VREFHI set to 3.3V, the PPB will generate an interrupt if
the input voltage goes above about 2.4V or below about 0.8V.

4.9 ADC PPB Delay Capture (adc_ppb_delay)

This example demonstrates delay capture using the post-processing block.
Two asynchronous ADC triggers are setup:

ePWM1, with period 2048, triggering SOC0 to convert on pin A0

ePWM1, with period 9999, triggering SOC1 to convert on pin A1

Each conversion generates an ISR at the end of the conversion. In the ISR for SOC0, a conversion counter is
incremented and the PPB is checked to determine if the sample was delayed.
After the program runs, the memory will contain:

conversion : the sequence of conversions using SOC0 that were delayed

delay : the corresponding delay of each of the delayed conversions

4.10 CLA arcsine(x) using a lookup table (cla_asin_cpu01)

In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Memory Allocation

CLA1 Math Tables (RAMLS0)

• CLAasinTable - Lookup table
CLA1 to CPU Message RAM
• fResult - Result of the lookup algorithm
CPU to CLA1 Message RAM
• fVal - Sample input to the lookup algorithm

Watch Variables

fVal - Argument to task 1

fResult - Result of arcsin(f V al)

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 CPU 1 Bit-field Example Applications

4.11 CLA arctangent(x) using a lookup table (cla_atan_cpu01)

In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.
Memory Allocation

CLA1 Math Tables (RAMLS0)

• CLAatan2Table - Lookup table
CLA1 to CPU Message RAM
• fResult - Result of the lookup algorithm
CPU to CLA1 Message RAM
• fNum - Numerator of sample input
• fDen - Denominator of sample input

Watch Variables

fVal - Argument to task 1

fResult - Result of arctan(f V al)

4.12 Buffered DAC Enable (buffdac_enable)

This example generates a voltage on the buffered DAC output, DACOUTA/ADCINA0 (HSEC Pin 9) and uses
the default DAC reference setting of VDAC.
When the DAC reference is set to VDAC, an external reference voltage must be applied to the VDAC pin. This
can accomplished by connecting a jumper wire from 3.3V to ADCINB0 (HSEC pin 12).

4.13 Buffered DAC Sine DMA (buffdac_sine_dma)

This example generates a sine wave on the buffered DAC output using the DMA to transfer sine values stored
in a sine table in GSRAM to DACVALS, DACOUTA/ADCINA0 (HSEC Pin 9) and uses the default DAC reference
setting of VDAC.
When the DAC reference is set to VDAC, an external reference voltage must be applied to the VDAC pin. This
can accomplished by connecting a jumper wire from 3.3V to ADCINB0 (HSEC pin 12).
Run the included .js file to add the watch variables.
outputFreq_hz = (samplingFreq_hz/SINE_TBL_SIZE)∗tableStep
The generated waveform can be adjusted with the following variables/macros but require recompile:

waveformGain : Adjust the magnitude of the waveform. Range is from 0.0 to 1.0. The default
value of 0.8003 centers the waveform within the linear range of the DAC.
waveformOffset : Adjust the offset of the waveform. Range is from -1.0 to 1.0. The default
value of 0 centers the waveform.
samplingFreq_hz : Adjust the rate at which the DAC is updated. Range - Bounded by cpu
timer maximum interrupt rate.

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 CPU 1 Bit-field Example Applications

tableStep : The sine table step size. Range - Bounded by sine table size, should be much
less than sine table size to have good resolution.
REFERENCE : The reference for the DAC. Range - REFERENCE_VDAC, REFER-
ENCE_VREF
CPUFREQ_MHZ : The cpu frequency. This does not set the cpu frequency. Range - See
device data manual
DAC_NUM : The DAC to use. Range - DACA, DACB, DACC

4.14 DMA GSRAM Transfer (dma_gsram_transfer)

This example uses one DMA channel to transfer data from a buffer in RAMGS0 to a buffer in RAMGS1. The
example sets the DMA channel PERINTFRC bit repeatedly until the transfer of 16 bursts (where each burst is 8
16-bit words) has been completed. When the whole transfer is complete, it will trigger the DMA interrupt.
Watch Variables

sdata - Data to send

rdata - Received data

4.15 ECAP APWM Example

This program sets up the eCAP pins in the APWM mode. This program runs at 200 MHz SYSCLK assuming a
20 MHz OSCCLK.
eCAP1 will come out on the GPIO5 pin This pin is configured to vary between frequencies using the shadow
registers to load the next period/compare values

4.16 EMIF ASYNC module (emif1_16bit_asram)

This example configures EMIF1 in 16bit ASYNC mode This example uses CS2 as chip enable.
Watch Variables:

TEST_STATUS - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
ErrCount - Error counter

4.17 EMIF1 SDRAM Module (emif1_16bit_sdram_far)

This example configures EMIF1 in 16bit SDRAM mode and uses CS0 (SDRAM) as chip enable. It will first write
to an array in the SDRAM and then read it back using the FPU function, memcpy_fast_far(), for both operations.
The buffer in SDRAM will be placed in the .farbss memory on account of the fact that its assigned the attribute
"far" indicating it lies beyond the 22-bit program address space. The compiler will take care to avoid using

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instructions such as PREAD, which uses the Program Read Bus, or addressing modes restricted to the lower
22-bit space when accessing data with the attribute "far"

Note:
The memory space beyond 22-bits must be treated as data space for load/store operations
only. The user is cautioned against using this space for either instructions or working memory.

Watch Variables:

TEST_STATUS - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
ErrCount - Error counter

4.18 EMIF1 SDRAM Module (emif1_16bit_sdram_dma)

This example configures EMIF1 in 16bit SDRAM mode and uses CS0 (SDRAM) as chip enable. It will first write
to an array in the SDRAM and then read it back using the DMA for both operations. The buffer in SDRAM will be
placed in the .farbss memory on account of the fact that its assigned the attribute "far" indicating it lies beyond
the 22-bit program address space. The compiler will take care to avoid using instructions such as PREAD,
which uses the Program Read Bus, or addressing modes restricted to the lower 22-bit space when accessing
data with the attribute "far"
Note:
The memory space beyond 22-bits must be treated as data space for load/store operations
only. The user is cautioned against using this space for either instructions or working memory.

Example has been tested using Micron 48LC32M16A2 "P -75 C" part.
Watch Variables:

TEST_STATUS - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
ErrCount - Error counter

4.19 EMIF1 SDRAM Module (emif1_32bit_sdram)

This example configures EMIF1 in 32bit SDRAM mode. This example uses CS0 (SDRAM) as chip enable.
Watch Variables:

TEST_STATUS - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
ErrCount - Error counter

4.20 EPWM Trip Zone Module (epwm_trip_zone)

This example configures ePWM1 and ePWM2 as follows

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ePWM1 has TZ1 as one shot trip source

ePWM2 has TZ1 as cycle by cycle trip source

Initially tie TZ1 high. During the test, monitor ePWM1 or ePWM2 outputs on a scope. Pull TZ1 low to see the
effect.
External Connections

EPWM1A is on GPIO0
EPWM2A is on GPIO2
TZ1 is on GPIO12

This example also makes use of the Input X-BAR. GPIO12 (the external trigger) is routed to the input X_BAR,
from which it is routed to TZ1.
The TZ-Event is defined such that EPWM1A will undergo a One-Shot Trip and EPWM2A will undergo a Cycle-
By-Cycle Trip.

4.21 EPWM Action Qualifier (epwm_updown_aq)

This example configures ePWM1, ePWM2, ePWM3 to produce an waveform with independent modulation on
EPWMxA and EPWMxB.
The compare values CMPA and CMPB are modified within the ePWM’s ISR.
The TB counter is in up/down count mode for this example.
View the EPWM1A/B(PA0_GPIO0 & PA1_GPIO1), EPWM2A/B(PA2_GPIO2 & PA3_GPIO3) and
EPWM3A/B(PA4_GPIO4 & PA5_GPIO5) waveforms via an oscilloscope.

4.22 EPWM Action Qualifier (epwm_up_aq)

This example configures ePWM1, ePWM2, ePWM3 to produce an waveform with independent modulation on
EPWMxA and EPWMxB.
The compare values CMPA and CMPB are modified within the ePWM’s ISR.
The TB counter is in up count mode for this example.
View the EPWM1A/B(PA0_GPIO0 & PA1_GPIO1), EPWM2A/B(PA2_GPIO2 & PA3_GPIO3) and
EPWM3A/B(PA4_GPIO4 & PA5_GPIO5) waveforms via an oscilloscope.

4.23 EPWM dead band control (epwm_deadband)

During the test, monitor ePWM1, ePWM2, and/or ePWM3 outputs on a scope.

ePWM1A is on GPIO0
ePWM1B is on GPIO1

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ePWM2A is on GPIO2
ePWM2B is on GPIO3
ePWM3A is on GPIO4
ePWM3B is on GPIO5

This example configures ePWM1, ePWM2 and ePWM3 for:

Count up/down
Deadband

3 Examples are included:

ePWM1: Active low PWMs

ePWM2: Active low complementary PWMs
ePWM3: Active high complementary PWMs

Each ePWM is configured to interrupt on the 3rd zero event. When this happens the deadband is modified such
that 0 <= DB <= DB_MAX. That is, the deadband will move up and down between 0 and the maximum value.
View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms via an oscilloscope

4.24 HRPWM Slider Test (hrpwm_slider)

This example modifies the MEP control registers to show edge displacement due to HRPWM control blocks of
the respective EPwm module channel A and B will have fine edge movement due to HRPWM logic. Load the
f2838x_hrpwm_slider.gel file. Select HRPWM FineDutySlider from the GEL menu. A FineDuty slider graphics
will show up in CCS. Load the program and run. Use the Slider to and observe the EPwm edge displacement
for each slider step change. This explains the MEP control on the EPwmxA channels.
Monitor ePWM1-ePWM8 A/B pins on an oscilloscope.

4.25 HRPWM Duty SFO (hrpwm_duty_sfo_v8)

This program requires the f2838x header files, which include the following files required for this example:
sfo_v8.h and SFO_v8_fpu_lib_build_c28_eabi.lib
Monitor ePWM1-ePWM8 A/B pins on an oscilloscope. DESCRIPTION:
This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up-Down count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)

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returns 1 when complete for the specified channel

returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
All ePWM1 -8 all channels will have fine edge movement due to the HRPWM logic
=======================================================================
NOTE: For more information on using the SFO software library, see the
f2838x High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
=======================================================================
To load and run this example:

1. ∗∗!!IMPORTANT!!∗∗
2. Run this example at maximum SYSCLKOUT
3. Activate Real time mode
4. Run the code
5. Watch ePWM A / B channel waveforms on a Oscilloscope
6. In the watch window: Set the variable UpdateFine = 1 to observe the ePWMxA & ePWMxB out-
put with HRPWM capabilities (default) Observe the period/frequency of the waveform changes
in fine MEP steps
7. In the watch window: Change the variable UpdateFine to 0, to observe the ePWMxA & eP-
WMxB output without HRPWM capabilities Observe the period/frequency of the waveform
changes in coarse SYSCLKOUT cycle steps.

4.26 HRPWM SFO Test (hrpwm_prdupdown_sfo_v8)

This program requires the f2838x header files, which include the following files required for this example:
sfo_v8.h and SFO_v8_fpu_lib_build_c28_eabi.lib
Monitor ePWM1-ePWM8 A/B pins on an oscilloscope. DESCRIPTION:
This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up-Down count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.

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All ePWM1-8 A/B channels will have fine edge movement due to the HRPWM logic
=======================================================================
NOTE: For more information on using the SFO software library, see the
f2838x High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
=======================================================================
To load and run this example:

1. ∗∗!!IMPORTANT!!∗∗
2. Run this example at maximum SYSCLKOUT
3. Activate Real time mode
4. Run the code
5. Watch ePWM A / B channel waveforms on an Oscilloscope
6. In the watch window: Set the variable UpdateFine = 1 to observe the ePWMxA & ePWMxB out-
put with HRPWM capabilities (default) Observe the period/frequency of the waveform changes
in fine MEP steps
7. In the watch window: Change the variable UpdateFine to 0, to observe the ePWMxA & eP-
WMxB output without HRPWM capabilities Observe the period/frequency of the waveform
changes in coarse SYSCLKOUT cycle steps.

4.27 HRPWM Dead-Band Example (hrpwm_deadband_sfo_v8)

This program requires the f2838x header files, including the following files required for this example: sfo_v8.h
and SFO_v8_fpu_lib_build_c28_eabi.lib
Monitor ePWM1 & ePWM2 A/B pins on an oscilloscope
DESCRIPTION:
This example sweeps the ePWM frequency while maintaining a duty cycle of ∼50% in ePWM up-down count
mode. In addition, this example demonstrates ePWM high-resolution dead-band (HRDB) capabilities utilizing
the HRPWM extension of the respective ePWM module.
This example calls the following TI’s micro-edge positioner (MEP) Scale Factor Optimizer (SFO) software library
V8 functions:
int SFO();
updates MEP_ScaleFactor dynamically when HRPWM is in use updates HRMSTEP register (exists only in
EPwm1Regs register space) which updates MEP_ScaleFactor value

returns 0 if not complete for the specified channel

returns 1 when complete for the specified channel
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)

This example is intended to demonstrate the HRPWM capability to control the dead-band falling edge delay
(FED) and rising edge delay (RED).
ePWM1 and ePWM2 A/B channels will have fine edge movement due to HRPWM control.

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=======================================================================
NOTE: For more information on using the SFO software library, see the f2838x High-
Resolution Pulse Width Modulator (HRPWM) Chapter in the Technical Reference Manual.
=======================================================================
To load and run this example:

1. ∗∗!!IMPORTANT!!∗∗
2. Run this example at maximum SYSCLKOUT
3. Activate Real time mode
4. Run the "AddWatchWindowVars_HRPWM.js" script from the scripting console (View -
> Scripting Console) to populate watch window by using the command: loadJSFile
<path_to_JS_file>/AddWatchWindowVars_HRPWM.js
5. Run the code
6. Watch ePWM A / B channel waveforms on an oscilloscope
7. In the watch window: Change the variable InputPeriodInc to increase or decrease the fre-
quency sweep rate. Setting InputPeriodInc = 0 will stop the sweep while allowing other vari-
ables to be manipulated and updated in real time.
8. In the watch window: Change values for registers EPwm1Regs.DBRED/EPwm2Regs.DBRED
to see changes in rising edge dead-bands for ePWM1 and ePWM2 respectively. Alternatively,
changing values for registers EPwm1Regs.DBFED/EPwm2Regs.DBFED will change falling
edge dead-bands for ePWM1 and ePWM2. Changing these values will alter the duty cycle
percentage for their respective ePWM modules. !!NOTE!!∗∗ - DBRED/DBFED values should
never be set below 4. Do not set these values to 0, 1, 2 or 3.
9. In the watch window: Change values for registers EPwm1Regs.DBREDHR.bit.DBREDHR/EPwm2Regs.DBR
to increase or decrease number of resolvable high-resolution steps
at the dead-band rising edge. Alternatively, change values for
EPwm1Regs.DBFEDHR.bit.DBFEDHR/EPwm2Regs.DBFEDHR.bit.DBFEDHR to change
the number of resolvable steps at the dead-band falling edge for ePWM1 and ePWM2
respectively.

4.28 External Interrupts (ExternalInterrupt)

This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO30 triggers XINT1 and GPIO31 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510∗SYSCLKOUT each.
GPIO34 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections

Connect GPIO30 to GPIO0. GPIO0 will be assigned to XINT1

Connect GPIO31 to GPIO1. GPIO1 will be assigned to XINT2

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Monitor GPIO34 with an oscilloscope. GPIO34 will be high outside of the ISRs and low within each ISR.
Watch Variables

Xint1Count for the number of times through XINT1 interrupt

Xint2Count for the number of times through XINT2 interrupt
LoopCount for the number of times through the idle loop

4.29 External Interrupts Latency (ExternalInterruptLatency)

This program triggers external interrupts when GPIO16 is pulled low. GPIO10 can be used to do this, or an
external signal generator can be connected. GPIO19 will toggle when the interrupt is entered. A global variable
(isrType) can be modified at run time to switch between C and assembly ISRs running out of RAM (0-wait state)
or flash (3-wait states).
Measured delays from GPIO16 falling to GPIO19 rising at SYSCLK=200 MHz:
ISR Delay Cycles
—————————
ASM/RAM 125ns 25
ASM/Flash 135ns 27
C/RAM 145ns 29
C/Flash 155ns 31
Some of the delay is due to the rise and fall times of the IOs. To see this, reduce SYSCLK to less than 75 MHz.
Under that condition, the ASM/RAM delay is 23 cycles, which is close to the theoretical minimum latency of 16
cycles.
The extra delay in the flash ISRs is due to the wait states. The extra delay in the C ISRs is due to two CLRC
instructions that are generated to make sure the address and overflow modes match the normal C environment.
With optimization enabled (-O1 and above), these instructions are removed.

4.30 SCI Echoback (sci_echoback)

This test receives and echo-backs data through the SCI-A port.
The PC application ’hyperterminal’ or another terminal such as ’putty’ can be used to view the data from the
SCI and to send information to the SCI. Characters received by the SCI port are sent back to the host.
Running the Application

1. Configure hyperterminal or another terminal such as putty:

For hyperterminal you can use the included hyperterminal configuration file SCI_96.ht. To load this configuration
in hyperterminal

1. Open hyperterminal
2. Go to file->open

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3. Browse to the location of the project and select the SCI_96.ht file.

Check the COM port. The configuration file is currently setup for COM1. If this is not correct, disconnect
(Call->Disconnect) Open the File-Properties dialogue and select the correct COM port.

1. Connect hyperterminal Call->Call and then start the 2838x SCI echoback program execution.
2. The program will print out a greeting and then ask you to enter a character which it will echo
back to hyperterminal.

Note:
If you are unable to open the .ht file, or you are using a different terminal, you can open a COM
port with the following settings
Find correct COM port
Bits per second = 9600
Date Bits = 8
Parity = None
Stop Bits = 1
Hardware Control = None

Watch Variables

LoopCount - the number of characters sent

External Connections
Connect the SCI-A port to a PC via a transceiver and cable.

GPIO28 is SCI_A-RXD (Connect to Pin3, PC-TX, of serial DB9 cable)

GPIO29 is SCI_A-TXD (Connect to Pin2, PC-RX, of serial DB9 cable)

4.31 SDFM Filter Sync CPU

In this example, SDFM filter data is read by CPU in SDFM ISR routine. The SDFM configuration is shown
below:

SDFM1 is used in this example. For using SDFM2, few modifications would be needed in the
example.

Input control mode selected - MODE0

Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected

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• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available.

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

Filter1_Result - Output of filter 1

Filter2_Result - Output of filter 2
Filter3_Result - Output of filter 3
Filter4_Result - Output of filter 4

4.32 SDFM Filter Sync CLA

In this example, SDFM filter data is read by CLA in Cla1Task1. The SDFM configuration is shown below:

SDFM1 used in this example.For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format

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• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

Filter1_Result - Output of filter 1

Filter2_Result - Output of filter 2
Filter3_Result - Output of filter 3
Filter4_Result - Output of filter 4

4.33 SDFM Filter Sync DMA

In this example, SDFM filter data is read by DMA. The SDFM configuration is shown below:

SDFM1 used in this example. For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter

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• All the 4 higher threshold comparator interrupts disabled

• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

Filter1_Result - Output of filter 1

Filter2_Result - Output of filter 2
Filter3_Result - Output of filter 3
Filter4_Result - Output of filter 4

4.34 SDFM PWM Sync

In this example, SDFM filter data is read by CPU in SDFM ISR routine. The SDFM configuration is shown
below:

SDFM1 is used in this example. For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)

Data filter settings

All the 4 filter modules enabled

Sinc3 filter selected
OSR = 256
All the 4 filters are synchronized by using PWM (Master Filter enable bit)
Filter output represented in 16 bit format
In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits for
Sinc3 filter with OSR = 256

Interrupt module settings for SDFM filter

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All the 4 higher threshold comparator interrupts disabled

All the 4 lower threshold comparator interrupts disabled
All the 4 modulator failure interrupts disabled
All the 4 filter will generate interrupt when a new filter data is available External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on

GPIO16-GPIO31

SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

Filter1_Result - Output of filter 1

Filter2_Result - Output of filter 2
Filter3_Result - Output of filter 3
Filter4_Result - Output of filter 4

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5 Dual Core Bit-field Example Applications

These example applications show how to make use of f2838x device functions which span both the CPU 1 and
CPU 2. All of these examples contain two example projects: one for CPU 1 and one for CPU 2.
Like the CPU1 only projects, these projects also contain different build configurations for RAM and Flash builds.
All of the projects contain RAM and Flash build configurations with debugger support.
The examples provided are built for controlCARD compatibility.
To run one of these examples after compiling it, load the appropriate programs on each of the two cores. Then,
for more example specific instructions please refer to the documentation regarding the example you wish to run
on the following pages or in the comments of the example sources.
All of these examples can be found in the
device_support/f2838x/examples/dual subdirectory of the C2000Ware package.

5.1 ADC & EPWM on CPU2

This example demonstrates how to make use of the ADC and EPWM peripherals from CPU2. Device clocking
(PLL) and GPIO setup are done using CPU1, while all other configuration of the peripherals is done using
CPU2.
CPU2 configures EPWM1 in up count mode in a similar fashion to what is done in the epwm_up_aq example.
The ADC is configured in continuous conversion mode similar to the adc_soc_continuous example. GPIO0 can
be connected to ADCINA0 and the results buffer AdcaResults graphed in CCS to view the duty cycle of the
generated waveform.

5.2 DMA Transfer Shared Peripheral

This example shows how to initiate a DMA transfer on CPU1 from a shared peripheral which is owned by CPU2.
In this specific example, a timer ISR is used on CPU2 to initiate a SPI transfer which will trigger the CPU1 DMA.
CPU1’s DMA will then in turn update the EPWM1 CMPA value for the PWM which it owns. The PWM output
can be observed on the GPIO pins configured in the InitEPwm1Gpio() function.
Watch Pins

GPIO0 and GPIO1 - ePWM output can be viewed with oscilloscope

5.3 Shared RAM management (CPU1)

This example shows how to assign shared RAM for use by both the CPU02 and CPU01 core. Shared RAM
regions are defined in both the CPU02 and CPU01 linker files. In this example GS0 and GS14 are assigned
to/owned by CPU02. The remaining shared RAM regions are owned by CPU01. In this example:
A pattern is written to c1_r_w_array and then IPC flag is sent to notify CPU02 that data is ready to be read.
CPU02 then reads the data from c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and compares with expected result.

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A Timed ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch GPIO31 and GPIO34 on oscilloscope. If using the control
card watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

c1_r_w_array[] is mapped to shared RAM GS1

c1_r_array[] is mapped to shared RAM GS0
c2_r_array[] is mapped to shared RAM GS1
c2_r_w_array[] is mapped to shared RAM GS0
cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34

Watch Variables

error Indicates that the data written is not correctly received by the other CPU.

5.4 Shared RAM management (CPU2)

This example shows how to assign shared RAM for use by both the CPU02 and CPU01 core. Shared RAM
regions are defined in both the CPU02 and CPU01 linker files. In this example GS0 and GS14 are assigned
to/owned by CPU02. The remaining shared RAM regions are owned by CPU01. In this example:
A pattern is written to c1_r_w_array and then IPC flag is sent to notify CPU02 that data is ready to be read.
CPU02 then reads the data from c2_r_array and writes a modified pattern to c2_r_w_array. Once CPU02
acknowledges the IPC flag to , CPU01 reads the data from c1_r_array and compares with expected result.
A Timed ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch GPIO31 and GPIO34 on oscilloscope. If using the control
card watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

c1_r_w_array[] is mapped to shared RAM GS1

c1_r_array[] is mapped to shared RAM GS0
c2_r_array[] is mapped to shared RAM GS1
c2_r_w_array[] is mapped to shared RAM GS0
cpu_timer0_isr in CPU02 is copied to shared RAM GS14 , toggles GPIO31
cpu_timer0_isr in CPU01 is copied to shared RAM GS15 , toggles GPIO34

Watch Variables

error Indicates that the data written is not correctly received by the other CPU.

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 Dual Core Bit-field Example Applications

5.5 SDFM Filter Sync CLA

In this example, SDFM1 filter data is read by CPU1 CLA in Cla1Task1 and SDFM2 filter data is read by CPU2
CLA in CLA1Task2. SDFM1 & SDFM2 instances can be assigned to either CPU1 or CPU2. The SDFM
configuration is shown below:

SDFM1 is used for CPU1 and SDFM2 is used for CPU2 for demonstration
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-

C8) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-
C8) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-
C8) on GPIO122-GPIO137

Watch Variables

Filter1_Result_CPU1 - Output of filter 1

Filter2_Result_CPU1 - Output of filter 2
Filter3_Result_CPU1 - Output of filter 3
Filter4_Result_CPU1 - Output of filter 4

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5.6 SDFM Filter Sync CLA

In this example, SDFM1 filter data is read by CPU1 CLA in Cla1Task1 and SDFM2 filter data is read by CPU2
CLA in CLA1Task2. SDFM1 & SDFM2 instances can be assigned to either CPU1 or CPU2. The SDFM
configuration is shown below:

SDFM1 is used for CPU1 and SDFM2 is used for CPU2 for demonstration
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-

C8) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-
C8) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SD-D1, SD-C1 to SD-D8,SD-
C8) on GPIO122-GPIO137

Watch Variables

Filter1_Result_CPU2 - Output of filter 1

Filter2_Result_CPU2 - Output of filter 2
Filter3_Result_CPU2 - Output of filter 3
Filter4_Result_CPU2 - Output of filter 4

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 C28x Driver Library Example Applications

6 C28x Driver Library Example Applications

These example applications show how to make use of various peripherals of a F2838x device. These applica-
tions are intended for demonstration and as a starting point for new applications.
All these examples are setup using the Code Composer Studio (CCS) "projectspec" format. Upon importing
the "projectspec", the example project will be generated in the CCS workspace with copies of the source and
header files included.
All these examples contain two build configurations which allow you to build each project to run from either RAM
or Flash. To change how the project is built simply right click on the project and select "Build Configurations".
Then, move over to set the active build configuration, either RAM or Flash.
The examples provided are built for controlCARD compatibility.
There may be a few examples which need either an external hardware or device not present on the controlCARD
like:

I2C communication with eeprom

SPI communication with eeprom
EMIF accessing external memory
DCC clock failure detection

Because CPU 1 is ultimately in control of the entire F2838x device and these applications contain no CPU 2
or CM dependencies, these examples may be run completely on their own without any associated CPU2 or
CM program. The only exception to this in the CPU1 examples is the cm_common_config_c28x example. This
example sets up all of the peripherals and GPIOs to be owned by CM.
All of these examples reside in the driverlib/f2838x/examples/c28x subdirectory of the C2000Ware
package.
Note that in all the examples, Device_init function assumes that the XTAL frequency is 25MHz. If a 20MHz
XTAL is used, please add a predefined symbol "USE_20MHZ_XTAL" in your CCS project. If a different XTAL
is used, you need to update the macro DEVICE_SETCLOCK_CFG in device.h file accordingly. Note that the
latest F2838x controlCARDs (Rev.B and later) have been updated to use 25MHz XTAL by default. If you have
an older 20MHz XTAL controlCARD (E1, E2, or Rev.A), refer to the controlCARD documentation on steps to
reconfigure the controlCARD from 20MHz to 25MHz.

6.1 ADC ePWM Triggering Multiple SOC

This example sets up ePWM1 to periodically trigger a set of conversions on ADCA and ADCC. This example
demonstrates multiple ADCs working together to process of a batch of conversions using the available paral-
lelism across multiple ADCs.
ADCA Interrupt ISRs are used to read results of both ADCA and ADCC.
External Connections

A0, A1, A2 and C2, C3, C4 pins should be connected to signals to be converted.

Watch Variables

adcAResult0 - Digital representation of the voltage on pin A0

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adcAResult1 - Digital representation of the voltage on pin A1

adcAResult2 - Digital representation of the voltage on pin A2
adcCResult0 - Digital representation of the voltage on pin C2
adcCResult1 - Digital representation of the voltage on pin C3
adcCResult2 - Digital representation of the voltage on pin C4

6.2 ADC Burst Mode

This example sets up ePWM1 to periodically trigger ADCA using burst mode. This allows for different channels
to be sampled with each burst.
Each burst triggers 3 conversions. A0 and A1 are part of every burst while the third conversion rotates between
A2, A3, and A4. This allows high importance signals to be sampled at high speed while lower priority signals
can be sampled at a lower rate.
ADCA Interrupt ISRs are used to read results for ADCA.
External Connections

A0, A1, A2, A3, A4

Watch Variables

adcAResult0 - Digital representation of the voltage on pin A0

adcAResult1 - Digital representation of the voltage on pin A1
adcAResult2 - Digital representation of the voltage on pin A2
adcAResult3 - Digital representation of the voltage on pin A3
adcAResult4 - Digital representation of the voltage on pin A4

6.3 ADC Burst Mode Oversampling

This example is an ADC oversampling example implemented with software. The ADC SOCs are configured in
burst mode, triggered by the ePWM SOC A event trigger.
External Connection

A2

Watch Variables

lv_results - Array of digital values measured on pin A2 (oversampling is configured by Over-

sampling_Amount)

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 C28x Driver Library Example Applications

6.4 ADC SOC Oversampling

This example sets up ePWM1 to periodically trigger a set of conversions on ADCA including multiple SOCs that
all convert A2 to achieve oversampling on A2.
ADCA Interrupt ISRs are used to read results of ADCA.
External Connections

A0, A1, A2 should be connected to signals to be converted.

Watch Variables

adcAResult0 - Digital representation of the voltage on pin A0

adcAResult1 - Digital representation of the voltage on pin A1
adcAResult2 - Digital representation of the voltage on pin A2

6.5 ADC PPB PWM trip (adc_ppb_pwm_trip)

This example demonstrates EPWM tripping through ADC limit detection PPB block. ADCAINT1 is configured to
periodically trigger the ADCA channel 2 post initial software forced trigger. The limit detection post-processing
block(PPB) is configured and if the ADC results are outside of the defined range, the post-processing block will
generate an ADCxEVTy event. This event is configured as EPWM trip source through configuring EPWM XBAR
and corresponding EPWM’s trip zone and digital compare sub-modules. The example showcases

one-shot
cycle-by-cycle
and direct tripping of PWMs through ADCAEVT1 source via Digital compare submodule.

The default limits are 0LSBs and 3600LSBs. With VREFHI set to 3.3V, the PPB will generate a trip event if the
input voltage goes above about 2.9V.
External Connections

A2 should be connected to a signal to convert

Observe the following signals on an oscilloscope
• ePWM1(GPIO0 - GPIO1)
• ePWM2(GPIO2 - GPIO3)
• ePWM3(GPIO4 - GPIO5)

Watch Variables

adcA2Results - digital representation of the voltage on pin A2

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6.6 ADC High Priority SOC (adc_high_priority_soc)

This example demonstrates configuration of ADC high priority SOCs in order to sample fastest control loop
signals with high priority while low priority signals are sampled with default round robin priority.
ADC PPB block is configured to capture delay between SOC trigger and actual start of the SOC sampling in
order to quantify the jitters in sampling high priority signals due to low priority signals. The delay in processing
an SOC is captured in ADCPPBxSTAMP.DLYSTAMP register field and the total delay in sampling an SOC is
equal to (DLYSTAMP - 2) cycles. In an optimal design the high priority SOC is expected to have less delay
between SOC trigger and actual start of the sample.
In this example ADCA, ADCB and ADCD are configured to sample both high and low priority signals. SOC0-3
are configured as high priority SOCs while rest are configured with default round-robin priority. ADCA SOC0-3
are configured as high priority SOCs sampling channels A0-A3, ADCB SOC0-1 are configured as high priority
SOCs sampling channels B0-B1 and ADCD SOC0-1 are configured as high priority SOCs sampling channels
D0-D1. For sampling low priority signals SOC4-SOC5 are configured sampling channel 4 and channel 13
respectively for ADCA and channel 4 and 5 for ADCB and ADCD. For ADCA, channel 13 is connected to
internal temperature sensor output and hence no signal needs to be connected to channel A13. High priority
SOC results are read in ADCINT1 ISR while low priority SOC results are read in idle loop.
This example has two modes of operation as follows. Desired mode can be selected by configuring the
EX_ADC_LP_SOC_TRIGGER macro accordingly. Mode 0: ADCINT as round robin SOC trigger Mode 1:
EPWM2 as round robin SOC trigger
In mode 0, EPWM1 is configured as trigger for high priority SOCs while ADCINT1 is configured as low priority
SOC trigger. ADCINT1 is configured to be triggered on completion of SOC1 conversion which in turn trigger
low priority SOCs 4 and 5 and ADCINT2 is configured to be triggered on completion of SOC5. ADC result
for high priority SOCs are read in ADCINT ISR while low priority SOC results are read in idle loop. ADCINT3
is configured to be triggered on completion of SOC3 and hence SOC2-SOC3 results for ADCA are read post
checking if the conversion is complete in ADCINT1 ISR.
In mode 0, SOC0-SOC1 for all ADCs will experience minimal delay(0 and 1 conversions) in processing due to
the high priority configuration. For ADCA, SOC4-SOC5 are triggered when SOC2-SOC3 conversion is ongoing,
hence SOC4-SOC5 will see some delay(2 and 3 conversions) in processing as expected. For ADCB and ADCD,
SOC4-SOC5 will see minimal delay (0 and 1 conversions) in processing as expected.
In mode 1, EPWM1 is configured as trigger for high priority SOCs while EPWM2 is configured as low priority
SOC trigger. ADCINT1 is configured to be triggered on completion of SOC3 conversion and ADC result for
high priority SOCs are read in the ADCINT ISR. Low priority SOCs 4 and 5 are triggered through EPWM2
and ADCINT2 is configured to be triggered on completion of SOC5. The result for low priority SOCs are read
in background loop. Since, SOC4-5 are triggered post SOC2-3 conversion(due to configured EPWM1 and
EPWM2 trigger frequency and duty), SOC4-SOC5 will have minimal delay(0 and 1 conversions respectively) in
SOC processing as expected.
Optimization Level: Example is expected to run with opt level = O2.
To view ADC results, put breakpoint at the statement where indexB is reset to zero in idle loop.
External Connections

A0-A4, B0-B1, B4-B5, D0-D1 and D4-D5 pins should be connected to signals to be converted.

Observe ePWM1, ePWM2 signals on oscilloscope

Watch Variables
ADC Results:

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 C28x Driver Library Example Applications

adcA0Results - adcA4Results - ADC result of channels A0-A4

adcA13Results - ADC result of channels A13(Temp Sensor output)
adcB0Results - adcB1Results - ADC result of channels B0-B1
adcB4Results - ADC result of channel B4
adcB5Results - ADC result of channel B5
adcD0Results - adcD1Results - ADC result of channels D0-D1
adcD4Results - ADC result of channel D4
adcD5Results - ADC result of channel D5

SOC conversion delays:

delaySocA0 - Delay in sampling ADCA SOC0

delaySocA3 - Delay in sampling ADCA SOC3
delaySocA4-delaySocA5 - Delay in sampling ADCA SOC4-SOC5
delaySocB0-delaySocB1 - Delay in sampling ADCB SOC0-SOC1
delaySocB4-delaySocB5 - Delay in sampling ADCB SOC4-SOC5
delaySocD0-delaySocD1 - Delay in sampling ADCD SOC0-SOC1
delaySocD4-delaySocD5 - Delay in sampling ADCD SOC4-SOC5

6.7 ADC Interleaved Averaging in Software

This example demonstrates software interleaved averaging of ADC input channels. ADCA/B channel 0 and 1
are sampled one after another in order to achieve interleaved averaging. SOC0-15 of ADCA and ADCB are
configured to sample channel 0 and 1 alternatively with channel 0 being sampled by even SOCs namely SOC0,
2, 4, 6, 8, 10, 12 & 14 and channel 1 being sampled by odd SOCs namely SOC1, 3, 5, 7, 9, 11, 13 & 15.
Sampling is initially triggered through external GPIO signal through enabling ADCEXTSOC signal via input
XBAR and thereafter through ADCINT1. GPIO33 is configured to trigger ADCA and B SOCs for the first time in
order to ensure synchronous operation. GPIO33 needs to be connected to GPIO32 which in turn is driven by
software to trigger the respective ADC SOCs.
ADCA Interrupt ISRs are used to read results of both ADCA and ADCB to demonstrate parallel operation of
multiple ADCs. ADCINT2 is configured to be triggered after completion of SOC7 while ADCINT1 is configured
to be triggered after completion of SOC15 conversion and respective SOC results of ADCA and ADCB are read
in ADCAINT2 and ADCAINT1 ISRs. Read SOC0-SOC15 ADC results are then averaged in ADCINT1 ISR to
get the filtered ADC output.
Early interrupt mode is configured to trigger the ADC interrupt just at the end of acquisition window in order
to save cycles(∼42 cycles) since ADCA result of SOC7 in ADCINT2 and SOC15 in ADCINT1 are read post
around 60 and 65 cycles respectively. Also, Fast ISRs are configured in the example to save some cycles
during compiler specific context save and restore.
Optimization level: This example is expected to be run with opt level = 2
Sampling rate related calculations:

ADC acquisition cycles programmed( S + H) = 15 SYSCLKS

Conversion time for 12-bit data = 10.5 ADCCLKS = N = 42 SYSCLKs
Time from 1st SOC trigger to interrupt trigger: 15 ∗ 57 + 15 = 870 SYSCLKs

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 C28x Driver Library Example Applications

Next ADC trigger will come after 870 SYSCLKs

Approximate ISR trigger frequency = 1/(870 ∗ 5ns) = 1/4350ns = 229 KSPS
Time taken in ADCINT1 ISR : 132 SYSCLKs (Fast ISR)(O2)
Time taken in ADCINT2 ISR : 76 SYSCLKs (Fast ISR)(O2)

To view results in graph window, add breakpoint inside while(1) loop in main() where bufferFull flag is cleared
and plot the watch variables.
External Connections

A0, A1, B0 and B1 pins should be connected to signals to be converted

Connect GPIO32 to GPIO33 to trigger ADC channels for the first time

Watch Variables

adcA0Results - A sequence of analog-to-digital conversion samples from pin A0.

adcA1Results - A sequence of analog-to-digital conversion samples from pin A1.
adcB0Results - A sequence of analog-to-digital conversion samples from pin B0.
adcB1Results - A sequence of analog-to-digital conversion samples from pin B1.

6.8 ADC Open Shorts Detection (adc_open_shorts_detection)

This example demonstrates the ADC open/shorts detection(ADCOSDETECT) circuit configuration for detecting
pin faults in the system. The example enables the open/shorts detection circuit along with mandatory ADC
configurations and diagnoses ADCA A0 input pin state before starting normal ADC conversions.
To enable the ADC OSDetect circuit: 1. Configure the ADC for conversion (E.g. channel, SOC, ACQPS,
prescalar, trigger etc). The OSDetect functionality is available in 12-bit only, hence ADCA is configured in 12-bit
mode in the example. 2. Set up the ADCOSDETECT register for the desired voltage divider connection. Refer
device TRM for details on available OSDetect configurations. 3. Initiate a conversion and inspect the conversion
result.
Note:
Note: The results must be interpreted based on what is driving on the input side and what are
the values of Rs and Cp. If the Vs signal can be disconnected from the input pin, the circuit
can be used to detect open and shorted input pins.

In the example, after configuring ADCA A0 channel in 12-bit mode along with other required ADC configurations,
following algorithm is used to check the A0 pin status: Step 1: Configure full scale OSDETECT mode & capture
ADC results(resultHi) Step 2: Configure zero scale OSDETECT mode & capture ADC results(resultLo) Step 3:
Disable OSDETECT mode and capture ADC results(resultNormal) Step 4: Determine the state of the ADC pin
a. If the pin is open, resultLo would be equal to Vreflo and resultHi would be equal to Vrefhi b. If the pin is shorted
to Vrefhi, resultLo should be approximately equal to Vrefhi and resultHi should be equal to Vrefhi c. If the pin is
shorted to Vreflo, resultLo should be equal to Vreflo and resultHi should be approximately equal to Vreflo d. If the
pin is connected to a valid signal, resultLo should be greater than osdLoLimit but less than resultNormal while
resultHi should be less than osdHiLimit but greater than resultNormal ——————————————————
———————– Input | Full-Scale output | Zero-scale Output | Pin Status ————————————————
—————————– Unknown| VREFHI | VREFLO | Open VREFHI | VREFHI | approx. VREFHI | Shorted to
VREFHI VREFLO | approx. VREFLO | VREFLO | Shorted to VREFLO Vn | Vn < resultHi < VREFHI | VREFLO
< resultLo < Vn | Good —————————————————————————– Step 5: osDetectStatusVal

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 C28x Driver Library Example Applications

of value greater than 4 would mean that there is no pin fault. a. If osDetectStatusVal == 1, means pin A0 is
OPEN b. If osDetectStatusVal == 2, means pin A0 is shorted to VREFLO c. If osDetectStatusVal == 4, means
pin A0 is shorted to VREFHI d. If osDetectStatusVal == 8, means pin A0 is in GOOD/VALID state e. Any value
of osDetectStatusVal > 4, means pin A0 is in VALID state
Following points should be noted while configuring the ADC in OSDETECT mode. 1. The divider resistance
tolerances can vary widely, hence this feature should not be used to check for conversion accuracy. 2. Consult
the device data manual for implementation and availability of analog input channels. 3. Due to high drive
impedance, a S+H duration much longer than the ADC minimum will be needed.
External Connections

A0 pin should be connected to signals to convert

Watch Variables

osDetectStatusVal : OS detection status of voltage on pin A0

adcAResult0 : a digital representation of the voltage on pin A0

6.9 ADC Software Triggering

This example converts some voltages on ADCA and ADCC based on a software trigger.
The ADCC will not convert until ADCA is complete, so the ADCs will not run asynchronously. However, this is
much less efficient than allowing the ADCs to convert synchronously in parallel (for example, by using an ePWM
trigger).
External Connections

A0, A1, C2, and C3 should be connected to signals to convert

Watch Variables

myADC0Result0 - Digital representation of the voltage on pin A0

myADC0Result1 - Digital representation of the voltage on pin A1
myADC1Result0 - Digital representation of the voltage on pin C2
myADC1Result1 - Digital representation of the voltage on pin C3

6.10 ADC ePWM Triggering

This example sets up ePWM1 to periodically trigger a conversion on ADCA.
External Connections

A0 should be connected to a signal to convert

Watch Variables

myADC0Results - A sequence of analog-to-digital conversion samples from pin A0. The time
between samples is determined based on the period of the ePWM timer.

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6.11 ADC Temperature Sensor Conversion

This example sets up the ePWM to periodically trigger the ADC. The ADC converts the internal connection
to the temperature sensor, which is then interpreted as a temperature by calling the ADC_getTemperatureC()
function.
Watch Variables

sensorSample - The raw reading from the temperature sensor

sensorTemp - The interpretation of the sensor sample as a temperature in degrees Celsius.

6.12 ADC Synchronous SOC Software Force

(adc_soc_software_sync)
This example converts some voltages on ADCA and ADCC using input 5 of the input X-BAR as a software
force. Input 5 is triggered by toggling GPIO0, but any spare GPIO could be used. This method will ensure that
both ADCs start converting at exactly the same time.
External Connections

A2, A3, C2, C3 pins should be connected to signals to convert

Watch Variables

myADC0Result0 : a digital representation of the voltage on pin A2

myADC0Result1 : a digital representation of the voltage on pin A3
myADC1Result0 : a digital representation of the voltage on pin C2
myADC1Result1 : a digital representation of the voltage on pin C3

6.13 ADC Continuous Triggering (adc_soc_continuous)

This example sets up the ADC to convert continuously, achieving maximum sampling rate.
External Connections

A0 pin should be connected to signal to convert

Watch Variables

adcAResults - A sequence of analog-to-digital conversion samples from pin A0. The time
between samples is the minimum possible based on the ADC speed.

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 C28x Driver Library Example Applications

6.14 ADC Continuous Conversions Read by DMA

(adc_soc_continuous_dma)
This example sets up two ADC channels to convert simultaneously. The results will be transferred by the DMA
into a buffer in RAM.
External Connections

A3 & C3 pins should be connected to signals to convert

Watch Variables

myADC0DataBuffer : a digital representation of the voltage on pin A3

myADC1DataBuffer : a digital representation of the voltage on pin C3

6.15 ADC PPB Offset (adc_ppb_offset)

This example software triggers the ADC. Some SOCs have automatic offset adjustment applied by the post-
processing block. After the program runs, the memory will contain ADC & post-processing block(PPB) results.
External Connections

A2, C2 pins should be connected to signals to convert

Watch Variables

myADC0Result : a digital representation of the voltage on pin A2

myADC0PPBResult : a digital representation of the voltage on pin A2, minus 100 LSBs of
automatically added offset
myADC1Result : a digital representation of the voltage on pin C2
myADC1PPBResult : a digital representation of the voltage on pin C2 plus 100 LSBs of
automatically added offset

6.16 ADC PPB Limits (adc_ppb_limits)

This example sets up the ePWM to periodically trigger the ADC. If the results are outside of the defined range,
the post-processing block will generate an interrupt.
The default limits are 1000LSBs and 3000LSBs. With VREFHI set to 3.3V, the PPB will generate an interrupt if
the input voltage goes above about 2.4V or below about 0.8V.
External Connections

A0 should be connected to a signal to convert

Watch Variables

None

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6.17 ADC PPB Delay Capture (adc_ppb_delay)

This example demonstrates delay capture using the post-processing block.
Two asynchronous ADC triggers are setup:

ePWM1, with period 2048, triggering SOC0 to convert on pin A0

ePWM2, with period 9999, triggering SOC1 to convert on pin A2

Each conversion generates an ISR at the end of the conversion. In the ISR for SOC0, a conversion counter is
incremented and the PPB is checked to determine if the sample was delayed.
After the program runs, the memory will contain:

conversion : the sequence of conversions using SOC0 that were delayed

delay : the corresponding delay of each of the delayed conversions

6.18 BGCRC CPU Interrupt Example

This example demonstrates how to configure and trigger BGCRC from the CPU. BGCRC module is configured
for 1 KB of GS0 RAM which is programmed with a known data. The pre-computed CRC value is used as the
golden CRC value. Interrupt is generated once the computation is done and checks if no error flags are raised
Calculation uses the 32-bit polynomial 0x04C11DB7 and seed value 0x00000000.
External Connections

None.

Watch Variables

pass - This should be 1.

runStatus - BGCRC running status. This will be BGCRC_ACTIVE if the module is running,
BGCRC_IDLE if the module is idle

6.19 BGCRC Example with Watchdog and Lock

This example demonstrates how to configure and trigger BGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if
the test does not complete in the specified time window.
The module is configured for 1kB of GS0 RAM which is programmed with random data. The golden CRC value
for comparison is computed using software method. Interrupt is generated once the computation is done and
checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections

None.

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Watch Variables

pass
bgcrcDone

6.20 CLA-BGCRC Example in CRC mode

This example demonstrates how to configure and trigger CLABGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if
the test does not complete in the specified time window.
The module is configured for 1kB of CLA ROM memory. The golden CRC value for comparison is computed
using software method. Interrupt is generated once the computation is done and checks if no error flags are
raised. The NMI is enabled and is triggered if an error is detected.
External Connections

None.

Watch Variables

pass
bgcrcDone

6.21 CLA-BGCRC Example in Scrub Mode

This example demonstrates how to configure and trigger CLA-BGCRC in Scrub mode. In Scrub mode, CRC of
data is not compared with the golden CRC. Error check is done using the ECC/Parity logic. It also showcases
how to configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used
as a diagnostic to check memory test completion within the expected time window. An error signal is generated
if the test does not complete in the specified time window.
The module is configured for 256 bytes of CLA ROM memory. Interrupt is generated once the computation is
done and checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections

None.

Watch Variables

pass
bgcrcDone

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6.22 CPU1 Secure Flash Boot

This example demonstrates how to use the secure flash boot mode for CPU1 as well as release CPU2 and CM
for secure flash boot.
Secure flash boot performs a CMAC authentication on the entry sector of flash upon device boot up. If authen-
tication passes, the application will begin execution. Learn more on the secure flash boot mode in the device
technical reference manual.
This project shows how to use the C2000 HEX Utility to generate a CMAC Tag based on a user CMAC key and
embed the value into the flash application. Additionally, the example details the method to call the CMAC API
from the user application to calculate CMAC on other flash sectors beyond the the application entry flash sector.
How to Run:

Load application into CPU1 flash (as well as CPU2 and CM applications)
Disconnect and reconnect to only CPU1
In memory window, set address 0xD00/D01 to 0x5AFFFFFF and address 0xD04 to 0x000A
(This sets emulation boot to secure flash boot)
Reset CPU1 via CCS and click resume
Observe the LEDs

Determining Pass/Fail without debugger connected: CPU1 - ControlCARD LED1.

LED off = Secure Boot failed

LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
LED Blinking = Secure Boot Passed and Full Flash CMAC passed CPU2 - ControlCARD
LED2.
LED off = Secure Boot failed
LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
LED Blinking = Secure Boot Passed and Full Flash CMAC passed CM - ControlCARD LED3.
LED off = Secure Boot failed
LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
LED Blinking = Secure Boot Passed and Full Flash CMAC passed

External Connections

None.

Watch Variables

cpu1_SuccessfullyBooted - True when CPU1 full flash CMAC authentication passes. Other-
wise, false.
cpu2_SuccessfullyBooted - True when CPU2 full flash CMAC authentication passes and CPU1
receives IPC. Otherwise, false.
cm_SuccessfullyBooted - True when CM full flash CMAC authentication passes and CPU1
receives IPC. Otherwise, false.

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6.23 CAN External Loopback

This example shows the basic setup of CAN in order to transmit and receive messages on the CAN bus. The
CAN peripheral is configured to transmit messages with a specific CAN ID. A message is then transmitted once
per second, using a simple delay loop for timing. The message that is sent is a 2 byte message that contains
an incrementing pattern.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual. Refer to [Programming Examples and Debug
Strategies for the DCAN Module](www.ti.com/lit/SPRACE5) for useful information about this example
External Connections

None.

Watch Variables

msgCount - A counter for the number of successful messages received

txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received

6.24 CAN External Loopback with Interrupts

This example shows the basic setup of CAN in order to transmit and receive messages on the CAN bus. The
CAN peripheral is configured to transmit messages with a specific CAN ID. A message is then transmitted once
per second, using a simple delay loop for timing. The message that is sent is a 4 byte message that contains an
incrementing pattern. A CAN interrupt handler is used to confirm message transmission and count the number
of messages that have been sent.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual. Refer to [Programming Examples and Debug
Strategies for the DCAN Module](www.ti.com/lit/SPRACE5) for useful information about this example
External Connections

None.

Watch Variables

txMsgCount - A counter for the number of messages sent

rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
errorFlag - A flag that indicates an error has occurred

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6.25 CAN-A to CAN-B External Transmit

This example initializes CAN module A and CAN module B for external communication. CAN-A module is setup
to transmit incrementing data for "n" number of times to the CAN-B module, where "n" is the value of TXCOUNT.
CAN-B module is setup to trigger an interrupt service routine (ISR) when data is received. An error flag will be
set if the transmitted data doesn’t match the received data.

Note:
Both CAN modules on the device need to be connected to each other via CAN transceivers.

Hardware Required

A C2000 board with two CAN transceivers

External Connections

ControlCARD CANA is on DEVICE_GPIO_PIN_CANTXA (CANTXA)

and DEVICE_GPIO_PIN_CANRXA (CANRXA)
ControlCARD CANB is on DEVICE_GPIO_PIN_CANTXB (CANTXB)
and DEVICE_GPIO_PIN_CANRXB (CANRXB)

Watch Variables

TXCOUNT - Adjust to set the number of messages to be transmitted

txMsgCount - A counter for the number of messages sent
rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
errorFlag - A flag that indicates an error has occurred

6.26 CAN External Loopback with DMA

This example sets up the CAN module to transmit and receive messages on the CAN bus. The CAN module
is set to transmit a 4 byte message internally. An interrupt is used to assert the DMA request line which then
triggers the DMA to transfer the received data from the CAN interface register to the receive buffer array. A data
check is performed once the transfer is complete.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual. Please refer to the appnote Programming
Examples and Debug Strategies for the DCAN Module (www.ti.com/lit/SPRACE5) for useful information about
this example
External Connections

None.

Watch Variables

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txMsgCount - A counter for the number of messages sent

rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received

6.27 CAN Transmit and Receive Configurations

This example shows the basic setup of CAN in order to transmit or receive messages on the CAN bus with a
specific Message ID. The CAN Controller is configured according to the selection of the define.
When the TRANSMIT define is selected, the CAN Controller acts as a Transmitter and sends data to the second
CAN Controller connected externally.If TRANMSIT is not defined the CAN Controller acts as a Receiver and
waits for message to be transmitted by the External CAN Controller. Refer to [Programming Examples and
Debug Strategies for the DCAN Module](www.ti.com/lit/SPRACE5) for useful information about this example

Note:
CAN modules on the device need to be connected to via CAN transceivers.

Hardware Required

A C2000 board with CAN transceiver.

External Connections

ControlCARD CANA is on DEVICE_GPIO_PIN_CANTXA (CANTXA)

and DEVICE_GPIO_PIN_CANRXA (CANRXA)

Watch Variables Transmit

MSGCOUNT - Adjust to set the number of messages

txMsgCount - A counter for the number of messages sent
txMsgData - An array with the data being sent
errorFlag - A flag that indicates an error has occurred
rxMsgCount - Has the initial value as No. of Messages to be received and decrements with
each message.

6.28 CAN Error Generation Example

This example demonstrates the ways of handling CAN Error conditions It generates the CAN Packets and sends
them over GPIO It is looped back externally to be received in CAN module The CAN Interrupt service routine
reads the Error status and demonstrates how different Error conditions can be detected
Change ERR_CFG define to the different Error Scenarios and run the example. The corresponding Error Flag
will be set in status variable of canaISR() routine. Uses a CPU Timer(Timer 0) for periodic timer interrupt
of CANBITRATE uSec On the Timer interrupt it sends the required CAN Frame type with the specified error
conditions

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Note:
CAN modules on the device need to be connected to via CAN transceivers.

Please refer to the application note titled "Configurable Error Generator for Controller Area Network" at
[Configurable Error Generator for Controller Area Network](https://www.ti.com/lit/pdf/spracq3) for further details
on this example
External Connections

ControlCARD GPIOTX_PIN should be connected to

DEVICE_GPIO_PIN_CANRXA(CANRXA)

Watch Variables Transmit

status - variable in canaISR for checking error Status

6.29 CAN Remote Request Loopback

This example shows the basic setup of CAN in order to transmit a remote frame and get a response for the
remote frame and store it in a receive Object. The CAN peripheral is configured to transmit remote request
frame and a remote answer frame messages with a specific CAN ID. Message object 3 is configured to transmit
a remote request. Message object 2 is configured as a remote answer object with filter mask such that it
accepts remote frame with any message ID and transmit’s remote answer with message ID 7 and data length 8.
Message object 1 is configured as a received object with filter message ID 7 so as to store the remote answer
data transmitted by message object 2.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual.
External Connections

None.

Watch Variables

txMsgData - An array with the data being sent

rxMsgData - An array with the data that was received

6.30 CAN example that illustrates the usage of Mask registers

This example initializes CAN module A for Reception. When a frame with a matching filter criterion is received,
the data will be copied in mailbox 1 and LED will be toggled a few times and the code gets ready for the next
frame. If a message of any other MSGID is received, an ACK will be provided Completion of reception is
determined by polling CAN_NDAT_21 register. No interrupts are used. Refer to [Programming Examples and
Debug Strategies for the DCAN Module](www.ti.com/lit/SPRACE5) for useful information about this example
Hardware Required

An external CAN node that transmits to CAN-A on the C2000 MCU

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Watch Variables

rxMsgCount - A counter for the number of messages received

rxMsgData - An array with the data that was received

6.31 CLA arcsine(x) using a lookup table (cla_asin_cpu01)

In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation

CLA1 Math Tables (RAMLS0)

• CLAasinTable - Lookup table
CLA1 to CPU Message RAM
• fResult - Result of the lookup algorithm
CPU to CLA1 Message RAM
• fVal - Sample input to the lookup algorithm

Watch Variables

fVal - Argument to task 1

fResult - Result of arcsin(f V al)

6.32 CLA arctangent(x) using a lookup table (cla_atan_cpu01)

In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation

CLA1 Math Tables (RAMLS0)

• CLAatan2Table - Lookup table
CLA1 to CPU Message RAM
• fResult - Result of the lookup algorithm
CPU to CLA1 Message RAM
• fNum - Numerator of sample input
• fDen - Denominator of sample input

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Watch Variables

fVal - Argument to task 1

fResult - Result of arctan(f V al)

6.33 CLA background nesting task

This example configures CLA task 1 to be triggered by EPWM1 running at 2 Hz (period = 0.5s). A background
task is configured to be triggered by CPU timer running at .5 Hz (period = 2s). CLA task 1 toggles LED1 at the
start and end of the task and the background task toggles LED2 at the start and end of the task. Background
task will be preempted by Task1 and hence LED1 will be toggling even while LED2 is ON.
Note that the compile flag cla_background_task is turned on in this project. Enabling background task adds
additional context save/restore cycles during task switching thus increasing the overall trigger-to-task latency.
If the application does not use the background CLA task, it is recommended to turn this flag off for better
performance. The option is available in Project Properties -> C2000 Build -> C2000 Compiler -> Advanced
Options -> Runtime Model Options.
External Connections

None

Watch Variables

None

#########################################################################

6.34 Controlling PWM output using CLA

This example showcases how to update PWM signal output using CLA. EPWM1 is configured to generate
complementary signals on both of its channels of fixed frequency 100 KHz. EPWM4 is configured to trigger a
periodic CLA control task of frequency 10 KHz. The CLA task implements a very simple logic to vary the duty
of the EPWM1 outputs by increasing it by 0.1 in every iteration and maintaining it in the range of 0.1-0.9. For
actual use-cases, the control logic could be modified to much more complex depending upon the application.
The other CLA task (CLA task 8) is triggered by software at beginning to initialize the CLA global variables
External Connections

Observe GPIO0 (EPWM1A) on oscilloscope

Observe GPIO1 (EPWM1B) on oscilloscope

Watch Variables

duty

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6.35 Just-in-time ADC sampling with CLA

This example showcases how to utilize early-interrupt feature of ADC in combination with the low interrupt
response of CLA to enable faster system response and achieve high frequency control loops. EPWM1 is
configured to generate a PWM output signal of frequency 1 MHz and this is also used to trigger the ADC
sampling at each cycle. ADCA is configured to sample the input on Channel 0 and to generate the early
interrupt at the end of S/H + offset cycles. This interrupt is used to trigger the CLA control task. The CLA task
implements the control logic to update the duty of the PWM output based on reading the ADC sample data
just-in-time i.e. as soon as the ADC results gets latched.The early interrupt feature and low interrupt latency of
CLA allows to do some pre-processing as well before reading the ADC data and still completes updating the
PWM output before the next interrupts comes in i.e. data read and PWM update is done within a 1 MHz cycle.
For illustration purposes, 3-point moving average filter is used to simulate some processing and few steps of
the filtering code are done before reading the ADC result which we consider as pre-processing code. The ADC
interrupt offset is programmed based on the cycles consumed by the pre-processing code.
The calculation for interrupt offset value is as follows :- -ADC acquisition cycles programmed = 10 SYSCLKS
-Conversion time for 12-bit data = 10.5 ADCCLKS = N = 42 SYSCLKS -CLA task trigger to first instruction in
Fetch delay = 4 -Let the interrupt offset value be ’x’ -The code inside CLA control task before ADC read takes
below cycles : Setting up profiling gpio : 3 cycles Pre-processing : 13 cycles Total = 3 + 13 = 16 cycles
As described in device TRM, in order to read just-in-time the total delay before reading ADC should be (N-2)
cycles = 40 i.e. : x + 4 + 16 = 40 : x = 20
NOTE :- The optimization is off for this project and the cycles quoted above corresponds to that case.
GPIO2 is used for profiling purposes. GPIO2 is set at the beginning of CLA task 1 and is reset at the end of the
task. Thus ON time of GPIO2 indicates the CLA activity. In order to validate the example functionality , observe
the GPIO0 (PWM output) and GPIO2 (profiling GPIO) on CRO. The cycles difference between the rising edge
of the GPIO0 and GPIO2 indicate the total delay from the time of ADC trigger to setting up of profiling GPIO
inside CLA task which should be around 44 cycles (220 ns) based on the above calculation.
External Connections

Provide constant DC input on ADCA0 for quick validation. GND -> Should observe PWM
output duty = 0.1 3.3V -> Should observe PWM output duty = 0.9 Can also provide analog
input in range 0 - 3.3V upto fs / 10 = 100 KHz for observing continuous duty variations

Observe GPIO0 on oscilloscope

Observe GPIO2 on oscilloscope

Watch Variables

None

6.36 Optimal offloading of control algorithms to CLA

This example showcases how to optimally offload the control algorithms from CPU to CLA in order to meet the
system requirements. In this example, two control loops are simulated, the faster one (loop1) running at 200
KHz and the slower one (loop2) running at 20 KHz. Loop1 senses the first parameter at ADCA Channel 0,
runs the PI controller to achieve the target and contributes to the duty of EPWM1A output with 80% weightage.
Loop2 senses the second parameter at ADCB Channel 2, runs the PI controller and contributes to the duty of
EPWM1A output with 20% weightage. It is important to note that since these are just software simulated control

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loops but there is no actual physical process involved and hence updating the duty is not going to have any affect
on sampled inputs. ADCA is configured to oversample the first parameter using SOCs 0-3 to suppress the noise
and similarly ADCB is used to oversample the second parameter. EPWM4 and EPWM5 are configured to trigger
the ADCA and ADCB sampling at loop1 and loop2 frequencies respectively. Once the conversion of all 4 SOCs
complete, a CPU ISR or a CLA task is triggered based on the user-configuration. There is also a background
task running in the main loop which disables the entire system including PWM output and the control loops
when "system_OFF" is set to 1. The system gets enabled again once "system_OFF" is restored back to 0. By
default system_OFF is set to 0 but it’s value can be updated dynamically by adding it to expression window and
writing to it. DCL library is included in the project to make use of optimal PI controllers used in both the loops.
User-configurable pre-defined symbol "run_loop1_cla" has been added to the project options in order to specify
whether to run the loop1 on C28x or CLA. GPIO2 and GPIO3 are used to profile the execution of loop1 and
loop2.
For run_loop1_cla == 0 i.e. both loops running on CPU
-> Loop1 Utilization = ∼77.5% (measured using profiling GPIO2) -> Loop2 Utilization = ∼6% (measured using
profiling GPIO3) -> Background task in a while loop -> Total CPU utilization is greater than Utilization bound
(UB) Hence the system is non-schedulable, lower priority task (Loop2) execution never completes (no toggling
observed on GPIO3) and also background task never gets chance to execute
For run_loop1_cla == 1 i.e. high frequency control loop (loop1) is offloaded to CLA while loop2 runs on CPU
-> Loop1 Utilization (CLA) = ∼73% -> Loop2 Utilization (CPU)= ∼6% -> Total CPU utilization has come down
to just ∼6% Hence the system is perfectly schedulable, no miss happens for any of the loops and offloading of
loop1 to CLA saves CPU bandwidth to execute background tasks as well
For quick inspection of the example functionality, constant DC HIGH/LOW inputs can be provided to the analog
channels instead of varying analog voltages. The target value for both the loops are set as some intermediate
value i.e. 3500 corresponds to ∼2.8V. Now since the sensed inputs are constant and not same as target so the
controller outputs will get saturated soon to either 1 or 0. Thus the "duty" variable can take only fixed values
based on the equations used in the loops. Infact the duty output would be very intutive, for instance if both inputs
are LOW(GND), the controller will try to produce the maximum duty as the target is higher than sensed value
hence the duty should be 1.0(0.2 + 0.8) but will get saturated to 0.9(the maximum value defined). Similarly if
both inputs are made HIGH, the duty will be 0.1 (the minimum saturation value defined). The final duty table is
shown below :
External Connections

Observe GPIO2 (Loop1 Profiling) on oscilloscope

Observe GPIO3 (Loop2 Profiling) on oscilloscope
Observe GPIO0 (EPWM1A Output) on oscilloscope

Provide constant HIGH(3.3V)/LOW(0V) on both ADCA Ch0 and ADCB Ch2 for quick valida-
tion, the following duty value should be observable at EPWM1A for various combinations if the
system is perfectly schedulable i.e. both loops gets chance to execute properly :-

A0 B2 duty GND GND 0.9 3.3V GND 0.2 GND 3.3V 0.8 3.3V 3.3V 0.1
Note :- The optimization is OFF for this project and all the profiling data quoted above corresponds to this case.

6.37 Handling shared resources across C28x and CLA

This example showcases how to handle shared resource challenges across C28x and CLA. As the peripherals
are shared between CLA and the CPU, overlapping read-modify-write to the registers by them can lead to data

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race conditions ultimately leading to data violation or incorrect functionality. In this example, CPU ISR and CLA
tasks runs independently. CPU ISR gets triggered by EPWM4 and toggles the EPWM1B output via software by
controlling CSFB bits of AQCSFRC. CLA task gets triggered by EPWM5 and toggles the EPWM1A output via
software by controlling CSFA bits of AQCSFRC. Thus in this process both CPU and CLA do read-modify -write
to AQCSFRC register independently at different frequencies so there is chance of race condition and updates
due to one of them can get lost/. overwritten. This can be clearly observed by updating "phase_shift_ON" to 0U
and probing the EPWM1A and 1B outputs on a scope.
This is a standard critical section problem and can be handled by software handshaking mechanism like mu-
tex etc. But most of the real-time control applications are time-sensitive and cannot afford addition software
overhead hence this example suggests an alternative hardware based technique to avoid shared resource con-
flicts between CPU and CLA. The phase shifting mechanism of the EPWM modules is utilized to schedule the
CLA task and CPU ISR as desired. EPWM4 generates a synchronous pulse every ZERO event and provides
a phase shift of 20 cycles to EPWM5. This way both CLA task and C28x ISR runs at original frequencies
i.e. 100KHz and 10KHz but CLA task leads with a phase offset of 20 cycles wrt CPU ISR. Hence concurrent
read-modify-writes to AQCSFRC never happens and the EPWM1A and EPWM1B outputs behave as desired
i.e. consistent 50 KHz PWM output on EPWM1A and 5 KHz PWM output on EPWM1B with a duty ∼50% on
both should be generated. In order to utilize this phase shifting mechanism in this example, please make sure
"phase_shift_ON" is set to 1.
External Connections

Observe GPIO0 (EPWM1A Output) on oscilloscope

Observe GPIO1 (EPWM1B Output) on oscilloscope
Observe GPIO2 (CLA Task Profiling) on oscilloscope
Observe GPIO3 (CPU ISR Profiling) on oscilloscope

Note :- The phase offset value can easily be configured by updating TBPHS register to schedule the CLA task
and C28x ISR as desired depending upon the application need so as to avoid overlapping register writes by
CPU and CLA
Note :- The optimization is on and set to O2 for the project and all the results quoted correspond to this case.

6.38 CLB Timer Two States

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, the timer is setup the same as the previous example. The difference is the use of the FSM
submodule to toggle the output of the CLB which is then exported to a GPIO. The FSM module acts as a single
bit memory block. Interrupts are setup in the same format as the previous example. The interrupt delay of the
CLB can be seen by comparing the output of the CLB and the GPIO toggled in the ISR.

6.39 CLB Interrupt Tag

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, a timer is setup with two different match values. These two events are used by the HLC
submodule to generate interrupts. The interrupt TAG is used to differentiate between the interrupt generated
due to the match1 event of the CLB counter and the match2 event of the CLB counter.

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6.40 CLB Output Intersect

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, the CLB module is set up the same as the external_AND_gate example. However, instead of
the output being exported to the GPIO using Output X-BAR, the output is exported to the GPIO by replacing
the output of ePWM1. This is done by configuring the GPIO for EPWM1A output, followed by enabling output
intersection.

6.41 CLB PUSH PULL

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, the use of the PUSH-PULL interface is shown. Multiple COUNTER submodules, HLC submod-
ule, FSM submodules, and OUTLUT submodules are used. The PUSH-PULL interface is used alongside the
GP register to update the COUNTER submodulesÃćÂĂÂŹ event frequencies.

6.42 CLB Multi Tile

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the output of a CLB TILE is passed to the input of another CLB TILE. The output of the second
CLB TILE is then exported to a GPIO, showcasing how two CLB TILEs can be used in series.

6.43 CLB Tile to Tile Delay

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the output of a GPIO is taken into the CLB TILE through INPUT XBAR and the CLB XBAR. The
signal is forwarded by the TILE to the next TILE. This time the signal only goes through the CLB XBAR and NOT
the Input XBAR. This is done to show that delays are added when the signals are passed from TILE to TILE
and the delay is NOT characterized. The user should always avoid passing signals with timing requirements
between tiles. The COUNTER modules inside the CLBs will count the amount of delay in cycles.

6.44 CLB based One-shot PWM

For the detailed description of this example, please refer to : ‘C2000Ware_PATH Tool Users Guide.pdf‘

6.45 CLB AOC Control

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘

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In this example the Asynchronous Output Conditioning block is used to asynchronously AND gate the input
signals to the CLB. This module is only available for CLB types 2 and up.

6.46 CLB AOC Release Control

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the Asynchronous Output Conditioning block is used to asynchronously set/release the input
signals to the CLB. This module is only available for CLB types 2 and up.

6.47 CLB Combinational Logic

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
The objective of this example is to prevent simultaneous high or low outputs on a PWM pair. PWM modules 1
and 2 are configured to generate identical waveforms based on a fixed frequency up-count mode.

6.48 CLB XBARs

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the CLB INPUTXBAR and CLB OUTPUTXBAR are used to take input signals from GPIOs into
the CLB TILEs and take output signal from the TILE to GPIOs. The availability of these XBARs are device
dependent.

6.49 CLB AOC Control

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the clock prescalar of the CLB module is used to divide down the CLB clock and use it as an
input to the TILE logic. Also the HLC module is used to generate NMI interrupts. This module is only available
for CLB types 2 and up.

6.50 CLB Serializer

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the CLB COUNTER is used in serializer mode to act as a shift register. This module is only
available for CLB types 2 and up.

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6.51 CLB LFSR

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the CLB COUNTER module is used in Linear Feedback Shift Register (LFSR) mode. This
module is only available for CLB types 2 and up.

6.52 CLB Lock Output Mask

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the lock outpt mask feature of the CLB is used to lock the selected output signal override
settings. This module is only available for CLB types 3 and up.

6.53 CLB INPUT Pipeline Mode

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the CLB Input Pipeline mode is enable to delay the input signal by a clock cycle. This module is
only available for CLB types 3 and up.

6.54 CLB Clocking and PIPELINE Mode

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the CLB pipeline mode is enable and affects the behavior of the CLB COUNTERs and HLC.
This module is only available for CLB types 3 and up.

6.55 CLB SPI Data Export

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the high speed data export feature of the CLB is used and one of the HLC registers is exported
out of the CLB module using the SPI RX buffer. This module is only available for CLB types 3 and up.

6.56 CLB SPI Data Export DMA

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example the high speed data export feature of the CLB is used and one of the HLC registers is exported
out of the CLB module using the SPI RX buffer. The data received in the SPI RX buffer is transferred to memory
using DMA. This module is only available for CLB types 3 and up.

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6.57 CLB Trip Zone Timestamp

This example displays how to timestamp interrupts generated by the CLB. An interrupt is generated when
ePWM1 is tripped.
ePWM1 is configured to be interrupted by TZ1 and TZ2, both one shot trip sources.
The CLB is configured as follows:

COUNTER0 and COUNTER1 continually count when the program begins.

COUNTER0 timestamps TZ1 and COUNTER1 timestamps TZ2.
COUNTER2 increments once when COUNTER0/COUNTER1 overflows using LUT2.
FSM0/1 are configured to sync counters and stop COUNTER0/1 when an interrupt is received.
TZ1 (GPIO12) and TZ2 (GPIO13) are routed as inputs through CLBXBAR.
BOUNDARY.boundaryInput0 denotes TZ1. On rising edge, HLC issues an interrupt with tag
12.
BOUDNARY.in1 denotes TZ2. On rising edge, HLC issues an interrupt with tag 13.
BOUNDARY.boundaryInput7 serves as a simultaneous enable for COUNTER0/1 to begin
counting.

TZ1 is tripped when GPIO12 is connected to GND. TZ2 is tripped when GPIO13 is connected to GND. When
an interrupt occurs, the interrupt handler determines the initial trip source and stores this value in a variable
’initialTripZone’.
View these variables in Debug Expressions tab:
initialTripZone: stores the first TZ to have been tripped tz1Counter64bit: stores the counter value at the instant
that TZ1 is tripped. tz2Counter64bit: stores the counter value at the instant that TZ2 is tripped.

6.58 CLB GPIO Input Filter

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
This example demonstrates use of finite state machines (FSMs) and counters to implement a simple
ÃćÂĂŸglitchÃćÂĂÂŹ filter which might, for example, be applied to an incoming GPIO signal to remove un-
wanted short duration pulses.

6.59 CLB CRC

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, the CLB module is used to perform the cyclic redundancy check (C.R.C.) with twelve messages
in bits checked with ten different CRC polynomials.
First element passed in is message length, second is the message stored in input_data
This example is only available for CLB types 2 and up.
The known values in the output_data are compared with expected values from the CLB-based CRC calculation.
A total of 120 messages are verified, and the number of matching messages are displayed in passCount

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Variables to add to Watch Expressions in debug view: passCount - number of messages that match between
generated and known CRC values failCount - number of messages that fail the CRC value verification
###########################################################################

6.60 CLB Auxilary PWM

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
This example configures a CLB tile as an auxiliary PWM generator. The example uses combinatorial logic
(LUTs), state machines (FSMs), counters, and the high level controller (HLC) to demonstrate the PWM output
generation capabilities using CLB.

6.61 CLB PWM Protection

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
This example extends the features of example 1 to ensure an active high complementary pair PWM configu-
ration always operates with a minimum value of dead-band irrespective of how the generating PWM module is
configured. The example illustrates the configuration of four separate PWM tiles to implement PWM protection
on four PWM modules. The outputs of PWM modules 1 to 4 are operated on by CLB tiles 1 to 4, respectively.

6.62 CLB Event Window

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
This example uses the counter, FSM, and HLC sub-modules of the CLB to implement an event timing feature
which detects whether an interrupt service routine takes too long to respond to an interrupt. The example
configures four PWM modules to operate in up-count mode and generate a low-to-high edge on a timer zero
match event. The zero match event also triggers a PWM ISR which, for the purposes of this example, contains
a dummy payload of variable length. At the end of the ISR, a write operation takes place to a CLB GP register
to indicate the ISR has ended.

6.63 CLB Signal Generator

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
This example uses CLB1 to generate a rectangular wave and CLB2 to check the rectangular wave generated
by CLB1 doesnÃćÂĂÂŹt exceed the defined duty cycle and period limits.

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6.64 CLB State Machine

For the detailed description of this example, please refer to: C2000Ware_PATH With the C2000 CLB.pdf This
application report describes the process of creating this CLB example and can be used as guidance on desiging
custom logic with the CLB. This example uses all submodules inside a CLB TILE in order to implement a
complete system.

6.65 CLB External Signal AND Gate

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, two external signals from two GPIOs are passed through the Input X-BAR and the CLB X-BAR
to the CLB TILE. Inside the CLB module these two signals are ANDED. The output of the AND gate is then
exported to a GPIO, using Output X-BAR.

6.66 CLB Timer

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘
In this example, a COUNTER module is used to create timed events. The use of the GP Register is shown.
Through setting/clearing the bits in the GP register, the timer is started, stopped or changes direction. The
output of the timer event (1-clock cycle) is exported to a GPIO. Interrupts are generated from the timer event
using the HLC module. A GPIO is also toggled inside the CLB ISR. The indirect CLB register access is used
to update the timerÃćÂĂÂŹs event match value and the active counter register to modify the frequency of the
timer.

6.67 CLB Empty Project

For the detailed description of this example, please refer to: ‘C2000Ware_PATH Tool Users Guide.pdf‘

6.68 C28x Common Configurations

This example configures the GPIOs and Allocates the shared peripherals according to the defines selected by
the users.

6.69 CMPSS Asynchronous Trip

This example enables the CMPSS1 COMPH comparator and feeds the asynchronous CTRIPOUTH signal to
the GPIO14/OUTPUTXBAR3 pin and CTRIPH to GPIO15/EPWM8B.

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CMPSS is configured to generate trip signals to trip the EPWM signals. CMPIN1P is used to give positive input
and internal DAC is configured to provide the negative input. Internal DAC is configured to provide a signal at
VDD/2. An EPWM signal is generated at GPIO15 and is configured to be tripped by CTRIPOUTH.
When a low input(VSS) is provided to CMPIN1P,

Trip signal(GPIO14) output is low

PWM8B(GPIO15) gives a PWM signal

When a high input(higher than VDD/2) is provided to CMPIN1P,

Trip signal(GPIO14) output turns high

PWM8B(GPIO15) gets tripped and outputs as high

External Connections

Give input on CMPIN1P (HSEC Pin 15)

Outputs can be observed on GPIO14 and GPIO15 using an oscilloscope

Watch Variables

None

6.70 CMPSS Digital Filter Configuration

This example enables the CMPSS1 COMPH comparator and feeds the output through the digital filter to the
GPIO14/OUTPUTXBAR3 pin.
CMPIN1P is used to give positive input and internal DAC is configured to provide the negative input. Internal
DAC is configured to provide a signal at VDD/2.
When a low input(VSS) is provided to CMPIN1P,

GPIO14 output is low

When a high input(higher than VDD/2) is provided to CMPIN1P,

GPIO14 output turns high

6.71 CPU Register Access

This example demonstrates functions which can be used to access CPU register contents using C-Callable
assembly APIs .

6.72 Buffered DAC Enable

This example generates a voltage on the buffered DAC output, DACOUTA/ADCINA0 and uses the default DAC
reference setting of VDAC.

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External Connections

When the DAC reference is set to VDAC, an external reference voltage must be applied to the
VDAC pin. This can be accomplished by connecting a jumper wire from 3.3V to ADCINB0.

Watch Variables

None.

6.73 Buffered DAC Random

This example generates random voltages on the buffered DAC output, DACOUTA/ADCINA0 and uses the de-
fault DAC reference setting of VDAC.
External Connections

When the DAC reference is set to VDAC, an external reference voltage must be applied to the
VDAC pin. This can accomplished by connecting a jumper wire from 3.3V to ADCINB0.

Watch Variables

None.

6.74 Buffered DAC Sine (buffdac_sine)

This example generates a sine wave on the buffered DAC output, DACOUTA/ADCINA0 (HSEC Pin 9) and uses
the default DAC reference setting of VDAC.
When the DAC reference is set to VDAC, an external reference voltage must be applied to the VDAC pin. This
can accomplished by connecting a jumper wire from 3.3V to ADCINB0.
Run the included .js file to add the watch variables. This example uses the SGEN module. Documentation for
the SGEN module can be found in the SGEN library directory.
The generated waveform can be adjusted with the following variables while running:

waveformGain : Adjust the magnitude of the waveform. Range is from 0.0 to 1.0. The default
value of 0.8003 centers the waveform within the linear range of the DAC
waveformOffset : Adjust the offset of the waveform. Range is from -1.0 to 1.0. The default
value of 0 centers the waveform
outputFreq_hz : Adjust the output frequency of the waveform. Range is from 0 to maxOut-
putFreq_hz
maxOutputFreq_hz : Adjust the max output frequency of the waveform. Range - See SGEN
module documentation for how this affects other parameters

The generated waveform can be adjusted with the following variables/macros but require recompile:

samplingFreq_hz : Adjust the rate at which the DAC is updated. Range - See SGEN module
documentation for how this affects other parameters

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SINEWAVE_TYPE : The type of sine generated. Range - LOW_THD_SINE,

HIGH_PRECISION_SINE

The following variables give additional information about the generated waveform: See SGEN module docu-
mentation for details

freqResolution_hz
maxOutput_lsb : Maximum value written to the DAC.
minOutput_lsb : Minimum value written to the DAC.
pk_to_pk_lsb : Magnitude of generated waveform.
cpuPeriod_us : Period of cpu.
samplingPeriod_us : The rate at which the DAC is updated. Note that samplingPeriod_us
has to be greater than the DAC settling time.
interruptCycles : Interrupt duration in cycles.
interruptDuration_us : Interrupt duration in uS.
sgen : The SGEN module instance.
DataLog : Circular log of writes to the DAC.

6.75 DCC Single shot Clock verification

This program uses the XTAL clock as a reference clock to verify the frequency of the PLLRAW clock.
The Dual-Clock Comparator Module 0 is used for the clock verification. The clocksource0 is the reference clock
(Fclk0 = 25Mhz) and the clocksource1 is the clock that needs to be verified (Fclk1 = 200Mhz). Seed is the value
that gets loaded into the Counter.
Please refer to the TRM for details on counter seed values to be set.
External Connections

None

Watch Variables

status/result - Status of the PLLRAW clock verification

6.76 DCC Single shot Clock measurement

This program demonstrates Single Shot measurement of the INTOSC2 clock post trim using XTAL as the
reference clock.
The Dual-Clock Comparator Module 0 is used for the clock measurement. The clocksource0 is the reference
clock (Fclk0 = 25Mhz) and the clocksource1 is the clock that needs to be measured (Fclk1 = 10Mhz). Since the
frequency of the clock1 needs to be measured an initial seed is set to the max value of the counter.
Please refer to the TRM for details on counter seed values to be set.
External Connections

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None

Watch Variables

result - Status if the INTOSC2 clock measurement completed successfully.

meas_freq1 - measured clock frequency, in this case for INTOSC2.

6.77 DCC Continuous clock monitoring

This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 200Mhz). The clock0
and clock1 seed are set to achieve a window of 500us. Seed is the value that gets loaded into the Counter. For
the sake of demo a slight variance is given to clock1 seed value to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections

None

Watch Variables

status/result - Status of the PLLRAW clock monitoring

cnt0 - Counter0 Value measure when error is generated
cnt1 - Counter1 Value measure when error is generated
valid - Valid0 Value measure when error is generated

6.78 DCC Continuous clock monitoring

This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop. The
Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 200Mhz). The clock0
and clock1 seed are set automatically by the error tolerances defined in the sysconfig file included this project.
For the sake of demo an un-realistic tolerance is assumed to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections

None

Watch Variables

status/result - Status of the PLLRAW clock monitoring

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cnt0 - Counter0 Value measure when error is generated

cnt1 - Counter1 Value measure when error is generated
valid - Valid0 Value measure when error is generated

6.79 DCC Detection of clock failure

This program demonstrates clock failure detection on continuous monitoring of the PLL Clock in the system
using XTAL as the osc clock source. Once the oscillator clock fails, it would trigger a DCC error interrupt,
causing the decrement/ reload of counters to stop. In this examples, the clock failure is simulated by turning off
the XTAL oscillator. Once the ISR is serviced, the osc source is changed to INTOSC1 and the PLL is turned off.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 25Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 200Mhz). Seed is the
value that gets loaded into the Counter.

Note:
In the current example, the XTAL is expected to be a Resonator running in Crystal mode which
is later switched off to simulate the clock failure. If an SE Crystal is used, you will need to
physically disconnect the clock on the board.

Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections

None

Watch Variables

status/result - Status of the clock failure detection

6.80 DCSM Memory partitioning Example

This example demonstrates how to configure and use DCSM. It configures the 1st Zone Select Block in the
OTP to change the zone passwords and allocates LS0-LS3 to zone 1 & LS4-LS7 to zone 2.
Zone1 | Zone2 | LS0-LS3 | LS4-LS7 |
In this example, zoning of memories is done by the OTP programming whose values are configured in
dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file. It writes some
data in the zones and checks before locking and after locking and matches with the data set . Ideally after
locking zone1, the data set stored in zone1 should not be readable( or reads a 0 value) and zone2 that is not
secured matches the written data set. It demonstrates how to lock and and unlock zones by showing where to
put the password and how to check if it is secured or unsecured.
External Connections

None.

Watch Variables

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result - Status of Secure memory partitioning done through OTP programming.

set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the
execution of the example.
Zone1_Locked_Array - Array demonstrating secured memory
Unsecure_mem_Array - Array demonstrating Unsecured memory

Note:
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :

Allocate LS0-LS3 to zone 1 , LS4-LS7 to zone 2 ZSBx_Z1_GRABRAM1R 0x000AAA55

ZSBx_Z2_GRABRAM1R 0x000A55AA
Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF
Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF
Note:
DCSM_unlockZone∗CSM function should not be called in an actual application, should only be
used for once to program the OTP memory. Ensure flash data cache is disabled before calling
this function.

6.81 Empty DCSM Tool Example

This example is an empty project setup for DCSM Tool and Driverlib development. For guidance refer to: [C2000
DCSM Security Tool](http://www.ti.com/lit/pdf/spracp8)

6.82 DMA GSRAM Transfer (dma_ex1_gsram_transfer)

This example uses one DMA channel to transfer data from a buffer in RAMGS0 to a buffer in RAMGS1. The
example sets the DMA channel PERINTFRC bit repeatedly until the transfer of 16 bursts (where each burst is 8
16-bit words) has been completed. When the whole transfer is complete, it will trigger the DMA interrupt.

Note:
: This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

Watch Variables

sData - Data to send

rData - Received data

6.83 DMA GSRAM Transfer (dma_ex2_gsram_transfer)

This example uses one DMA channel to transfer data from a buffer in RAMGS0 to a buffer in RAMGS1. The
example sets the DMA channel PERINTFRC bit repeatedly until the transfer of 16 bursts (where each burst is 8
16-bit words) has been completed. When the whole transfer is complete, it will trigger the DMA interrupt.

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Watch Variables

sData - Data to send

rData - Received data

6.84 eCAP APWM Example

This program sets up the eCAP module in APWM mode. The PWM waveform will come out on GPIO5. The
frequency of PWM is configured to vary between 10Hz and 20Hz using the shadow registers to load the next
period/compare values.

6.85 eCAP Capture PWM Example

This example configures ePWM3A for:

Up count mode
Period starts at 500 and goes up to 8000
Toggle output on PRD

eCAP1 is configured to capture the time between rising and falling edge of the ePWM3A output.
External Connections

eCAP1 is on GPIO16
ePWM3A is on GPIO4
Connect GPIO4 to GPIO16.

Watch Variables

ecap1PassCount - Successful captures.

ecap1IntCount - Interrupt counts.

6.86 eCAP APWM Phase-shift Example

This program sets up the eCAP1 and eCAP2 modules in APWM mode to generate the two phase-shifted PWM
outputs of same duty and frequency value The frequency, duty and phase values can be programmed of choice
by updating the defined macros. By default 10 Khz frequency, 50% duty and 30% phase shift values are used.
eCAP2 output leads the eCAP1 output by 30% GPIO5 and GPIO6 are used as eCAP1/2 outputs and can be
probed using analyzer/CRO to observe the waveforms.

6.87 eCAP Software Sync Example

This example configures ePWM3A for:

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Up count mode
Period starts at 500 and goes up to 8000
Toggle output on PRD

eCAP1, eCAP2 and eCAP3 are configured to capture the time between rising and falling edge of the ePWM3A
output.
External Connections

eCAP1, eCAP2, eCAP3 are on GPIO16

ePWM3A is on GPIO4
Connect GPIO4 to GPIO16.

Watch Variables

ecapPassCount - Successful captures.

ecap3IntCount - Interrupt counts.

6.88 Pin setup for EMIF module accessing ASRAM.

This example configures pins for EMIF in ASYNC mode.
###########################################################################

6.89 EMIF1 ASYNC module accessing 16bit ASRAM.

This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip enable.
External Connections

External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.90 EMIF1 module accessing 16bit ASRAM as code memory.

This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip enable. This example enables
use of ASRAM as code memory.
External Connections

External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card

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Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.91 EMIF1 module accessing 16bit SDRAM using mem-

cpy_fast_far().
This example configures EMIF1 in 16bit SYNC mode and uses CS0 as chip enable.It will first write to an array
in the SDRAM and then read it back using the FPU function, memcpy_fast_far(), for both operations.
The buffer in SDRAM will be placed in the .farbss memory on account of the fact that its assigned the attribute
"far" indicating it lies beyond the 22-bit program address space. The compiler will take care to avoid using
instructions such as PREAD, which uses the Program Read Bus, or addressing modes restricted to the lower
22-bit space when accessing data with the attribute "far".

Note:
The memory space beyond 22-bits must be treated as data space for load/store operations
only. The user is cautioned against using this space for either instructions or working memory.

External Connections

External SDR-SDRAM memory (MT48LC32M16A2 -75) daughter card

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.92 EMIF1 module accessing 16bit SDRAM then puts into Self
Refresh mode before entering Low Power Mode.
This example configures EMIF1 in 16bit SYNC mode and uses CS0 as chip enable. This example puts SDRAM
into self refresh before entering standby mode. Watchdog timer is configured to trigger WAKEINT interrupt.
As soon as the watchdog timer expires, the device should wake up, SDRAM should come out of self refresh
mode and GPIO11 can be observed to toggle.
External Connections

External SDR-SDRAM memory (MT48LC32M16A2 -75) daughter card

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

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6.93 EMIF1 module accessing 32bit SDRAM using DMA.

This example configures EMIF1 in 16bit SYNC(SDRAM) mode and uses CS0 as chip enable. It will first write
to an array in the SDRAM and then read it back, using the DMA for both operations.
The buffer in SDRAM will be placed in the .farbss memory on account of the fact that its assigned the attribute
"far" indicating it lies beyond the 22-bit program address space. The compiler will take care to avoid using
instructions such as PREAD, which uses the Program Read Bus, or addressing modes restricted to the lower
22-bit space when accessing data with the attribute "far".

Note:
The memory space beyond 22-bits must be treated as data space for load/store operations
only. The user is cautioned against using this space for either instructions or working memory.

External Connections

External SDR-SDRAM (Micron MT48LC32M16A2 "P -75 C") daughter card.

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.94 EMIF1 module accessing 16bit SDRAM using alternate ad-

dress mapping.
This example configures EMIF1 in 16bit SYNC mode and uses CS0 as chip enable.It will first write to an array
in the SDRAM and then read it back.
The buffer in SDRAM will be placed in the emif_cs0_nonfar memory section which is dual mapped with CS2
memory range. This has been done to keep the SDRAM memory range within 22-bit address range in order to
generate optimal code. EMIF1 Async RAM accesses will not be issued at the same time and program space
reads & fetches will be allowed to SDRAM in non-far range.
External Connections

External SDR-SDRAM memory (MT48LC32M16A2 -75) daughter card

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.95 EMIF1 ASYNC module accessing 16bit ASRAM HIC FSI

This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip enable. This can be run with
hic_ex3_config_16bit_fsi example on F28002x device. This is run first followed by the run of F28002x device

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example. This example configures EMIF1 in 16-bit ASYNC mode and uses CS2 as chip enable to access Host
Interface Controller(HIC) on F28002X device
This follows example configuration for performance critical applications described in the Application note titled
"Application guide for peripheral expansion using HIC"(SPRACR2).
-This example sets up the EMIF CS2 for ASRAM interface to access the Host interface Controller. This uses the
Direct Access Mode of the HIC. -The example on F28002x side sets up the FSI module for internal loopback
Sets up the Host interface Controller for direct access mode

Sends a HIC_INIT_DONE_TOKEN after which this example accesses the FSI of the device
side over HIC direct access
Fills the Transmit frame and triggers transmit
Receives an interrupt when the frame is received on the device side FSI(uses GPIO04 con-
nected to HIC_INT, configured for XINT1)
reads the FSI received frame and checks for correctness This demonstrates the usage of
Direct access mode and 16 bit mode of HIC module. External Connections
• This example will not work on F2838x Control Card and has been tested in TI Internal
Validation platform.

Watch Variables

errCountGlobal - Error counter

xint1Count - Number of times HIC Interrupt is received for FSI Receive event

6.96 EMIF1 ASYNC module accessing 8bit HIC controller.

This can be run with hic_ex2_config_8bit example on F28002x device. This is run first followed by the run of
F28002x device. This example configures EMIF1 in 8 bit ASYNC mode and uses CS2 as chip enable to access
Host Interface controller on F28002X device It uses Select Strobe mode of EMIF Controller.
This follows example configuration for pin constrained applications described in the Application note titled Ap-
plication guide for peripheral expansion using HIC(SPRACR2).

This uses 8 bit ASRAM with control signals as explained in the note. uses the Mailbox access
mode of Host interface Controller
This sets up the EMIF waits for HIC_INIT_DONE_TOKEN from device
sends HIC_START_TOKEN to the device to signal the device to start sampling the Analog
channels
The device sends periodic HIC_DATA_TOKEN token
The samples are available in the HIC D2H Buffer
Uses the HIC_INT interrupt from device(which is mapped to GPIO4, XINT1) Refer F28002X
device TRM for further details on HIC.

External Connections

This example will not work on F2838x Control Card and has been tested in TI Internal Valida-
tion platform.

Watch Variables

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sampleCount - Number of samples of data received from device.

xint1Count - Number interrupts received from device.

6.97 Empty Project Example

This example is an empty project setup for Driverlib development.

6.98 ePWM Chopper

This example configures ePWM1, ePWM2, ePWM3 and ePWM4 as follows

ePWM1 with Chopper disabled (Reference)

ePWM2 with chopper enabled at 1/8 duty cycle
ePWM3 with chopper enabled at 6/8 duty cycle
ePWM4 with chopper enabled at 1/2 duty cycle with One-Shot Pulse enabled

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO2 EPWM2A
GPIO3 EPWM2B
GPIO4 EPWM3A
GPIO5 EPWM3B
GPIO6 EPWM4A
GPIO7 EPWM4B

Watch Variables

None.

6.99 EPWM Configure Signal

This example configures ePWM1, ePWM2, ePWM3 to produce signal of desired frequency and duty. It also
configures phase between the configured modules.
Signal of 10kHz with duty of 0.5 is configured on ePWMxA & ePWMxB with ePWMxB inverted. Also, phase of
120 degree is configured between ePWM1 to ePWM3 signals.
During the test, monitor ePWM1, ePWM2, and/or ePWM3 outputs on an oscilloscope.

ePWM1A is on GPIO0
ePWM1B is on GPIO1

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ePWM2A is on GPIO2
ePWM2B is on GPIO3
ePWM3A is on GPIO4
ePWM3B is on GPIO5

6.100 Realization of Monoshot mode

This example showcases how to generate monoshot PWM output based on external trigger i.e. generating just
a single pulse output on receipt of an external trigger. And the next pulse will be generated only when the next
trigger comes. The example utilizes external synchronization and T1 action qualifier event features to achieve
the desired output.
ePWM1 is used to generate the monoshot output and ePWM2 is used an external trigger for that. No external
connections are required as ePWM2A is fed as the trigger using Input X-BAR automatically.
ePWM1 is configured to generated a single pulse of 0.5us when received an external trigger. This is achieved
by enabling the phase synchronization feature and configuring EPWMxSYNCI as EXTSYNCIN1. And this
EPWMxSYNCI is also configured as T1 event of action qualifier to set output HIGH while "CTR = PRD" action
is used to set output LOW.
ePWM2 is configured to generate a 100 KHz signal with a duty of 1% (to simulate a rising edge trigger) which
is routed to EXTSYNCIN1 using Input XBAR.
Observe GPIO0 (EPWM1A : Monoshot Output) and GPIO2(EPWM2 : External Trigger) on oscilloscope.
NOTE : In the following example, the ePWM timer is still running in a continuous mode rather than a one-shot
mode thus for more reliable implementation, refer to CLB based one shot PWM implementation demonstrated
in "clb_ex17_one_shot_pwm" example

6.101 EPWM Action Qualifier (epwm_up_aq)

This example configures ePWM1, ePWM2, ePWM3 to produce an waveform with independent modulation on
EPWMxA and EPWMxB.
The compare values CMPA and CMPB are modified within the ePWM’s ISR.
The TB counter is in up count mode for this example.
View the EPWM1A/B(GPIO0 & GPIO1), EPWM2A/B(GPIO2 & GPIO3) and EPWM3A/B(GPIO4 & GPIO5)
waveforms via an oscilloscope.

6.102 ePWM Trip Zone

This example configures ePWM1 and ePWM2 as follows

ePWM1 has TZ1 as one shot trip source

ePWM2 has TZ1 as cycle by cycle trip source

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Initially tie TZ1 high. During the test, monitor ePWM1 or ePWM2 outputs on a scope. Pull TZ1 low to see the
effect.
External Connections

ePWM1A is on GPIO0
ePWM2A is on GPIO2
TZ1 is on GPIO12

This example also makes use of the Input X-BAR. GPIO12 (the external trigger) is routed to the input X-BAR,
from which it is routed to TZ1.
The TZ-Event is defined such that ePWM1A will undergo a One-Shot Trip and ePWM2A will undergo a Cycle-
By-Cycle Trip.

6.103 ePWM Up Down Count Action Qualifier

This example configures ePWM1, ePWM2, ePWM3 to produce a waveform with independent modulation on
ePWMxA and ePWMxB.
The compare values CMPA and CMPB are modified within the ePWM’s ISR.
The TB counter is in up/down count mode for this example.
View the ePWM1A/B(GPIO0 & GPIO1), ePWM2A/B(GPIO2 &GPIO3) and ePWM3A/B(GPIO4 & GPIO5) wave-
forms on oscilloscope.

6.104 ePWM Synchronization

This example configures ePWM1, ePWM2, ePWM3 and ePWM4 as follows

ePWM1 without phase shift as sync source

ePWM2 with phase shift of 300 TBCLKs
ePWM3 with phase shift of 600 TBCLKs
ePWM4 with phase shift of 900 TBCLKs

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO2 EPWM2A
GPIO3 EPWM2B
GPIO4 EPWM3A
GPIO5 EPWM3B
GPIO6 EPWM4A
GPIO7 EPWM4B

Watch Variables

None.

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6.105 ePWM Digital Compare

This example configures ePWM1 as follows

ePWM1 with DCAEVT1 forcing the ePWM output LOW

GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCAEVT1
GPIO25’s PULL-UP resistor is enabled, in order to test the trip, PULL this pin to GND

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO25 TZ1, pull this pin low to trip the ePWM

Watch Variables

None.

6.106 ePWM Digital Compare Event Filter Blanking Window

This example configures ePWM1 as follows

ePWM1 with DCAEVT1 forcing the ePWM output LOW

GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCAEVT1
GPIO25’s PULL-UP resistor is enabled, in order to test the trip, PULL this pin to GND

ePWM1 with DCBEVT1 forcing the ePWM output LOW

GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCAEVT1
GPIO25’s PULL-UP resistor is enabled, in order to test the trip, PULL this pin to GND
DCBEVT1 uses the filtered version of DCBEVT1
The DCFILT signal uses the blanking window to ignore the DCBEVT1 for the duration of DC
Blanking window

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO25 TRIPIN1, pull this pin low to trip the ePWM

Watch Variables

None.

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6.107 ePWM Valley Switching

This example configures ePWM1 as follows

ePWM1 with DCAEVT1 forcing the ePWM output LOW

GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCAEVT1
GPIO25 is set to output and toggled in the main loop to trip the PWM

ePWM1 with DCBEVT1 forcing the ePWM output LOW

GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCAEVT1
GPIO25 is set to output and toggled in the main loop to trip the PWM
DCBEVT1 uses the filtered version of DCBEVT1
The DCFILT signal uses the valley switching module to delay the
DCFILT signal by a software defined DELAY value.

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO25 TRIPIN1 (Output Pin, toggled through software)

Watch Variables

None.

6.108 ePWM Digital Compare Edge Filter

This example configures ePWM1 as follows

ePWM1 with DCBEVT2 forcing the ePWM output LOW as a CBC source
GPIO25 is used as the input to the INPUT XBAR INPUT1
INPUT1 (from INPUT XBAR) is used as the source for DCBEVT2
GPIO25 is set to output and toggled in the main loop to trip the PWM
The DCBEVT2 is the source for DCFILT
The DCFILT will count edges of the DCBEVT2 and generate a signal to to trip the ePWM on
the 4th edge of DCBEVT2

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO25 TRIPIN1 (Output Pin, toggled through software)

Watch Variables

None.

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6.109 ePWM Deadband

This example configures ePWM1 through ePWM6 as follows

ePWM1 with Deadband disabled (Reference)

ePWM2 with Deadband Active High
ePWM3 with Deadband Active Low
ePWM4 with Deadband Active High Complimentary
ePWM5 with Deadband Active Low Complimentary
ePWM6 with Deadband Output Swap (switch A and B outputs)

External Connections

GPIO0 EPWM1A
GPIO1 EPWM1B
GPIO2 EPWM2A
GPIO3 EPWM2B
GPIO4 EPWM3A
GPIO5 EPWM3B
GPIO6 EPWM4A
GPIO7 EPWM4B
GPIO8 EPWM5A
GPIO9 EPWM5B
GPIO10 EPWM6A
GPIO11 EPWM6B

Watch Variables

None.

6.110 ePWM DMA

This example configures ePWM1 and DMA as follows:

ePWM1 is set up to generate PWM waveforms

DMA5 is set up to update the CMPAHR, CMPA, CMPBHR and CMPB every period with the
next value in the configuration array. This allows the user to create a DMA enabled fifo for all
the CMPx and CMPxHR registers to generate unconventional PWM waveforms.
DMA6 is set up to update the TBPHSHR, TBPHS, TBPRDHR and TBPRD every period with
the next value in the configuration array.
Other registers such as AQCTL can be controlled through the DMA as well by following the
same procedure. (Not used in this example)

External Connections

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GPIO0 EPWM1A
GPIO1 EPWM1B

Watch Variables

None.

6.111 Frequency Measurement Using eQEP

This example will calculate the frequency of an input signal using the eQEP module. ePWM1A is configured to
generate this input signal with a frequency of 5 kHz. It will interrupt once every period and call the frequency
calculation function. This example uses the IQMath library to simplify high-precision calculations.
In addition to the main example file, the following files must be included in this project:

eqep_ex1_calculation.c - contains frequency calculation function

eqep_ex1_calculation.h - includes initialization values for frequency structure

The configuration for this example is as follows

Maximum frequency is configured to 10KHz (baseFreq)

Minimum frequency is assumed at 50Hz for capture pre-scalar selection

SPEED_FR: High Frequency Measurement is obtained by counting the external input pulses for 10ms (unit
timer set to 100Hz).
Count Delta
SP EED_F R =
10ms
SPEED_PR: Low Frequency Measurement is obtained by measuring time period of input edges. Time mea-
surement is averaged over 64 edges for better results and the capture unit performs the time measurement
using pre-scaled SYSCLK.
Note that the pre-scaler for capture unit clock is selected such that the capture timer does not overflow at the
required minimum frequency. This example runs indefinitely until the user stops it.
For more information about the frequency calculation see the comments at the beginning of
eqep_ex1_calculation.c and the XLS file provided with the project, eqep_ex1_calculation.xls.
External Connections

Connect GPIO20/eQEP1A to GPIO0/ePWM1A

Watch Variables

freq.freqHzFR - Frequency measurement using position counter/unit time out

freq.freqHzPR - Frequency measurement using capture unit

6.112 Position and Speed Measurement Using eQEP

This example provides position and speed measurement using the capture unit and speed measurement using
unit time out of the eQEP module. ePWM1 and a GPIO are configured to generate simulated eQEP signals. The

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ePWM module will interrupt once every period and call the position/speed calculation function. This example
uses the IQMath library to simplify high-precision calculations.
In addition to the main example file, the following files must be included in this project:

eqep_ex2_calculation.c - contains position/speed calculation function

eqep_ex2_calculation.h - includes initialization values for position/speed structure

The configuration for this example is as follows

Maximum speed is configured to 6000rpm (baseRPM)

Minimum speed is assumed at 10rpm for capture pre-scalar selection
Pole pair is configured to 2 (polePairs)
Encoder resolution is configured to 4000 counts/revolution (mechScaler)
Which means: 4000 / 4 = 1000 line/revolution quadrature encoder (simulated by ePWM1)
ePWM1 (simulating QEP encoder signals) is configured for a 5kHz frequency or 300 rpm (= 4
∗ 5000 cnts/sec ∗ 60 sec/min) / 4000 cnts/rev)

SPEEDRPM_FR: High Speed Measurement is obtained by counting the QEP input pulses for 10ms (unit timer
set to 100Hz).
SPEEDRPM_FR = (Position Delta / 10ms) ∗ 60 rpm
SPEEDRPM_PR: Low Speed Measurement is obtained by measuring time period of QEP edges. Time mea-
surement is averaged over 64 edges for better results and the capture unit performs the time measurement
using pre-scaled SYSCLK.
Note that the pre-scaler for capture unit clock is selected such that the capture timer does not overflow at the
required minimum frequency. This example runs indefinitely until the user stops it.
For more information about the position/speed calculation see the comments at the beginning of
eqep_ex2_calculation.c and the XLS file provided with the project, eqep_ex2_calculation.xls.
External Connections

Connect GPIO20/eQEP1A to GPIO0/ePWM1A (simulates eQEP Phase A signal)

Connect GPIO21/eQEP1B to GPIO1/ePWM1B (simulates eQEP Phase B signal)
Connect GPIO23/eQEP1I to GPIO2 (simulates eQEP Index Signal)

Watch Variables

posSpeed.speedRPMFR - Speed meas. in rpm using QEP position counter

posSpeed.speedRPMPR - Speed meas. in rpm using capture unit
posSpeed.thetaMech - Motor mechanical angle (Q15)
posSpeed.thetaElec - Motor electrical angle (Q15)

6.113 ePWM frequency Measurement Using eQEP via xbar con-

nection
This example will calculate the frequency of an PWM signal using the eQEP module. ePWM1A is configured
to generate this input signal with a frequency of 5 kHz. This ePWM signal is connected to input of eQEP

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 C28x Driver Library Example Applications

using Input CrossBar and EPWM XBAR. ePWM module will interrupt once every period and call the frequency
calculation function. This example uses the IQMath library to simplify high-precision calculations.
In addition to the main example file, the following files must be included in this project:

eqep_ex1_calculation.c - contains frequency calculation function

eqep_ex1_calculation.h - includes initialization values for frequency structure

The configuration for this example is as follows

Maximum frequency is configured to 10KHz (baseFreq)

Minimum frequency is assumed at 50Hz for capture pre-scalar selection
GPIO0 is connected to output of INPUT_XBAR1
INPUT_XBAR1 is connected to output of PWMXBAR at TRIP4
eQEPA source is configured as PWMXBAR.1 output (TRIP4)

SPEED_FR: High Frequency Measurement is obtained by counting the external input pulses for 10ms (unit
timer set to 100Hz).
Count Delta
SP EED_F R =
10ms

SPEED_PR: Low Frequency Measurement is obtained by measuring time period of input edges. Time mea-
surement is averaged over 64 edges for better results and the capture unit performs the time measurement
using pre-scaled SYSCLK.
Note that the pre-scaler for capture unit clock is selected such that the capture timer does not overflow at the
required minimum frequency. This example runs indefinitely until the user stops it.
For more information about the frequency calculation see the comments at the beginning of
eqep_ex1_calculation.c and the XLS file provided with the project, eqep_ex1_calculation.xls.
Watch Variables

freq.freqHzFR - Frequency measurement using position counter/unit time out

freq.freqHzPR - Frequency measurement using capture unit

6.114 Frequency Measurement Using eQEP via unit timeout inter-

rupt
This example will calculate the frequency of an input signal using the eQEP module. ePWM1A is configured to
generate this input signal with a frequency of 5 kHz. EQEP unit timeout is set which will generate an interrupt
every UNIT_PERIOD microseconds and frequency calculation occurs continuously
The configuration for this example is as follows

PWM frequency is specified as 5000Hz

UNIT_PERIOD is specified as 10000 us
Min frequency is (1/(2∗10ms)) i.e 50Hz
Highest frequency can be (2∧ 32)/ ((2∗10ms))
Resolution of frequency measurement is 50hz

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freq : Frequency Measurement is obtained by counting the external input pulses for UNIT_PERIOD (unit timer
set to 10 ms).
External Connections

Connect GPIO20/eQEP1A to GPIO0/ePWM1A

Watch Variables

freq - Frequency measurement using position counter/unit time out

pass - If measured frequency matches with PWM frequency then pass = 1 else 0

6.115 Motor speed and direction measurement using eQEP via

unit timeout interrupt
This example can be used to sense the speed and direction of motor using eQEP in quadrature encoder mode.
ePWM1A is configured to simulate motor encoder signals with frequency of 5 kHz on both A and B pins with 90
degree phase shift (so as to run this example without motor). EQEP unit timeout is set which will generate an
interrupt every UNIT_PERIOD microseconds and speed calculation occurs continuously based on the direction
of motor
The configuration for this example is as follows

PWM frequency is specified as 5000Hz

UNIT_PERIOD is specified as 10000 us
Simulated quadrature signal frequency is 20000Hz (4 ∗ 5000)
Encoder holes assumed as 1000
Thus Simulated motor speed is 300rpm (5000 ∗ (60 / 1000))

freq : Simulated quadrature signal frequency measured by counting the external input pulses for UNIT_PERIOD
(unit timer set to 10 ms). speed : Measure motor speed in rpm dir : Indicates clockwise (1) or anticlockwise
(-1)
External Connections (if motor encoder signals are simulated by ePWM)

Connect GPIO20/eQEP1A to GPIO0/ePWM1A

Connect GPIO21/eQEP1B to GPIO1/ePWM1B With motor
Comment in "MOTOR" in includes
Connect GPIO20/eQEP1A to encoder A output
Connect GPIO21/eQEP1B to encoder B output

Watch Variables

freq : Simulated motor frequency measurement is obtained by counting the external input
pulses for UNIT_PERIOD (unit timer set to 10 ms).
speed : Measure motor speed in rpm
dir : Indicates clockwise (1) or anticlockwise (-1)
pass - If measured qudrature frequency matches with i.e. input quadrature frequency (4 ∗
PWM frequency) then pass = 1 else fail = 1 (∗∗ only when "MOTOR" is commented out)

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6.116 ERAD Profile Function

This example uses BUSCOMP1, BUSCOMP2 and COUNTER1 of the ERAD module to profile a function (delay-
Function). It calculates the CPU cycles taken between the the start address of the function to the end address
of the function
Two dummy variable are written to inside the function - startCount and endCount. BUSCOMP3, BUSCOMP4
and COUNTER2 are used to profile the time taken between the access to startCount variable till the access to
endCount variable.
Both the counters are setup to operate in START-STOP mode and count the number of CPU cycles spend
between the respective bus comparator events.
Watch Variables

cycles_Function - the maximum number of cycles between the start of function to the end of
function
cycles_Data - the maximum number of cycles taken between accessing startCount variable to
endCount variable

External Connections
None

6.117 ERAD Profile Function

This example uses BUSCOMP1, BUSCOMP2 and COUNTER1 of the ERAD module to profile a function (delay-
Function). It calculates the CPU cycles taken between the the start address of the function to the end address
of the function
Two dummy variable are written to inside the function - startCount and endCount. BUSCOMP3, BUSCOMP4
and COUNTER2 are used to profile the time taken between the access to startCount variable till the access to
endCount variable.
Both the counters are setup to operate in START-STOP mode and count the number of CPU cycles spend
between the respective bus comparator events.
Watch Variables

cycles_Function - the maximum number of cycles between the start of function to the end of
function
cycles_Data - the maximum number of cycles taken between accessing startCount variable to
endCount variable

External Connections
None

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6.118 ERAD HWBP Monitor Program Counter

In this example, the function delayFunction is called multiple times. The function does read and writes to the
global variables startCount and endCount.
The BUSCOMP1 and COUNTER1 is used to count the number of times the function delayFunction was in-
voked. BUSCOMP2 is used to generate an interrupt when there is read access to the startCount variable and
BUSCOMP3 is used to generate an interrupt when there is a write access to the endCount variable
Watch Variables

funcCount - number of times the function delayFunction was invoked

isrCount - number of times the ISR was invoked

External Connections

None

6.119 ERAD HWBP Monitor Program Counter

In this example, the function delayFunction is called multiple times. The function does read and writes to the
global variables startCount and endCount.
The BUSCOMP1 and COUNTER1 is used to count the number of times the function delayFunction was in-
voked. BUSCOMP2 is used to generate an interrupt when there is read access to the startCount variable and
BUSCOMP3 is used to generate an interrupt when there is a write access to the endCount variable
Watch Variables

funcCount - number of times the function delayFunction was invoked

isrCount - number of times the ISR was invoked

External Connections

None

6.120 ERAD HWBP Stack Overflow Detection

This example uses BUSCOMP1 to monitor the stack. The Bus comparator is set to monitor the data write access
bus and generate an RTOS interrupt CPU when a write is detected to end of the STACK within a threshold.
Watch Variables

functionCallCount - the number of times the recursive function overflowing the STACK is called.
x indicates that the ISR has been entered

External Connections
None

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6.121 ERAD HWBP Stack Overflow Detection

This example uses BUSCOMP1 to monitor the stack. The Bus comparator is set to monitor the data write access
bus and generate an RTOS interrupt CPU when a write is detected to end of the STACK within a threshold.
Watch Variables

functionCallCount - the number of times the recursive function overflowing the STACK is called.
x indicates that the ISR has been entered

External Connections
None

6.122 ERAD Profiling Interrupts

This example shows how an ISR can be profiled by ERAD. The CPU timer generates interrupts periodically. We
set up the counters to count the CPU cycles elapsed while executing the ISR, to count the number of interrupts,
the number of ISR executions and the CPU cycles elapsed between the interrupt and the execution of the ISR.
This example uses 2 bus comparators and 4 counters:

BUSCOMP_1 : PC = start address of cpuTimer1ISR

BUSCOMP_2 : PC = address of cpuTimer1IntCount variable access. This specifies the end
address of the code of interest.
COUNTER_1 : Used to count the cpuTimer1ISR execution cycles. Configured in start-stop
mode with start event as BUSCOMP_1 and stop event as BUSCOMP_2
COUNTER_2 : Used to count the number of times the system event TIMER1_TINT1
has occurred. Configured in rising-edge count mode with counting input as system event
TIMER1_TINT1
COUNTER_3 : Used to count the number of times cputTimer2ISR executes. Configured in
rising-edge count mode with counting input as BUSCOMP_1
COUNTER_4 : Used to count the latency from the system event TIMER1_TINT1 to
cpuTimer1ISR entry. Configured in start-stop mode with start event as TIMER1_TINT1 and
stop event as BUSCOMP_1

We configure the COUNTER1 to generate an interrupt once it reaches a threshold value.

External Connections

None

Profiling Output

Current ISR cycle count (COUNTER_1)

Interrupt occurrence count (COUNTER_2)
ISR execution count (COUNTER_3)
ISR entry delay cycle count (maximum value of COUNTER_4)
x - To show that the ISR executed

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6.123 ERAD Profiling Interrupts

This example shows how an ISR can be profiled by ERAD. The CPU timer generates interrupts periodically. We
set up the counters to count the CPU cycles elapsed while executing the ISR, to count the number of interrupts,
the number of ISR executions and the CPU cycles elapsed between the interrupt and the execution of the ISR.
This example uses 2 bus comparators and 4 counters:

BUSCOMP_1 : PC = start address of cpuTimer1ISR

BUSCOMP_2 : PC = address of cpuTimer1IntCount variable access. This specifies the end
address of the code of interest.
COUNTER_1 : Used to count the cpuTimer1ISR execution cycles. Configured in start-stop
mode with start event as BUSCOMP_1 and stop event as BUSCOMP_2
COUNTER_2 : Used to count the number of times the system event TIMER1_TINT1
has occurred. Configured in rising-edge count mode with counting input as system event
TIMER1_TINT1
COUNTER_3 : Used to count the number of times cputTimer2ISR executes. Configured in
rising-edge count mode with counting input as BUSCOMP_1
COUNTER_4 : Used to count the latency from the system event TIMER1_TINT1 to
cpuTimer1ISR entry. Configured in start-stop mode with start event as TIMER1_TINT1 and
stop event as BUSCOMP_1

We configure the COUNTER1 to generate an interrupt once it reaches a threshold value.

External Connections

None

Profiling Output

Current ISR cycle count (COUNTER_1)

Interrupt occurrence count (COUNTER_2)
ISR execution count (COUNTER_3)
ISR entry delay cycle count (maximum value of COUNTER_4)
x - To show that the ISR executed

FILE: erad_ex5_restricted_write_detect.c
TITLE: erad_ex5_restrictedwrite_detect

6.124 ERAD MEMORY ACCESS RESTRICT

This example uses BUSCOMP1 to monitor the Data Write Address Bus. It monitors the bus and generates an
RTOS interrupt if a certain region of memory is accessed by the PC. The user may disable the Bus Comparator
to access that region.
Use the COM port (Baud=9600) to try to write to the restricted area.
Watch Variables

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x : stores the number of times the region of memory is accessed

External Connections

None

#############################################################################
FILE: erad_ex6_interrupt_order.c
TITLE: ERAD INTERRUPT ORDER

6.125 ERAD INTERRUPT ORDER

This example uses a COUNTER to monitor the sequence of ISRs executed. An interrupt is generated if the
ISRs executed are not in the expected order. The expected order is CPUTimer0 ,then CPUTimer1 and then
CPUTimer2
The counter is configured in Start-Stop Mode to count the number of times CPUTimer interrupt occurs between
the CPUTimer1 interrupt and CPUTimer2 ISRs. Ideally, this count should be zero if the interrupts are occurring
in the expected order. we configure a threshold value of 1 to generate an RTOS interrupt. This indicates that
the CPUTimer2 interrupt has come out of order.
For demonstration purposes, this example disables CPUTimer1 to simulate this error.
Watch Variables

cpuTimer0IntCount: Number of executions of ISR0

cpuTimer1IntCount: Number of executions of ISR1
cpuTimer2IntCount: Number of executions of ISR2

External Connections

None

6.126 ERAD AND CLB

This example uses 4 BUS COMPARATORS of ERAD along with the CLB. One bus comparator monitors a write
to x, another one monitors a write to y. The other two monitor a write of 0x1 and 0x0. By using the LUTs in the
CLB1 tile, we can monitor a write of 0x1 to x or 0x0 to x. These are used to change the state of FSM2 in the
CLB1 tile. If y is accessed before writing a 0x1 to x, an interrupt is generated and y is changed to 0x0 again.
The LED2 indicates when access to y is allowed(it is off at this point) The LED1 indicates if an invalid access is
attempted. A COUNTER in ERAD is used to count the number of access attempts to y.
Watch Variables

y
x
a - counts the number of access attempts to y

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External Connections
None

6.127 ERAD PWM PROTECTION

This example uses a BUS COMPARATOR and the CLB to detect the event when the delay between the interrupt
and the ISR execution is longer than expected. The PWM output is also tripped in this case.
Watch Variables

adcAResults stores the results of the conversions from the ADC

External Connections

Monitor the PWM output (GPIO0)

6.128 ERAD Profiling Interrupts

This example configures CPU Timer0, 1, and 2 to be profiled using the ERAD module. Included is a JavaScript
file, profile_interrupts.js, which is used with the scripting console to program ERAD registers and view profiling
data.
To properly use the provided ERAD script, the following variables must be set in the scripting environment prior
to launching the ERAD script:

var PROJ_NAME = "erad_debugger_ex1_profileinterrupts"

var PROJ_WKSPC_LOC = "<proj_workspace_path>"
var PROJ_CONFIG = "<name of active configuration [CPU1_FLASH|CPU1_RAM]>"

To run the ERAD script, use the following command in the scripting console:

loadJSFile("<proj_workspace_path>\\erad_debugger_ex1_profileinterrupts\\erad_ex1_profile_interrupts.js
0);

The included JavaScript file, erad_ex1_profile_interrupts.js, uses Debug Server Script-

ing (DSS) features. For information on using the DSS, please visit: http://software-
dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html
Note that the script must be run after loading and running the .out on the C28x core. Only CPU timer 2 ISR is
profiled in this example.
This example uses 2 HW breakpoints and 4 counters:

HWBP_1 : PC = start address of cpuTimer2ISR

HWBP_2 : PC = end address of cpuTimer2ISR
CTM_1 : Used to count the cpuTimer2ISR execution cycles. Configured in start-stop mode
with start event as HWBP_1 and stop event as HWBP_2

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CTM_2 : Used to count the number of times the system event TIMER2_TINT2 has occurred.
Configured in rising-edge count mode with counting input as system event TIMER2_TINT2
(INP_SEL[25])
CTM_3 : Used to count the number of times cputTimer2ISR executes. Configured in rising-
edge count mode with counting input as HWBP_1 (INP_SEL[0])
CTM_4 : Used to count the latency from the system event TIMER2_TINT2 to cpuTimer2ISR
entry. Configured in start-stop mode with start event as TIMER2_TINT2 and stop event as
HWBP_1

External Connections

None

Watch Variables

cpuTimer0IntCount
cpuTimer1IntCount
cpuTimer2IntCount

Profiling Script Output

Current ISR cycle count (CTM_1)

Max ISR cycle count (maximum value of CTM_1)
Interrupt occurrence count (CTM_2)
ISR execution count (CTM_3)
ISR entry delay cycle count (maximum value of CTM_4)

Note that the large difference between Interrupt occurrence count (CTM_2) and ISR execution count (CTM_3)
is because the ISR takes more number of cycles than the actual interrupt period. ISR entry delay cycle count
will also be higher due to the same reason.

6.129 ERAD Profile Function

This example contains a basic FIR calculation and sorting algorithm to help demonstrate the function profiling
capability of the ERAD peripheral. A number of FIR sums are calculated within a loop and are then sorted using
the insertion sort algorithm. Cycle counts of both the FIR calculations and the sorting algorithm are output to the
screen through the scripting console. In this example, it can be seen that sorting the data takes up a majority of
the CPU cycles executed in this program.
To properly use the provided ERAD script, the following variables must be set in the scripting environment prior
to launching the ERAD script:

var PROJ_NAME = "erad_debugger_ex2_profilefunction"

var PROJ_WKSPC_LOC = "<proj_workspace_path>"
var PROJ_CONFIG = "<name of active configuration [CPU1_FLASH|CPU1_RAM]>"

To run the ERAD script, use the following command in the scripting console:

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loadJSFile("<proj_workspace_path>\\erad_debugger_ex2_profilefunction\\erad_ex2_profile_function.js",
0);

Note that the script must be run after loading and running the .out on the C28x core.
The included JavaScript file, erad_ex2_profile_function.js, uses Debug Server Script-
ing (DSS) features. For information on using the DSS, please visit: http://software-
dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html
This example uses 4 HW breakpoints and 2 counters:

HWBP_1 : PC = start address of performFIR

HWBP_2 : PC = end address of performFIR
HWBP_3 : PC = start address of sortMax
HWBP_4 : PC = end address of sortMax
CTM_1 : Used to count the performFIR execution cycles. Configured in start-stop mode with
start event as HWBP_1 and stop event as HWBP_2
CTM_2 : Used to count the sortMax execution cycles. Configured in start-stop mode with start
event as HWBP_3 and stop event as HWBP_4

External Connections

None.

Watch Variables

FIR_iterationCounter - A counter for the number of times FIR calculation and sorting was
performed

Profiling Script Output

Current FIR cycle count (CTM_1)

Max FIR cycle count (maximum value of CTM_1)
Current sorting function cycle count (CTM_2)
Max sorting function cycle count (maximum value of CTM_2)

Note that the the counters are reset after the stop event. The counter value remains 0 till the next start event
occurs. The javascript continuously reads the counter value in a while(1) and hence the current counter may
return 0.

6.130 ERAD Stack Overflow

This example shows the basic setup of CAN in order to transmit and receive messages on the CAN bus. The
CAN peripheral is configured to transmit messages with a specific CAN ID. A message is then transmitted once
per second, using a simple delay loop for timing. The message that is sent is a 2 byte message that contains
an incrementing pattern.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core.

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A buffer is created to store message history up to 50 messages for the duration of the program. A logic error is
intentionally made to allow the buffer to overflow, eventually causing a stack overflow. The included JavaScript
file, stack_overflow.js, programs ERAD registers in order to detect the stack overflow and halt the CPU once the
illegal write is made. The illegal write is made after 507 messages are received.
To properly use the provided ERAD script, the following variables must be set in the scripting environment prior
to launching the ERAD script:

var PROJ_NAME = "erad_debugger_ex3_stackoverflow"

var PROJ_WKSPC_LOC = <proj_workspace_path>

To run the ERAD script, use the following command in the scripting console:

loadJSFile("<proj_workspace_path>\\erad_debugger_ex3_stackoverflow\\erad_ex3_stack_overflow.js",
0);

Note that the script must be run after loading and running the .out on the C28x core.
The included JavaScript file, erad_ex3_stack_overflow.js, uses Debug Server Script-
ing (DSS) features. For information on using the DSS, please visit: http://software-
dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html
This example uses 1 HW watchpoint :

HWBP_1 : Data Write Address Bus = Stack end address + 1

External Connections

None.

Watch Variables

msgCount - A counter for the number of successful messages received

txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
msgHistoryBuff - An array meant to store the last 50 messages received

Profiling Script Output

"STACK OVERFLOW detected. Halting CPU." will be printed in the scripting console when a
stack overflow occurs (that is, when the watchpoint is hit)

6.131 ERAD Profile Interrupts CLA

This example configures EPWM1A to run at 1 KHz (period = 1 ms) to trigger a start-of-conversion on ADC
channel A0. This channel will, in turn, sample EPWM4A which is set to run at 100Hz. At the end-of-conversion
the ADC interrupt is fired. The interrupt signal will be used to trigger a CLA task that runs an FIR filter. The
filter is designed to be low pass with a cutoff frequency of 100Hz; it will remove the odd harmonics in the input
signal smoothing the square wave to a sinusoidal shape. The CLA background task will continuously buffer the
filtered output in a circular buffer.

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This example also utilizes the ERAD peripheral to profile the Interrupt Service Routine (ISR) cla1ISR1 (on the
C28x core). The ISR contains a loop that simulates storing a random amount of data to a location in order to
introduce variability into the cycle measurements. The ERAD peripheral is also configured to count the number
of times the system event CLA_INTERRUPT1 occurs.
To properly use the provided ERAD script, the following variables must be set in the scripting environment prior
to launching the ERAD script:

var PROJ_NAME = "erad_debugger_ex4_profileinterrupts_cla"

var PROJ_WKSPC_LOC = "<proj_workspace_path>"
var PROJ_CONFIG = "<name of active configuration [CPU1_FLASH|CPU1_RAM]>"

To run the ERAD script, use the following command in the scripting console:

loadJSFile("<proj_workspace_path>\\erad_debugger_ex4_profileinterrupts_cla\\erad_ex4_profile_interrup
0);

Note that the script must be run after loading and running the .out on the C28x core.
The included JavaScript file, erad_ex4_profile_interrupts_cla.js, uses Debug Server Script-
ing (DSS) features. For information on using the DSS, please visit: http://software-
dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html
This example uses 4 HW breakpoints and 2 counters:

HWBP_1 : PC = start address of cla1Isr1

HWBP_2 : PC = end address of cla1Isr1
CTM_1 : Used to count the cla1Isr1 execution cycles. Configured in start-stop mode with start
event as HWBP_1 and stop event as HWBP_2
CTM_2 : Used to count the number of times the system event CLA_INTERRUPT1 event
has occurred. Configured in rising-edge count mode with counting input as system event
CLA_INTERRUPT1 (INP_SEL[26])

External Connections

connect A0 to EPWM4A

Watch Variables

ISR_count - A counter that signifies how many times cla1ISR1 executes

Profiling Script Output

Current ISR cycle count (CTM_1)

Max ISR cycle count (maximum value of CTM_1)
Interrupt occurrence count (CTM_2)

6.132 Flash ECC Test Mode

This example demonstrates ECC Test mode.

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6.133 Flash Programming with AutoECC, DataAndECC, DataOnly

and EccOnly
This example demonstrates how to program Flash using API’s following options 1. AutoEcc generation 2.
DataOnly and EccOnly 3. DataAndECC
External Connections

None.

Watch Variables

None.

6.134 FSI daisy chain topology, lead device example

fsi_ex16_daisy_handshake_lead is for the lead device in the daisy-chain loop, fsi_ex16_daisy_handshake_node
for the other N-1 devices(N>=2).
In the code, there are different settings provided: [define FSI_DMA_ENABLE 0] represents FSI communication
using CPU control. [define FSI_DMA_ENABLE 1] represents FSI communication using DMA control, enabling
FSIRX to trigger a DMA event and move the RX FSI data to the TX FSI buffer
In a real scenario two separate devices may power up in arbitrary order and there is a need to establish a clean
communication link which ensures that receiver side is flushed to properly interpret the start of a new valid
frame.
The node devices in the daisy chain topology respond to the handshake sequence and forwards the information
to the next device in the chain.
After above synchronization steps, FSI Rx can be configured as per use case i.e. nWords, lane width, enabling
events, etc and start the infinite transfers. More details on establishing the communication link can be found in
the device TRM.
User can edit some of configuration parameters as per use case, similar to other examples.
nWords - Number of words per transfer may be from 1 -16 nLanes - Choice to select single or double lane for
frame transfers txUserData - User data to be sent with Data frame txDataFrameTag - Frame tag used for Data
transfers txPingFrameTag - Frame tag used for Ping transfers txPingTimeRefCntr - Tx Ping timer reference
counter rxWdTimeoutRefCntr - Rx Watchdog timeout reference counter
External Connections
For the FSI daisy-chain topology external connections are required to be made between the devices in the
chain. Each devices FSI TX pins need to be connected to the FSI RX pins of the next device in the chain (or
ring). See below for external connections to include and GPIOs used:
External Connections Required:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

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GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frames received back

error Non zero for transmit/receive data mismatch

6.135 FSI daisy chain topology, node device example

fsi_ex16_daisy_handshake_lead is for the lead device in the daisy-chain loop, fsi_ex16_daisy_handshake_node
for the other N-1 devices(N>=2).
In the code, there are different settings provided: [define FSI_DMA_ENABLE 0] represents FSI communication
using CPU control. [define FSI_DMA_ENABLE 1] represents FSI communication using DMA control, enabling
FSIRX to trigger a DMA event and move the RX FSI data to the TX FSI buffer
In a real scenario two separate devices may power up in arbitrary order and there is a need to establish a clean
communication link which ensures that receiver side is flushed to properly interpret the start of a new valid
frame.
The node devices in the daisy chain topology respond to the handshake sequence and forwards the information
to the next device in the chain.
After above synchronization steps, FSI Rx can be configured as per use case i.e. nWords, lane width, enabling
events, etc and start the infinite transfers. More details on establishing the communication link can be found in
the device TRM.
User can edit some of configuration parameters as per use case, similar to other examples.
nWords - Number of words per transfer may be from 1 -16 nLanes - Choice to select single or double lane for
frame transfers txUserData - User data to be sent with Data frame txDataFrameTag - Frame tag used for Data
transfers txPingFrameTag - Frame tag used for Ping transfers txPingTimeRefCntr - Tx Ping timer reference
counter rxWdTimeoutRefCntr - Rx Watchdog timeout reference counter
External Connections
For the FSI daisy-chain topology external connections are required to be made between the devices in the
chain. Each devices FSI TX pins need to be connected to the FSI RX pins of the next device in the chain (or
ring). See below for external connections to include and GPIOs used:
External Connections Required:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

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GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frames received back

error Non zero for transmit/receive data mismatch

6.136 FSI Loopback:CPU Control

Example sets up infinite data frame transfers where trigger happens through CPU. Automatic(Hw triggered)
Ping frame transmission is also setup along with data.
User can edit some of configuration parameters as per usecase. These are as below. Default values can be
referred in code where these globals are defined

nWords - Number of words per transfer may be from 1 -16

nLanes - Choice to select single or double lane for frame transfers
fsiClock - FSI Clock used for transfers
txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers
txPingFrameTag - Frame tag used for Ping transfers
txPingTimeRefCntr - Tx Ping timer reference counter
rxWdTimeoutRefCntr - Rx Watchdog timeout reference counter

For any errors during transfers i.e. error events such as Frame Overrun, Underrun, Watchdog timeout and
CRC/EOF/TYPE errors, execution will stop immediately and status variables can be looked into for more details.
Execution will also stop for any mismatch between received data and sent ones and also if transfers takes
unusually long time(detected through software counters - txTimeOutCntr and rxTimeOutCntr)
External Connections
For FSI internal loopback (EXTERNAL_FSI_ENABLE == 0), no external connections needed
For FSI external loopback (EXTERNAL_FSI_ENABLE == 1), external connections are required. The FSI TX
pins should be connected to the FSI RX pins of the same device. See below for external connections to include
and GPIOs used:
External Connections Required between FSI TX and RX of the same device:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

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GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

6.137 FSI Loopback CLA control

Example sets up infinite data frame transfers where trigger happens through CLA. Automatic(Hw triggered)
Ping frame transmission is also setup along with data. This example is similar to fsi_ex1_loopback_cpucontrol
and only different in in the sense that data frame transfer are trigged from a CLA task. Using CLA will release
some of load from CPU and help it in providing time for other tasks.
User can edit some of configuration parameters as per usecase. These are as below. Default values can be
referred in code where these globals are defined

nWords - Number of words per transfer may be from 1 -16

nLanes - Choice to select single or double lane for frame transfers
fsiClock - FSI Clock used for transfers
txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers
txPingFrameTag - Frame tag used for Ping transfers
txPingTimeRefCntr - Tx Ping timer reference counter
rxWdTimeoutRefCntr - Rx Watchdog timeout reference counter

For any errors during transfers i.e. error events such as Frame Overrun, Underrun, Watchdog timeout and
CRC/EOF/TYPE errors, execution will stop immediately and status variables can be looked into for more details.
Execution will also stop for any mismatch between received data and sent ones and also if transfers takes
unusually long time(detected through software counters - txTimeOutCntr and rxTimeOutCntr)
External Connections
For FSI internal loopback (EXTERNAL_FSI_ENABLE == 0), no external connections needed
For FSI external loopback (EXTERNAL_FSI_ENABLE == 1), external connections are required. The FSI TX
pins should be connected to the respective FSI RX pins of the same device. See below for external connections
to include and GPIOs used:
External Connections Required between FSI TX and RX of the same device:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0

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FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

6.138 FSI DMA frame transfers:DMA Control

Example sets up infinite data frame transfers where DMA trigger happens once through CPU and then DMA
takes control to transfer data iteratively. This example demonstrates the FSI feature about triggering DMA
events which in turn can copy data and trigger next transfer.
Two DMA channels are setup for FSI Tx operation and two for Rx. Four areas in GSx memories are also setup
as source and sink for data and tag values of frame under transmission.
Automatic(Hw triggered) Ping frame transmission is also setup along with data.
If there are any comparison failures during transfers or any error event occurs, execution will stop.
User Configurations: If "Software Frame Size" is modified in FSI TX or FSI RX Sysconfig, change: DMA CH0
"Destination Wrap Size" DMA CH0 "Burst Size" DMA CH2 "Source Wrap Size" DMA CH2 "Burst Size" FSI
TX/RX "Software Frame Size"

Note:
: This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections
For FSI internal loopback (default setting), no external connections needed
For FSI external loopback (disable "Loopback Mode" in FSI RX Sysconfig), external connections are required.
Refer to SysConfig for external connections (GPIO pin numbers) specific to each device.
Watch Variables

countDMAtransfers Number of Data frame transfered

error Non zero for transmit/receive data mismatch

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6.139 FSI data transfer by external trigger

FSI frame transfer can be triggered by external sources. It can connect up to 32 trigger sources but as of now,
only 16 ePWMx-SOCy(x-1:8, y-A:B) are supported. FSI supports external trigger for both PING and DATA frame
transfers and in this example we demonstrate how to setup infinite DATA transfers using selectable ePWM-SOC
as a trigger source. The TB counter for ePWM operation is in up/down count mode for this example.
Automatic(Hw triggered) Ping frame transmission is also setup along with data.
If there are any comparison failures during transfers or any of error event occurs, execution will stop.
External Connections
For FSI internal loopback (EXTERNAL_FSI_ENABLE == 0), no external connections needed
For FSI external loopback (EXTERNAL_FSI_ENABLE == 1), external connections are required. The FSI TX
pins should be connected to the respective FSI RX pins of the same device. See below for external connections
to include and GPIOs used:
External Connections Required between FSI TX and RX of the same device:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

6.140 FSI data transfers upon CPU Timer event

Example sets up infinite data frame transfers where trigger comes from ISR handling the periodic CPU Timer
event. Automatic(Hw triggered) Ping frame transmission is also setup along with data.
CPU Timer0 is chosen for setting up periodic timer events. User can choose any other Timer-1/Timer-2 as well.
Automatic(Hw triggered) Ping frame transmission is also setup along with data.
If there are any comparison failures during transfers or any of error event occurs, execution will stop.
External Connections
For FSI internal loopback (EXTERNAL_FSI_ENABLE == 0), no external connections needed

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For FSI external loopback (EXTERNAL_FSI_ENABLE == 1), external connections are required. The FSI TX
pins should be connected to the respective FSI RX pins of the same device. See below for external connections
to include and GPIOs used:
External Connections Required between FSI TX and RX of the same device:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

6.141 FSI and SPI communication(fsi_ex6_spi_main_tx)

FSI supports SPI compatibility mode to talk to the devices not having FSI but SPI module. Example sets up
infinite data frame transfers where FSI acts like main Tx and SPI as remote Rx. API to decode FSI frame
received at SPI end is implemented and checks are made to ensure received details(frame tag/type, userdata,
data) match with transfered frame.
If there are any comparison failures during transfers or any of error event occurs, execution will stop.
External Connections
For FSI <-> SPI communication, make below connections in GPIO settings

GPIO_2 -> GPIO_18 :: To connect FSITX_CLK with SPICLKA

GPIO_0 -> GPIO_16 :: To connect FSITX_TX0 with SPIPICOA
GPIO_1 -> GPIO_19 :: To connect FSITX_TX1 with SPIPTEA

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

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6.142 FSI and SPI communication(fsi_ex7_spi_remote_rx)

FSI supports SPI compatibility mode to talk to the devices not having FSI but SPI module. Example sets up
infinite data frame transfers where FSI acts like remote Rx and SPI as main Rx. API to build the FSI frame at
SPI end before transfer is implemented in SW and checks are made to ensure received details(frame tag/type,
userdata, data) on FSI Rx match with transferred data.
If there are any comparison failures during transfers or any of error event occurs, execution will stop.
External Connections
For FSI(Rx) <-> SPI(Tx) communication, make connections in GPIO settings
There is no requirement for a chip select signal to be used when connected to the FSIRX. This is because the
FSIRX will respond to any incoming clock edge.

GPIO_13 -> GPIO_18 :: To connect FSIRXCLKA with SPICLKA

GPIO_12 -> GPIO_16 :: To connect FSIRXD0A with SPIPICOA

Watch Variables

dataFrameCntr Number of Data frame transfered

error Non zero for transmit/receive data mismatch

6.143 FSI P2Point Connection:Rx Side

Example sets up FSI receiving device in a point to point connection to the FSI transmitting device. Example
code to set up FSI transmit device is implemented in a separate file.
In a real scenario two separate devices may power up in arbitrary order and there is a need to establish a clean
communication link which ensures that receiver side is flushed to properly interpret the start of a new valid
frame.
There is no true concept of a main or a remote node in the FSI protocol, but to simplify the data flow and
connection we can consider transmitting device as main and receiving side as remote. Transmitting side will be
driver of initialization sequence.
Handshake mechanism which must take place before actual data transmission can be usecase specific; points
described below can be taken as an example on how to implement the handshake from receiving side -

Setup the receiver interrupts to detect PING type frame reception

Begin the first PING loop + Wait for receiver interrupt + If the FSI Rx has received a PING
frame with FSI_FRAME_TAG0, come out of loop. Otherwise iterate the loop again.
Begin the second PING loop + Send the Flush sequence + Send the PING frame with tag +
Wait for receiver interrupt + If the FSI Rx has received a PING frame with FSI_FRAME_TAG1,
come out of loop. Otherwise iterate the loop again.
• Now, the receiver side has received the acknowledged PING frame(tag1), so it is ready
for normal operation further.

After above synchronization steps, FSI Rx can be configured as per usecase i.e. nWords, lane width, enabling
events etc and start the infinite transfers. More details on establishing the communication link can be found in
device TRM.

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User can edit some of configuration parameters as per usecase, similar to other examples.
nWords - Number of words per transfer may be from 1 -16 nLanes - Choice to select single or double lane
for frame transfers fsiClock - FSI Clock used for transfers txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers txPingFrameTag - Frame tag used for Ping transfers
txPingTimeRefCntr - Tx Ping timer reference counter rxWdTimeoutRefCntr - Rx Watchdog timeout reference
counter
External Connections
For FSI external P2P connection, external connections are required to be made between two devices. Device
1’s FSI TX and RX pins need to be connected to device 2’s FSI RX and TX pins respectively. See below for
external connections to make and GPIOs used:
External connections required between independent RX and TX devices:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame received

error Non zero for transmit/receive data mismatch

6.144 FSI P2Point Connection:Tx Side

Example sets up FSI transmitting device in a point to point connection to the FSI receiving device. Example
code to set up FSI receiving device is implemented in a separate file.
In a real scenario two separate devices may power up in arbitrary order and there is a need to establish a clean
communication link which ensures that receiver side is flushed to properly interpret the start of a new valid
frame.
There is no true concept of a main or a remote node in the FSI protocol, but to simplify the data flow and
connection we can consider transmitting device as main and receiving side as remote. Transmitting side will be
driver of initialization sequence.
Handshake mechanism which must take place before actual data transmission can be usecase specific; points
described below can be taken as an example on how to implement the handshake from transmitting side -

Setup the receiver interrupts to detect PING type frame reception

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Begin the PING loop + Send the Flush sequence + Send a PING frame with the frame tag
FSI_FRAME_TAG0 + Wait for some time(determined by application) + If the FSI Rx has re-
ceived a PING frame with FSI_FRAME_TAG1, come out of loop. Otherwise iterate the loop
again
• Send a PING frame with the frame tag FSI_FRAME_TAG1

After above synchronization steps, FSI Tx can be configured as per usecase i.e. nWords, lane width, enabling
events etc and start the infinite transfers. More details on establishing the communication link can be found in
device TRM.
User can edit some of configuration parameters as per usecase, similar to other examples.
nWords - Number of words per transfer may be from 1 -16 nLanes - Choice to select single or double lane
for frame transfers fsiClock - FSI Clock used for transfers txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers txPingFrameTag - Frame tag used for Ping transfers
txPingTimeRefCntr - Tx Ping timer reference counter rxWdTimeoutRefCntr - Rx Watchdog timeout reference
counter
External Connections
For FSI external P2P connection, external connections are required to be made between two devices. Device
1’s FSI TX and RX pins need to be connected to device 2’s FSI RX and TX pins respectively. See below for
external connections to make and GPIOs used:
External connections required between independent RX and TX devices:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1
GPIO_9 -> FSIRXA_CLK
GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

Watch Variables

dataFrameCntr Number of Data frame transmitted

error Non zero for transmit/receive data mismatch

6.145 FSI star connection topology example. FSI communication

using CPU control
fsi_ex9_star_broadcast is for the central device in the star topology, fsi_ex16_daisy_handshake_node (CPU
Control Only) is used for the N node devices. The fsi_ex16_daisy_handshake_node software example is cur-
rently only available for the F28004x devices.

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In a real scenario two separate devices may power up in arbitrary order and there is a need to establish a clean
communication link which ensures that receiver side is flushed to properly interpret the start of a new valid
frame.
The central device in the star topology initiates and drives the handshake sequence and subsequent broadcast
data transmissions. The node devices receive and respond to the broadcasts.
After above synchronization steps, FSI Rx can be configured as per use case i.e. nWords, lane width, enabling
events, etc and start the infinite transfers. More details on establishing the communication link can be found in
the device TRM.
Preprocessor Directives FSI_RXA_ENABLE, FSI_RXB_ENABLE, FSI_RXC_ENABLE are used to enable dif-
ferent FSI RX instances. Each node device’s FSI TX should be connected to a FSI RX instance of the central
device. The FSI TX of the central device should be connected to each node device’s FSI RX.
User can edit some of configuration parameters as per use case, similar to other examples.
nWords - Number of words per transfer may be from 1 -16 nLanes - Choice to select single or double lane
for frame transfers txUserData - User data to be sent with Data frame txDataFrameTag - Frame tag used for
Data transfers txPingFrameTag - Frame tag used for Ping transfers txPingTimeRefCntr - Tx Ping timer ref-
erence counter rxWdTimeoutRefCntr - Rx Watchdog timeout reference counter rxTimeOutCntr - Rx timeout
reference counter used in handshake sequence
External Connections
For the FSI star connection topology, external connections are required to be made between the included
devices. The FSI TXA pins of the central device (F2838x) needs to be connected to the FSI RX pins of all node
devices (broadcast to node devices). The FSI RXA, RXB, RXC pins of the central device should be connected
to each individual node device’s FSI TX pins. See below for external connections to include and GPIOs used:
External Connections Required:

FSIRX_CLK to FSITX_CLK
FSIRX_RX0 to FSITX_TX0
FSIRX_RX1 to FSITX_TX1

ControlCard FSI Header GPIOs:

GPIO_27 -> FSITXA_CLK

GPIO_26 -> FSITXA_TX0
GPIO_25 -> FSITXA_TX1

GPIO_9 -> FSIRXA_CLK

GPIO_8 -> FSIRXA_RX0
GPIO_10 -> FSIRXA_RX1

GPIO_60 -> FSIRXB_CLK

GPIO_58 -> FSIRXB_RX0
GPIO_59 -> FSIRXB_RX1

GPIO_14 -> FSIRXC_CLK

GPIO_12 -> FSIRXC_RX0
GPIO_13 -> FSIRXC_RX1

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FSI TXA of the central device needs to be connected to FSI RX of all node devices (broadcast to nodes). FSI
RXA, RXB, RXC of the central device should be connected to each individual node device’s FSI TX.
Watch Variables

dataFrameCntr_A Number of Data frame received on FSI RXA

frame_type_error_A Counts number of RXA frame type errors
frame_tag_error_A Counts number of RXA frame tag errors
user_data_error_A Counts number of RXA user data errors
data_error_A Counts number of RXA data packet errors

dataFrameCntr_B Number of Data frame received on FSI RXB

frame_type_error_B Counts number of RXB frame type errors
frame_tag_error_B Counts number of RXB frame tag errors
user_data_error_B Counts number of RXB user data errors
data_error_B Counts number of RXB data packet errors

dataFrameCntr_C Number of Data frame received on FSI RXC

frame_type_error_C Counts number of RXC frame type errors
frame_tag_error_C Counts number of RXC frame tag errors
user_data_error_C Counts number of RXC user data errors
data_error_C Counts number of RXC data packet errors

6.146 Device GPIO Setup

Configures the device GPIO into two different configurations This code is verbose to illustrate how the GPIO
could be setup. In a real application, lines of code can be combined for improved code size and efficiency.
This example only sets-up the GPIO. Nothing is actually done with the pins after setup.
In general:

All pullup resistors are enabled. For ePWMs this may not be desired.
Input qual for communication ports (CAN, SPI, SCI, I2C) is asynchronous
Input qual for Trip pins (TZ) is asynchronous
Input qual for eCAP and eQEP signals is synch to SYSCLKOUT
Input qual for some I/O’s and __interrupts may have a sampling window

6.147 Device GPIO Toggle

Configures the device GPIO through the sysconfig file. The GPIO pin is toggled in the infinite loop. In order to
migrate the project within syscfg to any device, click the swtich button under the device view and select your
corresponding device to migrate, saving the project will auto-migrate your project settings.

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Note:
: This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

6.148 Device GPIO Interrupt

Configures the device GPIOs through the sysconfig file. One GPIO output pin, and one GPIO input pin is
configured. The example then configures the GPIO input pin to be the source of an external interrupt which
toggles the GPIO output pin.

6.149 HRCAP Capture and Calibration Example

This example configures an ECAP to use HRCAP functionality to capture time between edges on input GPIO2.
External Connections
The user must provide a signal to GPIO2. XCLKOUT has been configured to an output GPIO and can be
externally jumped to serve this purpose. See Sysconfig file for XCLKOUT GPIO selected.
Watch Variables

onTime1, onTime2
offTime1, offTime2
period1, period2

6.150 HRPWM Duty Control with SFO

This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
External Connections

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Monitor ePWM1/2/3/4 A/B pins on an oscilloscope.

6.151 HRPWM Slider

This example modifies the MEP control registers to show edge displacement due to HRPWM. Control blocks of
the respective ePWM module channel A and B will have fine edge movement due to HRPWM logic.
Monitor ePWM1 A/B pins on an oscilloscope.

6.152 HRPWM Period Control

This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up-Down count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
External Connections

Monitor ePWM1/2/3/4 A/B pins on an oscilloscope.

6.153 HRPWM Duty Control with UPDOWN Mode

This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

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 C28x Driver Library Example Applications

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
External Connections

Monitor ePWM1/2/3/4 A/B pins on an oscilloscope.

6.154 HRPWM Slider Test

This example modifies the MEP control registers to show edge displacement due to HRPWM. Control blocks of
the respective ePWM module channel A and B will have fine edge movement due to HRPWM logic. Load the
hrpwm_slider.gel file. Select the HRPWM_eval from the GEL menu. A FineDuty slider graphics will show up in
CCS. Load the program and run. Use the Slider to and observe the EPWM edge displacement for each slider
step change. This explains the MEP control on the EPwmxA channels.
Monitor ePWM1 & ePWM2 A/B pins on an oscilloscope.

6.155 HRPWM Duty Up Count

This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
To run this example:

1. Run this example at maximum SYSCLKOUT

2. Activate Real time mode
3. Run the code

External Connections

Monitor ePWM1/2 A/B pins on an oscilloscope.

Watch Variables

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status - Example run status

updateFine - Set to 1 use HRPWM capabilities and observe in fine MEP steps(default) Set to
0 to disable HRPWM capabilities and observe in coarse SYSCLKOUT cycle steps

6.156 HRPWM Period Up-Down Count

This example modifies the MEP control registers to show edge displacement for high-resolution period with
ePWM in Up-Down count mode due to the HRPWM control extension of the respective ePWM module.
This example calls the following TI’s MEP Scale Factor Optimizer (SFO) software library V8 functions:
int SFO();

updates MEP_ScaleFactor dynamically when HRPWM is in use

updates HRMSTEP register (exists only in EPwm1Regs register space) with
MEP_ScaleFactor value
returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255 (Auto-conversion
may not function properly under this condition)
returns 1 when complete for the specified channel
returns 0 if not complete for the specified channel

This example is intended to explain the HRPWM capabilities. The code can be optimized for code efficiency.
Refer to TI’s Digital power application examples and TI Digital Power Supply software libraries for details.
To run this example:

1. Run this example at maximum SYSCLKOUT

2. Activate Real time mode
3. Run the code

External Connections

Monitor ePWM1/2 A/B pins on an oscilloscope.

Watch Variables

updateFine - Set to 1 use HRPWM capabilities and observe in fine MEP steps(default) Set to
0 to disable HRPWM capabilities and observe in coarse SYSCLKOUT cycle steps

6.157 I2C Digital Loopback with FIFO Interrupts

This program uses the internal loopback test mode of the I2C module. Both the TX and RX I2C FIFOs and their
interrupts are used. The pinmux and I2C initialization is done through the sysconfig file.
A stream of data is sent and then compared to the received stream. The sent data looks like this:
0000 0001
0001 0002

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0002 0003
....
00FE 00FF
00FF 0000
etc..
This pattern is repeated forever.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections

None

Watch Variables

sData - Data to send

rData - Received data
rDataPoint - Used to keep track of the last position in the receive stream for error checking

6.158 I2C EEPROM

This program will write 1-14 words to EEPROM and read them back. The data written and the EEPROM
address written to are contained in the message structure, i2cMsgOut. The data read back will be contained in
the message structure i2cMsgIn.
External Connections

Connect external I2C EEPROM at address 0x50

Connect DEVICE_GPIO_PIN_SDAA on to external EEPROM SDA (serial data) pin
Connect DEVICE_GPIO_PIN_SCLA on to external EEPROM SCL (serial clock) pin

Watch Variables

i2cMsgOut - Message containing data to write to EEPROM

i2cMsgIn - Message containing data read from EEPROM

6.159 I2C Digital External Loopback with FIFO Interrupts

This program uses the I2CA and I2CB modules for achieving external loopback. The I2CA TX FIFO and the
I2CB RX FIFO are used along with their interrupts.
A stream of data is sent on I2CA and then compared to the received stream on I2CB. The sent data looks like
this:

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0000 0001
0001 0002
0002 0003
....
00FE 00FF
00FF 0000
etc..
This pattern is repeated forever.
External Connections

Connect SCLA(DEVICE_GPIO_PIN_SCLA) to SCLB (DEVICE_GPIO_PIN_SCLB)

and SDAA(DEVICE_GPIO_PIN_SDAA) to SDAB (DEVICE_GPIO_PIN_SDAB)
Connect DEVICE_GPIO_PIN_LED1 to an LED used to depict data transfers.

Watch Variables

sData - Data to send

rData - Received data
rDataPoint - Used to keep track of the last position in the receive stream for error checking

6.160 I2C EEPROM

This program will shows how to perform different EEPROM write and read commands using I2C polling method
EEPROM used for this example is AT24C256
External Connections

Connect external I2C EEPROM at address 0x50 ——————————– Signal | I2CA

| EEPROM ——————————– SCL | DEVICE_GPIO_PIN_SCLA | SCL SDA | DE-
VICE_GPIO_PIN_SDAA | SDA Make sure to connect GND pins if EEPROM and C2000 device
are in different board. ——————————–

6.161 I2C controller target communication using FIFO interrupts

This program shows how to use I2CA and I2CB modules in both controller and target configuration This example
uses I2C FIFO interrupts and doesn’t using polling
Example1: I2CA as controller Transmitter and I2CB working target Receiver Example2: I2CA as controller
Receiver and I2CB working target Transmitter Example3: I2CB as controller Transmitter and I2CA working
target Receiver Example4: I2CB as controller Receiver and I2CA working target Transmitter
External Connections on launchpad should be made as shown below
——————————– Signal | I2CA | I2CB ——————————– SCL | DEVICE_GPIO_PIN_SCLA | DE-
VICE_GPIO_PIN_SCLB SDA | DEVICE_GPIO_PIN_SDAA | DEVICE_GPIO_PIN_SDAB —————————
—–

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Watch Variables in memory window

I2CA_TXdata
I2CA_RXdata
I2CB_TXdata
I2CB_RXdata stream for error checking

###########################################################################

6.162 I2C EEPROM

This program will shows how to perform different EEPROM write and read commands using I2C interrupts
EEPROM used for this example is AT24C256
External Connections

Connect external I2C EEPROM at address 0x50 ——————————– Signal | I2CA

| EEPROM ——————————– SCL | DEVICE_GPIO_PIN_SCLA | SCL SDA | DE-
VICE_GPIO_PIN_SDAA | SDA Make sure to connect GND pins if EEPROM and C2000 device
are in different board. ——————————– Example 1: EEPROM Byte Write Example 2:
EEPROM Byte Read Example 3: EEPROM word (16-bit) write Example 4: EEPROM word
(16-bit) read Example 5: EEPROM Page write Example 6: EEPROM word Paged read

Watch Variables

TX_MsgBuffer - Message buffer which stores the data to be transmitted

RX_MsgBuffer - Message buffer which stores the data to be received

###########################################################################

6.163 External Interrupts (ExternalInterrupt)

This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO10 triggers XINT1 and GPIO11 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510∗SYSCLKOUT each.
GPIO16 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections

Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1

Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2

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Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the ISRs and low within each ISR.
Watch Variables

xint1Count for the number of times through XINT1 interrupt

xint2Count for the number of times through XINT2 interrupt
loopCount for the number of times through the idle loop

6.164 Multiple interrupt handling of I2C, SCI & SPI Digital Loop-
back
This program is used to demonstrate how to handle multiple interrupts when using multiple communication
peripherals like I2C, SCI & SPI Digital Loopback all in a single example. The data transfers would be done with
FIFO Interrupts.
It uses the internal loopback test mode of these modules. Both the TX and RX FIFOs and their interrupts are
used. Other than boot mode pin configuration, no other hardware configuration is required.
A stream of data is sent and then compared to the received stream. The sent data looks like this for I2C and
SCI:
0000 0001
0001 0002
0002 0003
....
00FE 00FF
00FF 0000
etc..
The sent data looks like this for SPI:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.
External Connections

None

Watch Variables

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sDatai2cA - Data to send through I2C

rDatai2cA - Received I2C data
rDataPoint - Used to keep track of the last position in the receive I2C stream for error checking

sDataspiA - Data to send through SPI

rDataspiA - Received SPI data
rDataPointspiA - Used to keep track of the last position in the receive SPI stream for error
checking

sDatasciA - SCI Data being sent

rDatasciA - SCI Data received
rDataPointA - Keep track of where we are in the SCI data stream. This is used to check the
incoming data

6.165 CPU Timer Interrupt Software Prioritization

This examples demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software
prioritization of interrupts is achieved by enabling interrupt nesting.
In this device, hardware priorities for CPU Timer 0, 1 and 2 are set as timer 0 being highest priority and timer
2 being lowest priority. This example configures CPU Timer0, 1, and 2 priority in software with timer 2 priority
being highest and timer 0 being lowest in software and prints a trace for the order of execution.
For most applications, the hardware prioritizing of the interrupts is sufficient. For applications that need cus-
tom prioritizing, this example illustrates how this can be done through software.User specific priorities can be
configured in sw_prioritized_isr_level.h header file.
To enable interrupt nesting, following sequence needs to followed in ISRs. Step 1: Set the global priority:
Modify the IER register to allow CPU interrupts with a higher user priority to be serviced. Note: at this time IER
has already been saved on the stack. Step 2: Set the group priority: (optional) Modify the appropriate PIEIERx
register to allow group interrupts with a higher user set priority to be serviced. Do NOT clear PIEIER register
bits from another group other than that being serviced by this ISR. Doing so can cause erroneous interrupts to
occur. Step 3: Enable interrupts: There are three steps to do this: a. Clear the PIEACK bits b. Wait at least
one cycle c. Clear the INTM bit. Step 4: Run the main part of the ISR Step 5: Set INTM to disable interrupts.
Step 6: Restore PIEIERx (optional depending on step 2) Step 7: Return from ISR
Refer to below link on more details on Interrupt nesting in C28x devices: <C2000Ware>.html
External Connections

None

Watch Variables

traceISR - shows the order in which ISRs are executed.

6.166 EPWM Real-Time Interrupt

This example configures the ePWM1 Timer and increments a counter each time the ISR is executed. ePWM
interrupt can be configured as time critical to demonstrate real-time mode functionality and real-time interrupt

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capability.
The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is toggled in the EPWM Timer Inter-
rupt. FREE_SOFT bits and DBGIER.INT3 bit must be set to enable ePWM1 interrupt to be time critical and
operational in real time mode after halt command
How to run the example?

Add the watch variables as mentioned below and enable Continuous Refresh.
Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
Initially, the DBGIER register is set to 0 and the EPWM emulation mode is set to
EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
When the application is running, you will find both LEDs toggling and the watch variables
EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
When the application is halted, both LEDs stop toggling and the watch variables remain con-
stant. EPWM counter is stopped on debugger halt.
To enable EPWM counter run during debugger halt, set emulation mode as
EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR is
running, but EPwm1TimerIntCount remains constant. This means, the EPWM counter is run-
ning, but the ISRs are not getting serviced.
To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is part of PIE Group
3). You will find that the EPwm1TimerIntCount is incrementing and the LED starts toggling.
The EPWM ISR is getting serviced even during a debugger halt.

For more details, watch this video : [C2000 Real-Time Features](https://training.ti.com/c2000-real-time-

features)
External Connections

None

Watch Variables

EPwm1TimerIntCount - EPWM1 ISR counter

EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
DBGIER.INT3 - Set to 1 to enable real time interrupt

6.167 LED Blinky Example with DCSM

This example demonstrates how to blink a LED and program the DCSM OTP. Please refer
f2838x_dcsm_z1otp.asm and f2838x_dcsm_z1otp.asm files for details on DCSM OTP programming.
External Connections

None.

Watch Variables

None.

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6.168 Low Power Modes: Device Idle Mode and Wakeup using
GPIO
This example puts the device into IDLE mode and then wakes up the device from IDLE using XINT1 which
triggers on a falling edge of GPIO0.
The GPIO0 pin must be pulled from high to low by an external agent for wakeup. GPIO0 is configured as an
XINT1 pin to trigger an XINT1 interrupt upon detection of a falling edge.
Initially, pull GPIO0 high externally. To wake device from IDLE mode by triggering an XINT1 interrupt, pull
GPIO0 low (falling edge). The wakeup process begins as soon as GPIO0 is held low for the time indicated in
the device datasheet.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the external interrupt ISR.
External Connections

GPIO0 needs to be pulled low to wake up the device.

On device wakeup, the GPIO1 will be low and LED1 will start blinking

6.169 Low Power Modes: Device Idle Mode and Wakeup using
Watchdog
This example puts the device into IDLE mode and then wakes up the device from IDLE using watchdog timer.
The device wakes up from the IDLE mode when the watchdog timer overflows, triggering an interrupt. A pre
scalar is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the wakeup ISR.
External Connections

On device wakeup, the GPIO1 will be low and LED1 will start blinking

6.170 Low Power Modes: Device Standby Mode and Wakeup using
GPIO
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode and then wakes up the device from STANDBY using an LPM
wakeup pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse. Initially, pull GPIO0 high externally. To wake device from STANDBY mode, pull GPIO0 low for at least
(2+QUALSTDBY), OSCLKS, then pull it high again.
The example then wakes up the device from STANDBY using GPIO0. GPIO0 wakes the device from STANDBY

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mode when a low pulse (signal goes high->low->high)is detected on the pin. This pin must be pulsed by an
external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections

GPIO0 needs to be pulled low to wake up the device.

On device wakeup, the GPIO1 will be low and LED1 will start blinking

6.171 Low Power Modes: Device Standby Mode and Wakeup using
Watchdog
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode then wakes up the device from STANDBY using watchdog
timer.
The device wakes up from the STANDBY mode when the watchdog timer overflows triggering an interrupt. In
the ISR, the GPIO1 is pulled low. the GPIO1 is toggled to indicate the device is out of STANDBY mode. A pre
scalar is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections

On device wakeup, the GPIO1 will be low and LED1 will start blinking

6.172 MCAN Loopback with Interrupts Example Using SYSCON-

FIG Tool
This example illustrates the MCAN Loopback functionality. The internal loopback mode is entered. The mes-
sage transmitted would be received by the node. The last address of memory is used for the Rx buffer. Periph-
eral configuration is done through SYSCONFIG
External Connections

None.

Watch Variables

error - Checks if there is an error that occurred when the data was sent using internal loopback.

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6.173 McBSP loopback example

This example demonstrates the McBSP operation using internal loopback. This example does not use inter-
rupts. Instead, a polling method is used to check the receive data. The incoming data is checked for accuracy.
Three different serial word sizes can be tested. Before compiling this project, select the serial word size of 8, 16
or 32 by using the #define statements at the beginning of the code.
This program will execute until terminated by the user.
8-bit word example:
The sent data looks like this:
00 01 02 03 04 05 06 07 .... FE FF
16-bit word example:
The sent data looks like this:
0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF
32-bit word example:
The sent data looks like this:
FFFF0000 FFFE0001 FFFD0002 .... 0000FFFF
External Connections

None

Watch Variables:

txData1 - Sent data word: 8 or 16-bit or low half of 32-bit

txData2 - Sent data word: upper half of 32-bit
rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
rxData2 - Received data word: upper half of 32-bit
errCountGlobal - Error counter

Note:
txData2 and rxData2 are not used for 8-bit or 16-bit word size.

6.174 McBSP loopback with DMA example.

This example demonstrates the McBSP operation using internal loopback and utilizes the DMA to transfer data
from one buffer to the McBSP and then from McBSP to another buffer.
Initially, txData[] is filled with values from 0x0000- 0x007F. The DMA moves the values in txData[] one by one
to the DXRx registers of the McBSP. These values are transmitted and subsequently received by the McBSP.
Then, the the DMA moves each data value to rxData[] as it is received by the McBSP.
The sent data buffer looks like this:
0000 0001 0002 0003 0004 0005 .... 007F

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Three different serial word sizes can be tested. Before compiling this project, select the serial word size of 8, 16
or 32 by using the #define statements at the beginning of the code.
This example uses DMA channel 1 and 2 interrupts. The incoming data is checked for accuracy.
External Connections

None

Watch Variables:

txData - Sent data buffer

rxData - Received data buffer
errCountGlobal - Error counter

6.175 McBSP loopback with interrupts example

This example demonstrates the McBSP operation using internal loopback. This example uses interrupts. Both
Rx and Tx interrupts are enabled.
External Connections

None

Watch Variables:

txData - Sent data word

rxData - Received data word
errCountGlobal - Error counter

6.176 McBSP loopback with interrupts example

This example demonstrates the McBSP operation using internal loopback. This example uses interrupts. Both
Rx and Tx interrupts are enabled.
External Connections

None

Watch Variables:

txData - Sent data word

rxData - Received data word
errCountGlobal - Error counter

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6.177 McBSP loopback example using SPI mode

This example demonstrates the McBSP operation in SPI mode using internal loopback. This example demon-
strates SPI master mode transfer of 32-bit word size with digital loopback enabled.
McBSP Signals - SPI equivalent

MCLKX - SPICLK
MFSX - SPISTE
MDX - SPISIMO
MDR - SPISOMI (not used for this example)

External Connections

None

Watch Variables:

txData1 - Sent data word: 8 or 16-bit or low half of 32-bit

txData2 - Sent data word: upper half of 32-bit
rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
rxData2 - Received data word: upper half of 32-bit
errCountGlobal - Error counter

6.178 McBSP external loopback example

This example demonstrates the McBSP operation using external loopback. This example does not use inter-
rupts. Instead, a polling method is used to check the receive data. The incoming data is checked for accuracy.
Three different serial word sizes can be tested. Before compiling this project, select the serial word size of 8, 16
or 32 by using the #define statements at the beginning of the code.
This program will execute until terminated by the user.
8-bit word example:
The sent data looks like this:
00 01 02 03 04 05 06 07 .... FE FF
16-bit word example:
The sent data looks like this:
0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF
32-bit word example:
The sent data looks like this:
FFFF0000 FFFE0001 FFFD0002 .... 0000FFFF
External Connections
McBSPA Signals - McBSPB signals

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MCLKXA - MCLKRB
MFSXA - MFSRB
MDXA - MDRB
MCLKRA - MCLKXB
MFSRA - MFSXB
MDRA - MDXB

Watch Variables:

txData1A - Sent data word by McBSPA Transmitter:8 or 16-bit or low half of 32-bit
txData2A - Sent data word by McBSPA Transmitter:upper half of 32-bit
rxData1A - Received data word by MCBSPA Receiver:8 or 16-bit or lower half of 32-bit
rxData2A - Received data word by McBSPA Receiver:upper half of 32-bit
txData1B - Sent data word by McBSPB Transmitter:8 or 16-bit or low half of 32-bit
txData2B - Sent data word by McBSPB Transmitter:upper half of 32-bit
rxData1B - Received data word by McBSPB Receiver:8 or 16-bit or lower half of 32-bit
rxData2B - Received data word by McBSPB Receiver:upper half of 32-bit
errCountGlobal - Error counter

Note:
txData2A, rxData2A, txData2B and rxData2B are not used for 8-bit or 16-bit word size.

6.179 McBSP external loopback example using SPI mode

This example demonstrates the McBSP operation in SPI mode using external loopback. This example config-
ures McBSP instances available on the device as SPI master and slave and demonstrates transfer of 32-bit
word size data with external loopback.
External Connections
SPI Master(McBSPA) SPI Slave(McBSPB)

MCLKXA(SPICLK) (GPIO22) - MCLKXB(SPICLK) (GPIO26)

MFSXA (SPISTE) (GPIO23) - MFSXB (SPISTE) (GPIO27)
MDXA (SPISIMO)(GPIO20) - MDRB (SPISIMO)(GPIO25)
MDRA (SPISOMI)(GPIO21) - MDXB (SPISOMI)(GPIO24)

Watch Variables:

txData1 - Sent data word: 8 or 16-bit or low half of 32-bit

txData2 - Sent data word: upper half of 32-bit
rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
rxData2 - Received data word: upper half of 32-bit
errCountGlobal - Error counter

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6.180 McBSP TDM-8 Test

For the detailed description of this example, please refer to: How to Implement Custom Serial Interfaces Using
the Configurable Logic Block (CLB) Application Note (SPRAD62).
In this example a MCBSP is used to generate and receive a TDM-8 test stream. This example uses interrupts.
Both RX and TX interrupts are enabled. The McBSP TDM stream is set to eight 32-bit channels per frame.

Note:
This example is specifically created for use with SPRAD62.

To use the McBSP inputs and outputs, the following connections are needed:
External Connections
McBSP Output Pins GPIO pin Device Under Test (DUT) MCLKX GPIO22 BCLK_IN MFSX GPIO23 FSYNC_IN
MDX GPIO20 DATA1_IN
McBSP Input Pins GPIO pin Device Under Test (DUT) MCLKR GPIO58 BCLK_OUT FSR GPIO59 FSYNC_OUT
MDR GPIO21 DATA1_OUT
Note:
The McBSP TX and RX pins can be externally looped back to create self contained test.

Watch Variables:

txData - Sent data word by McBSP Transmitter

rxData - Received data word by McBSP Receiver
testWordDetected - Indicates when test has started
errCountGlobal - Number of errors detected

6.181 Correctable & Uncorrectable Memory Error Handling

This example demonstrates error handling in case of various erroneous memory read/write operations. Error
handling in case of CPU read/write violations, correctable & uncorrectable memory errors has been demon-
strated. Correctable memory errors & violations can generate SYS_INT interrupt to CPU while uncorrectable
errors lead to NMI generation.
External Connections

None

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errCountGlobal - Error counter

6.182 Empty SysCfg & Driverlib Example

This example is an empty project setup for SysConfig and Driverlib development.

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6.183 Tune Baud Rate via UART Example

This example demonstrates the process of tuning the UART/SCI baud rate of a C2000 device based on the
UART input from another device. As UART does not have a clock signal, reliable communication requires baud
rates to be reasonably matched. This example addresses cases where a clock mismatch between devices
is greater than is acceptable for communications, requiring baud compensation between boards. As reliable
communication only requires matching the EFFECTIVE baud rate, it does not matter which of the two boards
executes the tuning (the board with the less-accurate clock source does not need to be the one to tune; as long
as one of the two devices tunes to the other, then proper communication can be established).
To tune the baud rate of this device, SCI data (of the desired baud rate) must be sent to this device. The in-
put SCI baud rate must be within the +/- MARGINPERCENT of the TARGETBAUD chosen below. These two
variables are defined below, and should be chosen based on the application requirements. Higher MARGIN-
PERCENT will allow more data to be considered "correct" in noisy conditions, and may decrease accuracy. The
TARGETBAUD is what was expected to be the baud rate, but due to clock differences, needs to be tuned for
better communication robustness with the other device.
NOTE: Lower baud rates have more granularity in register options, and therefore tuning is more affective at
these speeds.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections for Control Card

SCIA_RX/eCAP1 is on GPIO9, connect to incoming SCI communications

SCIA_TX is on GPIO8, for observation externally

Watch Variables

avgBaud - Baud rate that was detected and set after tuning

6.184 SCI FIFO Digital Loop Back

This program uses the internal loop back test mode of the peripheral. Other then boot mode pin configuration,
no other hardware configuration is required. The pinmux and SCI modules are configured through the sysconfig
file.
This test uses the loopback test mode of the SCI module to send characters starting with 0x00 through 0xFF.
The test will send a character and then check the receive buffer for a correct match.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

Watch Variables

loopCount - Number of characters sent

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errorCount - Number of errors detected

sendChar - Character sent
receivedChar - Character received

6.185 SCI Digital Loop Back with Interrupts

This test uses the internal loop back test mode of the peripheral. Other then boot mode pin configuration, no
other hardware configuration is required. Both interrupts and the SCI FIFOs are used.
A stream of data is sent and then compared to the received stream. The SCI-A sent data looks like this:
00 01
01 02
02 03
....
FE FF
FF 00
etc..
The pattern is repeated forever.
Watch Variables

sDataA - Data being sent

rDataA - Data received
rDataPointA - Keep track of where we are in the data stream. This is used to check the
incoming data

6.186 SCI Echoback

This test receives and echo-backs data through the SCI-A port.
A terminal such as ’putty’ can be used to view the data from the SCI and to send information to the SCI.
Characters received by the SCI port are sent back to the host.
Running the Application Open a COM port with the following settings using a terminal:

Find correct COM port

Bits per second = 9600
Data Bits = 8
Parity = None
Stop Bits = 1
Hardware Control = None

The program will print out a greeting and then ask you to enter a character which it will echo back to the terminal.
Watch Variables

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loopCounter - the number of characters sent

External Connections
Connect the USB cable from Control card J1:A to PC

6.187 stdout redirect example

This test transmits data through the SCI-A port to a terminal
A terminal such as ’putty’ can be used to view the data from the SCI. Characters received by the SCI port are
sent back to the host.
Running the Application Open a COM port with the following settings using a terminal:

Find correct COM port

Bits per second = 9600
Data Bits = 8
Parity = None
Stop Bits = 1
Hardware Control = None

The program will print out three sentences: one to the SCIA, one to CCS, and a final one to SCIA.
External Connections
Connect the SCI-A port to a PC via a transceiver and cable.

DEVICE_GPIO_PIN_SCIRXDA is SCI_A-RXD (Connect to Pin3, PC-TX, of serial DB9 cable)

DEVICE_GPIO_PIN_SCITXDA is SCI_A-TXD (Connect to Pin2, PC-RX, of serial DB9 cable)

6.188 SDFM Filter Sync CPU

In this example, SDFM filter data is read by CPU in SDFM ISR routine. The SDFM configuration is shown
below:

SDFM used in this example - SDFM1

Input control mode selected - MODE0
Comparator settings
• Sinc3 filter selected
• OSR = 32
• HLT = 0x7FFF (Higher threshold setting)
• LLT = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 128

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• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 7 bits for
Sinc3 filter with OSR = 128
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available.

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

filter1Result - Output of filter 1

filter2Result - Output of filter 2
filter3Result - Output of filter 3
filter4Result - Output of filter 4

6.189 SDFM Filter Sync CLA

In this example, SDFM filter data is read by CLA in Cla1Task1. The SDFM configuration is shown below:

SDFM1 used in this example.For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• hlt = 0x7FFF (Higher threshold setting)
• llt = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format

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• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

filter1Result - Output of filter 1

filter2Result - Output of filter 2
filter3Result - Output of filter 3
filter4Result - Output of filter 4

6.190 SDFM Filter Sync DMA

In this example, SDFM filter data is read by DMA. The SDFM configuration is shown below:

SDFM1 used in this example. For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• hlt = 0x7FFF (Higher threshold setting)
• llt = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter

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• All the 4 higher threshold comparator interrupts disabled

• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

filter1Result - Output of filter 1

filter2Result - Output of filter 2
filter3Result - Output of filter 3
filter4Result - Output of filter 4

6.191 SDFM PWM Sync

In this example, SDFM filter data is read by CPU in SDFM ISR routine. The SDFM configuration is shown
below:

SDFM1 is used in this example. For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• hlt = 0x7FFF (Higher threshold setting)
• llt = 0x0000(Lower threshold setting)

Data filter settings

All the 4 filter modules enabled

Sinc3 filter selected
OSR = 256
All the 4 filters are synchronized by using PWM (Master Filter enable bit)
Filter output represented in 16 bit format
In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits for
Sinc3 filter with OSR = 256

Interrupt module settings for SDFM filter

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All the 4 higher threshold comparator interrupts disabled

All the 4 lower threshold comparator interrupts disabled
All the 4 modulator failure interrupts disabled
All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

filter1Result - Output of filter 1

filter2Result - Output of filter 2
filter3Result - Output of filter 3
filter4Result - Output of filter 4

6.192 SDFM Type 1 Filter FIFO

This example configures SDFM1 filter in type 1 to demonstrate data read through CPU in FIFO & non-FIFO
mode. Data filter is configured in mode 0 to select SINC3 filter with OSR of 256. Filter output is configured for
16-bit format and data shift of 10 is used.
This example demonstrates the FIFO usage if enabled. FIFO length is set at 16 and data ready interrupt is
configured to be triggered when FIFO is full. In this example, SDFM filter data is read by CPU in SDFM Data
Ready ISR routine.
External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to (GPIO16,

GPIO17)
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to (GPIO48,
GPIO49)
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to (GPIO122,
GPIO123)

Watch Variables

filter1Result - Output of filter 1

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6.193 SDFM Filter Sync CLA

In this example, SDFM FIFO will not be filled until a SDSYNC event. On a SDSYNC event, SDFM data filter
output will start filling FIFO and stop filling after programmable number ’N’ of FIFO is filled.
SDy-C1 (Filter1 channel clock) is internally configured to connected SDy-C2 / SDy-C3 / SDy-C4 SDFM config-
uration is shown below:

SDFM1 used in this example.For using SDFM2, few modifications would be needed in the
example.
MODE0 Input control mode selected
Comparator settings
• Sinc3 filter selected
• OSR = 32
• hlt = 0x7FFF (Higher threshold setting)
• llt = 0x0000(Lower threshold setting)
Data filter settings
• All the 4 filter modules enabled
• Sinc3 filter selected
• OSR = 256
• All the 4 filters are synchronized by using MFE (Master Filter enable bit)
• Filter output represented in 16 bit format
• In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits
for Sinc3 filter with OSR = 256
Interrupt module settings for SDFM filter
• All the 4 higher threshold comparator interrupts disabled
• All the 4 lower threshold comparator interrupts disabled
• All the 4 modulator failure interrupts disabled
• All the 4 filter will generate interrupt when a new filter data is available

External Connections

SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-

D4,SDx-C4) on GPIO16-GPIO31
SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO48-GPIO63
SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to (SDx-D1, SDx-C1 to SDx-
D4,SDx-C4) on GPIO122-GPIO137

Watch Variables

filter1Result - Output of filter 1

filter2Result - Output of filter 2
filter3Result - Output of filter 3
filter4Result - Output of filter 4

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6.194 SD FATFS Library Example

This example demonstrates how to use the FATFS library.
External Connections

Connect the SPI signals identifed in the SysConfig to an SD CARD.

Watch Variables

None.

6.195 SD FATFS Library Example with exFAT Support

This example demonstrates how to use the FATFS library with exFAT support.
External Connections

Connect the SPI signals identifed in the SysConfig to an SD CARD.

Watch Variables

None.

6.196 SPI Digital Loopback

This program uses the internal loopback test mode of the SPI module. This is a very basic loopback that does
not use the FIFOs or interrupts. A stream of data is sent and then compared to the received stream. The pinmux
and SPI modules are configure through the sysconfig file.
The sent data looks like this:
0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF 0000
This pattern is repeated forever.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections

None

Watch Variables

sData - Data to send

rData - Received data

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6.197 SPI Digital Loopback with FIFO Interrupts

This program uses the internal loopback test mode of the SPI module. Both the SPI FIFOs and their interrupts
are used.
A stream of data is sent and then compared to the received stream. The sent data looks like this:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections

None

Watch Variables

sData - Data to send

rData - Received data
rDataPoint - Used to keep track of the last position in the receive stream for error checking

6.198 SPI Digital External Loopback without FIFO Interrupts

This program uses the external loopback between two SPI modules. Both the SPI FIFOs and interrupts are
not used in this example. SPIA is configured as a peripheral and SPI B is configured as controller. This
example demonstrates full duplex communication where both controller and peripheral transmits and receives
data simultaneously.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections
Refer to SysConfig for external connections (GPIO pin numbers) specific to each device
Watch Variables

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TxData_SPIA - Data send from SPIA (peripheral)

TxData_SPIB - Data send from SPIB (controller)
RxData_SPIA - Data received by SPIA (peripheral)
RxData_SPIB - Data received by SPIB (controller)

6.199 SPI Digital External Loopback with FIFO Interrupts

This program uses the external loopback between two SPI modules. Both the SPI FIFOs and their interrupts
are used. SPIA is configured as a peripheral and receives data from SPI B which is configured as a controller.
A stream of data is sent and then compared to the received stream. The sent data looks like this:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections
Refer to SysConfig for external connections (GPIO pin numbers) specific to each device
Watch Variables

sData - Data to send

rData - Received data
rDataPoint - Used to keep track of the last position in the receive stream for error checking

6.200 SPI Digital Loopback with DMA

This program uses the internal loopback test mode of the SPI module. Both DMA interrupts and the SPI FIFOs
are used. When the SPI transmit FIFO has enough space (as indicated by its FIFO level interrupt signal), the
DMA will transfer data from global variable sData into the FIFO. This will be transmitted to the receive FIFO via
the internal loopback.
When enough data has been placed in the receive FIFO (as indicated by its FIFO level interrupt signal), the
DMA will transfer the data from the FIFO into global variable rData.

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When all data has been placed into rData, a check of the validity of the data will be performed in one of the
DMA channels’ ISRs.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections

None

Watch Variables

sData - Data to send

rData - Received data

6.201 SPI EEPROM

This program will write 8 bytes to EEPROM and read them back. The device communicates with the EEPROM
via SPI and specific opcodes. This example is written to work with the SPI Serial EEPROM AT25128/256.
Note: SPI character length is configured to 8 bits in SysConfig, and not changed throughout the execution of
the program. Runtime updation of character length when CS pin is not controlled by the SPI module can lead
to unpredictable behaviour
External Connections
External Connections

Connect external SPI EEPROM

Connect GPIO16 (PICO) to external EEPROM SI pin
Connect GPIO17 (POCI) to external EEPROM SO pin
Connect GPIO18 (CLK) to external EEPROM SCK pin
Connect GPIO11 (CS) to external EEPROM CS pin
Connect the external EEPROM VCC and GND pins

Watch Variables

writeBuffer - Data that is written to external EEPROM

readBuffer - Data that is read back from EEPROM
error - Error count

6.202 SPI DMA EEPROM

This program will write 8 bytes to EEPROM and read them back. The device communicates with the EEP-
ROM via SPI using DMA and specific opcodes. This example is written to work with the SPI Serial EEPROM

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AT25128/256. Note: Runtime updation of character length when CS pin is not controlled by the SPI module can
lead to unpredictable behaviour
External Connections
External Connections

Connect external SPI EEPROM

Connect GPIO16 (PICO) to external EEPROM SI pin
Connect GPIO17 (POCI) to external EEPROM SO pin
Connect GPIO18 (CLK) to external EEPROM SCK pin
Connect GPIO11 (CS) to external EEPROM CS pin
Connect the external EEPROM VCC and GND pins

Watch Variables

writeBuffer - Data that is written to external EEPROM

SPI_DMA_Handle.RXdata - Data that is read back from EEPROM when number of received
bytes is less than 4
SPI_DMA_Handle.pSPIRXDMA->pbuffer - Start address of received data from EEPROM
error - Error count

6.203 Missing clock detection (MCD)

This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (200Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 200Mhz but using the INTOSC1 as clock source.
External Connections

None.

Watch Variables

fail - Indicates that a missing clock was either not detected or was not handled correctly.
mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and
called an the ISR to handle it.
mcd_detect - Indicates that a missing clock was detected.
result - Status of a successful handling of missing clock detection

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6.204 XCLKOUT (External Clock Output) Configuration

This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8. Ex-
pected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO73 using an oscilloscope.

6.205 CPU Timers

This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt. In order to migrate the project within syscfg to any device, click the swtich button under the device
view and select your corresponding device to migrate, saving the project will auto-migrate your project settings.
External Connections

None

Watch Variables

cpuTimer0IntCount
cpuTimer1IntCount
cpuTimer2IntCount

6.206 CPU Timers

This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.

Note:
This example project has support for migration across our C2000 device families. If you are
wanting to build this project from launchpad or controlCARD, please specify in the .syscfg file
the board you’re using. At any time you can select another device to migrate this example.

External Connections

None

Watch Variables

cpuTimer0IntCount
cpuTimer1IntCount
cpuTimer2IntCount

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6.207 USB HUB Host example

This example application demonstrates how to support a USB keyboard and USB Mouse with a USB Hub. The
display will show the connected devices on the USB hub.
To run the example you should connect a USB Hub to the microUSB port on the top of the controlCARD and
open up a serial terminal with the above settings to view the characters typed on the keyboard. Allow the
example to run with the hub connected and then connect the USB Host Mouse or Keyboard.
When a USB Mouse is connected on the Hub the position of the mouse pointer and the state of the mouse
buttons are output to the display. Similarly when a USB Keyboard is connected, any key press on the keyboard
will cause them to be sent out the SCI at 115200 baud with no parity, 8 bits and 1 stop bit.
This example is for depicting the usage of Hub.
There are some limitations in this example : 1. The Example fails to recognize the USB Hub and the device if
the Mouse/Keyboard is already connected to the USB Hub and the Hub is connected to the Micro USB of the
Control Card. 2. The same port should not be used to connect a Keyboard and mouse.

6.208 USB CDC serial example

This example application turns the evaluation kit into a virtual serial port when connected to the USB host
system. The application supports the USB Communication Device Class, Abstract Control Model to redirect
SCIA traffic to and from the USB host system.
Connect USB cables from your PC to both the mini and microUSB connectors on the controlCARD.Figure out
what COM ports your controlCARD is enumerating (typically done using Device Manager in Windows) and open
a serial terminal to each of with the settings 115200 Baud 8-N-1. Characters typed in one terminal should be
echoed in the other and vice versa.
A driver information (INF) file for use with Windows XP, Windows 7 and Windows 10 can be found in the
windows_drivers directory.

6.209 USB HID Mouse Device

This example application turns the evaluation board into a USB mouse supporting the Human Interface Device
class. After loading and running the example simply connect the PC to the controlCARDs microUSB port using
a USB cable, and the mouse pointer will move in a square pattern for the duration of the time it is plugged in.
SCIA, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages from
this application.

6.210 USB Device Keyboard

This example application turns the evaluation board into a USB keyboard supporting the Human Interface
Device class. The global variable ui32Button should be modified to wake up the USB. Care should be taken to
ensure that the active window can safely receive the text; enter is not pressed at any point so no actions are
attempted by the host if a terminal window is used.

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The device implemented by this application also supports USB remote wake up allowing it to request the host
to reactivate a suspended bus. If the bus is suspended (as indicated on the application display), updating
ui32Button will request a remote wakeup assuming the host has not specifically disabled such requests.
To run the example compile the project, load to the target, and run the example. After the example is run-
ning, connect a USB cable from the PC to the microUSB port on the controlCARD.Modify ui32Button value in
the expressions window and then focus should be on the window so that we can receive keyboard input (i.e.
NotePad).

6.211 USB Generic Bulk Device

This example provides a generic USB device offering simple bulk data transfer to and from the host. The
device uses a vendor-specific class ID and supports a single bulk IN endpoint and a single bulk OUT endpoint.
Data received from the host is assumed to be ASCII text and it is echoed back with the case of all alphabetic
characters swapped.
SCIA, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages from
this application.
A Windows INF file for the device is provided under the windows drivers directory. This INF contains information
required to install the WinUSB subsystem on WindowsXP, Windows 7 and Windows 10. WinUSB is a Windows
subsystem allowing user mode applications to access the USB device without the need for a vendor-specific
kernel mode driver.
A sample Windows command-line application, usb_bulk_example, illustrating how to connect to and com-
municate with the bulk device is also provided. Project files are included to allow the examples
to be built using Microsoft VisualStudio. Source code for this application can be found in directory
∼/C2000Ware/utilities/tools/{Device}/usb_bulk_example/Release

6.212 USB HID Mouse Host

This application demonstrates the handling of a USB mouse attached to the evaluation kit. Once attached, the
position of the mouse pointer and the state of the mouse buttons are output to the display.
SCIA, which is connected to the FTDI virtual serial port on the controlCARD board, is configured for 115200
bits per second, and 8-N-1 mode. When a HID compliant mouse is connected to the microUSB port on the top
of the controlCARD, position and button information will be displayed to the console.

6.213 USB HID Keyboard Host

This example application demonstrates how to support a USB keyboard attached to the evaluation kit board.
The display will show if a keyboard is currently connected and the current state of the Caps Lock key on the
keyboard that is connected on the bottom status area of the screen. Pressing any keys on the keyboard will
cause them to be sent out the SCI at 115200 baud with no parity, 8 bits and 1 stop bit. Any keyboard that
supports the USB HID BIOS protocol should work with this demo application.
To run the example you should connect a HID compliant keyboard to the microUSB port on the top of the
controlCARD and open up a serial terminal with the above settings to view the characters typed on the keyboard.

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6.214 USB Mass Storage Class Host

This example application demonstrates reading a file system from a USB mass storage class device. It makes
use of FatFs, a FAT file system driver. It provides a simple command console via the SCI for issuing commands
to view and navigate the file system on the mass storage device.
The first SCI, which is connected to the FTDI virtual serial port on the controlCARD board, is configured for
115200 bits per second, and 8-N-1 mode. When the program is started a message will be printed to the
terminal. Type “help” for command help.
After loading and running the example, open a serial terminal with the above settings to open the command
prompt. Then connect a USB MSC device to the microUSB port on the top of the controlCARD.
For additional details about FatFs, see the following site: [FatFs - Generic FAT Filesystem Module](http://elm-
chan.org/fsw/ff/00index_e.html)

6.215 USB Dual Detect

This program uses a GPIO to do ID detection. If a host is connected to the device’s USB port, the stack will
switch to device mode and enumerate as mouse. If a mouse device is connected to the device’s USB port,
the stack will switch to host mode and display the mouses movement and button press information in a serial
terminal.

6.216 USB Throughput Bulk Device Example

(usb_ex9_throughput_dev_bulk)
This example provides a throughput numbers of bulk data transfer to and from the host. The device uses a
vendor-specific class ID and supports a single bulk IN Endpoint and a single bulk OUT Endpoint.
SCIA, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages from
this application.
A Windows INF file for the device is provided under the windows drivers directory. This INF contains information
required to install the WinUSB subsystem on WindowsXP, Windows 7 and Windows 10. This is present in
utilities/windows_drivers.
A sample Windows command-line application, usb_throughput_bulk_example, illustrating how to connect to
and communicate with the bulk device is also provided. Project files are included to allow the exam-
ples to be built using Microsoft VisualStudio. Source code for this application can be found in directory
∼/utilities/tools/usb_throughput_bulk_example/Release.
After running the example in CCS Connect the USB Micro to the PC. Then the example will wait to receive data
from the application. Run the usb_throughput_bulk example, the throughput and Data Packets Transferred.

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6.217 Watchdog
This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By
default the example will generate a Wake interrupt. To service the watchdog and not generate the interrupt,
uncomment the SysCtl_serviceWatchdog() line in the main for loop.
External Connections

None.

Watch Variables

wakeCount - The number of times entered into the watchdog ISR

loopCount - The number of loops performed while not in ISR

6.218 CM Empty Project Example

This example is an empty project setup for Driverlib development for CM.

6.219 CPU1 Empty Project Example

This example is an empty project setup for Driverlib development for CPU1.

6.220 Flash Programming Solution using SCI.

In this example, we set up a UART connection with a host using SCI, receive commands for CPU1 to perform
which then sends ACK, NAK, and status packets back to the host after receiving and completing the tasks. This
kernel has the ability to program, verify, unlock, reset, and run an application. Each command either expects no
data from the command packet or specific data relative to the command.
In this example, we set up a UART connection with a host using SCI, receive an application for CPU01 in -sci8
ascii format to run on the device and program it into Flash.

6.221 LED Blinky Example (CM)

This example demonstrates how to blink a LED using CM.
External Connections

None.

Watch Variables

None.

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6.222 CAN External Loopback with Interrupts

This example sets up the CAN controller in External Loopback test mode using CPU2. The CAN peripheral is
configured to transmit messages with a specific CAN ID. A message is then transmitted once per second, using
a simple delay loop for timing. The message that is sent is a 4 byte message that contains an incrementing
pattern. A CAN interrupt handler is used to confirm message transmission and count the number of messages
that have been sent.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual. Refer to [Programming Examples and Debug
Strategies for the DCAN Module](www.ti.com/lit/SPRACE5) for useful information about this example
External Connections

None.

Watch Variables

txMsgCount - A counter for the number of messages sent

rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
errorFlag - A flag that indicates an error has occurred

6.223 EMIF1 ASYNC module accessing 16bit ASRAM through

CPU1 and CPU2.
This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip enable. The EMIF1 ownership is
passed between CPU1 and CPU2 to access different memory regions. Initially CPU2 grabs and configures the
EMIF1, thereafter both CPU1 and CPU2 grabs EMIF1 to access different memory regions in external memory.
External Connections

External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card

Watch Variables

testStatusGlobalCPU1 - Equivalent to TEST_PASS if test finished correctly, else the value is

set to TEST_FAIL
errCountGlobalCPU1 - Error counter

6.224 EMIF1 ASYNC module accessing 16bit ASRAM trhough

CPU1 and CPU2.
This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip enable. The EMIF1 ownership is
passed between CPU1 and CPU2 to access different memory regions. Initially CPU2 grabs and configures the

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EMIF1, thereafter both CPU1 and CPU2 grabs EMIF1 to access different memory regions in external memory.
External Connections

External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card

Watch Variables

testStatusGlobalCPU2 - Equivalent to TEST_PASS if test finished correctly, else the value is

set to TEST_FAIL
errCountGlobalCPU2 - Error counter

6.225 CM Empty Project Example

This example is an empty project setup for Driverlib development for CM.

6.226 Flash Programming with AutoECC, DataAndECC, DataOnly

and EccOnly
This example demonstrates how to program Flash using API’s following options 1. AutoEcc generation 2.
DataOnly and EccOnly 3. DataAndECC
Before running this example, please run the cm_common_config_c28x Example from the c28x folder. It will
initialize the clock, configure CPU1 Flash wait-states, fall back power mode, performance features and ECC.
External Connections

None.

Watch Variables

None.

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7 Dual Core Driver Library Example Applications

These example applications show how to make use of F2838x device functions which span both the CPU 1 and
CPU 2. All of these examples contain two example projects: one for CPU 1 and one for CPU 2.
Like the CPU1 only projects, these projects also contain different build configurations for RAM and Flash builds.
All of the CPU1 projects contain RAM and Flash build configurations with debugger support, as well as a
standalone flash build configuration which sends an IPC command to boot the second core and begin executing
the application in its flash. The CPU2 projects all only contain a flash and RAM build configuration as there are
no dependencies in the code regarding whether the application is running with or without a debugger.
All these examples are setup using the Code Composer Studio (CCS) "projectspec" format. For these dual core
example applications, the "projectspec" allows for two projects to be defined in one file. Upon importing the
"projectspec", the two example projects will be generated in the CCS workspace with copies of the source and
header files included for each project. All these examples contain two build configurations which allow you to
build each project to run from either RAM or Flash. To change how the project is built simply right click on the
project and select "Build Configurations". Then, move over to set the active build configuration, either RAM or
Flash.
The examples provided are built for controlCARD compatibility.
To run one of these examples after compiling it, load the appropriate programs on each of the two cores. Then,
for more example specific instructions please refer to the documentation regarding the example you wish to run
on the following pages or in the comments of the example sources.
All of these examples can be found in the
driverlib/f2838x/examples/c28x_dual subdirectory of the C2000Ware package.

7.1 NMI handling

This example demonstrates how to allocate CAN peripheral to CPU2.

7.2 Watchdog Reset

This example sets up the CAN controller in External Loopback test mode using CPU2
External Connections

None.

Watch Variables

msgCount - A counter for the number of successful messages received

txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received

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7.3 CLA arcsine(x) using a lookup table (cla_asin_cpu01)

In this example, cpu1 will be used to initialize the clocks Task 1 of the CLA on cpu2 will calculate the arcsine of
an input argument in the range (-1.0 to 1.0) using a lookup table. It is recommended to run the c28x1 core first,
followed by the C28x2 core.
Memory Allocation

CLA1 Math Tables (RAMLS0)

• CLAasinTable - Lookup table
CLA1 to CPU Message RAM
• fResult - Result of the lookup algorithm
CPU to CLA1 Message RAM
• fVal - Sample input to the lookup algorithm

Watch Variables

fVal - Argument to task 1

fResult - Result of arcsin(f V al)

7.4 CLA Arcsine Example.

Dual Core arcsine example. This example demonstrates how to run CLA tasks on cpu2.cla1 It is recommended
to run the c28x1 core first, followed by the C28x2 core.

7.5 CLA 2 Pole 2 Zero Infinite Impulse Response Filter

(cla_iir2p2z_cpu01)
This example implements a Transposed Direct Form II IIR filter, commonly known as a Biquad. The input vector
is a software simulated noisy signal that is fed to the biquad one sample at a time, filtered and then stored in an
output buffer for storage. It is recommended to run the c28x1 core first, followed by the C28x2 core.
Memory Allocation

CLA1 Data RAM 1 (RAML2)

• S1_A - Feedback coefficients
• S1_B - Feedforward coefficients
CLA1 to CPU Message RAM
• yn - Output of the Biquad
CPU to CLA1 Message RAM
• xn - Sample input to the filter

Watch Variables

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 Dual Core Driver Library Example Applications

fBiquadOutput
pass
fail

7.6 CLA 2-pole 2-zero IIR Filter Example for F2837xD.

Dual Core iir2p2z example. This example demonstrates how to run CLA tasks on cpu2.cla1 It is recommended
to run the c28x1 core first, followed by the C28x2 core.

7.7 DCSM Memory Access control by CPU1

This example demonstrates how to configure the 1st Zone Select Block in the OTP needed to allocate CPU2’s
LS4-LS5 to zone 1 & CPU2’s LS6-LS7 to zone 2, later accessed by CPU2.
Zone1 | Zone2 | CPU2’s LS4-LS5 | CPU2’s LS6-LS7 |
In this example, zoning of memories is done by the OTP programming whose values are configured in
dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file. It demon-
strates how to control the access of the memories which would later be accessed by CPU2. This would even do
a dummy read of the password needed by CPU2 to unsecure the memory. The communication between the 2
CPUs are done using IPC ( Inter process communication) through a sync function. This enables the CPU Core
to wait until the expected task is completed on the other core.
External Connections

None.

Watch Variables

result - Status of Memory Access control by CPU1

set_error - Count of errors occurring during the execution of the example.

Note:
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :

Allocate CPU2’s LS4-LS5 to zone 1 , LS6-LS7 to zone 2 ZSBx_Z1_GRABRAM3R

0x0000A500 ZSBx_Z2_GRABRAM3R 0x00005A00
Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF
Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF

7.8 DCSM Memory Access by CPU2

This example demonstrates how the access of the memory is affected when the memories are secured by
CPU1. CPU1 allocate CPU2’s LS4-LS5 to zone 1 & CPU2’s LS6-LS7 to zone 2 using the 1st Zone Select
Block.

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Zone1 | Zone2 | CPU2’s LS4-LS5 | CPU2’s LS6-LS7 |

It writes some data in the zones and checks after the CPU1 does a memory locking and matches with the data
set . Further, once the CPU2 unlocks the memories, it matches with the data set written before CPU1 lock.
Ideally after locking, zone1 should not be readable(or reads a 0 value) and zone2 that is not secured matches
the written data set. It demonstrates how to lock and and unlock zone by showing where to put the password
and how to check if it is secured or unsecured.
The communication between the 2 CPUs are handled using IPC (Inter process communication) through a synch
function. This enables the CPU Core to wait until the expected task is completed on the other core.
External Connections

None.

Watch Variables

result - Status of CPU2’s secure memory access

set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the
execution of the example.
Zone1_Locked_Array - Array demonstrating secured memory
Unsecure_mem_Array - Array demonstrating Unsecured memory

7.9 DMA Transfer Shared Peripheral

This example shows how to initiate a DMA transfer on CPU1 from a shared peripheral which is owned by CPU2.
In this specific example, a timer ISR is used on CPU2 to initiate a SPI transfer which will trigger the CPU1 DMA.
CPU1’s DMA will then in turn update the ePWM1 CMPA value for the PWM which it owns. The PWM output
can be observed on the GPIO pins. It is recommended to run the c28x1 core first, followed by the C28x2 core.
Watch Pins

GPIO0 and GPIO1 - ePWM output can be viewed with oscilloscope

7.10 DMA Transfer Shared Peripheral

This example shows how to initiate a DMA transfer on CPU1 from a shared peripheral which is owned by CPU2.
In this specific example, a timer ISR is used on CPU2 to initiate a SPI transfer which will trigger the CPU1 DMA.
CPU1’s DMA will then in turn update the ePWM1 CMPA value for the PWM which it owns. The PWM output
can be observed on the GPIO pins. It is recommended to run the c28x1 core first, followed by the C28x2 core.
Watch Pins

GPIO0 and GPIO1 - ePWM output can be viewed with oscilloscope

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7.11 CPU1 Empty Project Example >/h1> This example is an

empty project setup for Driverlib development for CPU1.
CPU2 Empty Project Example
This example is an empty project setup for Driverlib development for CPU2.

7.12 FSI Multi-Rx Tag-Match

Example sets up infinite data frame transfers where trigger happens through CPU. Multiple receivers receive
data as per the received frame tag.
This is a dual core example where FSITxA & FSIRxA instances are owned by CPU1 while FSIRxB, FSIRxC &
FSIRxD are owned by CPU2. Internal loopback mode is enabled for FSIRxA, FSIRxB, FSIRxC & FSIRxD which
connects data & clock lines of these receivers to FSITxA internally.
FSITxA infinitely sends data frames with alternating tag values. Receivers are configured to receive data frame
with different tag values with tag-match feature enabled. Tx doesn’t send next frame of data until it all receivers
receive the data. Synchronization among all the receivers is maintained through IPC flags.
User can edit some of configuration parameters as per usecase. These are as below. Default values can be
referred in code where these globals are defined:-

nWords - Number of words per transfer may be from 1 -16

nLanes - Choice to select single or double lane for frame transfers
fsiClock - FSI Clock used for transfers
txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers

For any errors during transfers i.e. error events such as Frame Overrun, Underrun, Watchdog timeout and
CRC/EOF/TYPE errors, execution will stop immediately and status variables can be looked into for more details.
Execution will also stop for any mismatch between received data and sent ones and also if transfers takes
unusually long time(detected through software counters - txTimeOutCntr and rxTimeOutCntr)
External Connections
For FSI internal loopback, no external connections needed
Watch Variables

dataFrameCntrA Number of Data frame transfered

error Non zero for transmit/receive data mismatch

7.13 FSI Multi-Rx Tag-Match

Example sets up infinite data frame transfers where trigger happens through CPU. Multiple receivers receive
data as per the received frame tag.

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This is a dual core example where FSITxA & FSIRxA instances are owned by CPU1 while FSIRxB, FSIRxC &
FSIRxD are owned by CPU2. Internal loopback mode is enabled for FSIRxA, FSIRxB, FSIRxC & FSIRxD which
connects data & clock lines of these receivers to FSITxA internally.
FSITxA infinitely sends data frames with alternating tag values. Receivers are configured to receive data frame
with different tag values with tag-match feature enabled. Tx doesn’t send next frame of data until it all receivers
receive the data. Synchronization among all the receivers is maintained through IPC flags.
User can edit some of configuration parameters as per usecase. These are as below. Default values can be
referred in code where these globals are defined:-

nWords - Number of words per transfer may be from 1 -16

nLanes - Choice to select single or double lane for frame transfers
fsiClock - FSI Clock used for transfers
txUserData - User data to be sent with Data frame
txDataFrameTag - Frame tag used for Data transfers

For any errors during transfers i.e. error events such as Frame Overrun, Underrun, Watchdog timeout and
CRC/EOF/TYPE errors, execution will stop immediately and status variables can be looked into for more details.
Execution will also stop for any mismatch between received data and sent ones and also if transfers takes
unusually long time(detected through software counters - txTimeOutCntr and rxTimeOutCntr)
External Connections
For FSI internal loopback, no external connections needed
Watch Variables

dataFrameCntrB Number of Data frame received by FSIRxB

dataFrameCntrC Number of Data frame received by FSIRxC
dataFrameCntrD Number of Data frame received by FSIRxD
error Non zero for transmit/receive data mismatch

7.14 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core without
message queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

pass

7.15 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core without
message queues It is recommended to run the C28x1 core first, followed by the C28x2 core.

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External Connections

None.

Watch Variables

None.

7.16 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core with message
queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

pass

7.17 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core with message
queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

None.

7.18 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core without
message queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

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pass

7.19 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core without
message queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

None.

7.20 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core with message
queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

pass

7.21 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x1 to C28x2 core with message
queues. It is recommended to run the C28x1 core first, followed by the C28x2 core.
External Connections

None.

Watch Variables

None.

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7.22 LED Blinky Example

This example demonstrates how to blink a LED using CPU1 and blink another LED using CPU2
(led_ex1_blinky_cpu2.c).
External Connections

None.

Watch Variables

None.

7.23 LED Blinky Example

This example demonstrates how to blink a LED using CPU1 and blink another LED using CPU2
(led_ex1_blinky_cpu2.c).
External Connections

None.

Watch Variables

None.

7.24 Shared RAM Management (CPU1)

This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

cpu1RWArray[] is mapped to shared RAM GS1

cpu1RArray[] is mapped to shared RAM GS0
cpu2RArray[] is mapped to shared RAM GS1
cpu2RWArray[] is mapped to shared RAM GS0
cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1

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cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

Watch Variables

error Indicates that the data written is not correctly received by the other CPU.

7.25 Shared RAM Management (CPU2)

This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

cpu1RWArray[] is mapped to shared RAM GS1

cpu1RArray[] is mapped to shared RAM GS0
cpu2RArray[] is mapped to shared RAM GS1
cpu2RWArray[] is mapped to shared RAM GS0
cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

7.26 Shared RAM Management (CPU1)

This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

cpu1RWArray[] is mapped to shared RAM GS1

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cpu1RArray[] is mapped to shared RAM GS0

cpu2RArray[] is mapped to shared RAM GS1
cpu2RWArray[] is mapped to shared RAM GS0
cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

Watch Variables

error Indicates that the data written is not correctly received by the other CPU.

7.27 Shared RAM Management (CPU2)

This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.

cpu1RWArray[] is mapped to shared RAM GS1

cpu1RArray[] is mapped to shared RAM GS0
cpu2RArray[] is mapped to shared RAM GS1
cpu2RWArray[] is mapped to shared RAM GS0
cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

7.28 NMI handling

This example demonstrates how to handle an NMI.
The watchdog of CPU2 is configured to reset the core once the watchdog overflows and in the CPU1 the NMI
is triggered. The NMI status is read and is verified to be due to CPU2 Watchdog reset. The NMI ISR reboots
the CPU2 core and the process is repeated.
Watch Variables

nmi_isr_count Indicates the number of times the NMI ISR was hit because of CPU2 watchdog
reset.

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7.29 Watchdog Reset

This example shows how to configure the watchdog to reset CPU2 which will trigger an NMI in CPU1. LED1 is
toggled at the start of main indicating CPU reset.
External Connections

None.

Watch Variables

loopCount - The number of loops performed while not in ISR

7.30 NMI handling

This example demonstrates how to handle an NMI.
The watchdog of CPU2 is configured to reset the core once the watchdog overflows and in the CPU1 the NMI
is triggered. The NMI status is read and is verified to be due to CPU2 Watchdog reset. The NMI ISR reboots
the CPU2 core and the process is repeated.
Watch Variables

nmi_isr_count Indicates the number of times the NMI ISR was hit because of CPU2 watchdog
reset.

7.31 Watchdog Reset

This example shows how to configure the watchdog to reset CPU2 which will trigger an NMI in CPU1. LED1 is
toggled at the start of main indicating CPU reset.
External Connections

None.

Watch Variables

loopCount - The number of loops performed while not in ISR

7.32 NMI handling

This example demonstrates how to handle an NMI.
The watchdog of CPU2 is configured to reset the core once the watchdog overflows and in the CPU1 the NMI
is triggered. The NMI status is read and is verified to be due to CPU2 Watchdog reset. The NMI ISR reboots
the CPU2 core and the process is repeated.
Watch Variables

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nmi_isr_count Indicates the number of times the NMI ISR was hit because of CPU2 watchdog
reset.

7.33 Watchdog Reset

This example shows how to configure the watchdog to reset CPU2 which will trigger an NMI in CPU1. LED1 is
toggled at the start of main indicating CPU reset.
External Connections

None.

Watch Variables

loopCount - The number of loops performed while not in ISR

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 C28x and CM Dual Driver Library Example Applications

8 C28x and CM Dual Driver Library Example

Applications
These example applications show how to make use of F2838x device functions which span both the C28x and
CM. All of these examples contain two example projects: one for C28x and one for CM.
Like the CPU1 only projects, these projects also contain different build configurations for RAM and Flash builds.
All of the C28x projects contain RAM and Flash build configurations with debugger support, as well as a stan-
dalone flash build configuration which sends an IPC command to boot the second core and begin executing the
application in its flash. The CPU2 projects all only contain a flash and RAM build configuration as there are no
dependencies in the code regarding whether the application is running with or without a debugger.
All these examples are setup using the Code Composer Studio (CCS) "projectspec" format. For these dual core
example applications, the "projectspec" allows for two projects to be defined in one file. Upon importing the
"projectspec", the two example projects will be generated in the CCS workspace with copies of the source and
header files included for each project. All these examples contain two build configurations which allow you to
build each project to run from either RAM or Flash. To change how the project is built simply right click on the
project and select "Build Configurations". Then, move over to set the active build configuration, either RAM or
Flash.
The examples provided are built for controlCARD compatibility.
To run one of these examples after compiling it, load the appropriate programs on each of the two cores. Then,
for more example specific instructions please refer to the documentation regarding the example you wish to run
on the following pages or in the comments of the example sources.
All of these examples can be found in the
driverlib/f2838x/examples/c28x_cm subdirectory of the C2000Ware package.

8.1 DCSM Memory Access by CM

This example demonstrates how the access of the memory is affected when the memories are secured by
CPU1. CPU1 allocate CM’s C0RAM to zone 1 & CM’s C1RAM to zone 2 using the 1st Zone Select Block.
Zone1 | Zone2 | CM’s C0RAM | CM’s C1RAM |
It writes some data in the zones and checks after the CPU1 does a memory locking and matches with the data
set . Further, once the CM unlocks the memories, it matches with the data set written before CPU1 lock. Ideally
after locking, zone1 should not be readable(or reads a 0 value) and zone2 that is not secured matches the
written data set. It demonstrates how to lock and and unlock zone by showing where to put the password and
how to check if it is secured or unsecured.
The communication between the 2 CPUs are handled using IPC (Inter process communication) through a sync
function. This enables the CPU Core to wait until the expected task is completed on the other core.
External Connections

None.

Watch Variables

result - Status of CM’s secure memory access

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set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the

execution of the example.
Zone1_Locked_Array - Array demonstrating secured memory
Unsecure_mem_Array - Array demonstrating Unsecured memory

8.2 DCSM Memory Access control by master CPU1

This example demonstrates how to configure the 1st Zone Select Block in the OTP to allocate CM’s C0RAM to
zone 1 & CM’s C1RAM to zone 2, later accessed by CM.
Zone1 | Zone2 | CM’s C0RAM | CM’s C1RAM |
In this example, zoning of memories is done by the OTP programming whose values are configured in
dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file. It demon-
strates how to control the access of the memories which would later be accessed by CM. This would even do a
dummy read of the password needed by CM to unsecure the memory. The communication between the 2 CPUs
are done using IPC ( Inter process communication) through a synch function. This enables the CPU Core to
wait until the expected task is completed on the other core.
External Connections

None.

Watch Variables

result - Status of Memory Access control by CPU1

set_error - Count of errors occurring during the execution of the example.

Note:
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :

Allocate CM’s C0RAM to zone 1 , C1RAM to zone 2 ZSBx_Z1_GRABRAM2R 0x0AAAAA09

ZSBx_Z2_GRABRAM2R 0x0AAAAA06
Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF
Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF

8.3 Ethernet + IPC basic message passing example with inter-

rupt
This example demonstrates how to configure IPC and pass information from C28x to CM core without message
queues. This configures the Pinmux for Ethernet Prepares the Ethernet frame that is sent to the CM core over
IPC Message RAM. Uses the IPC command interface to signal the IPC Command, Packet address, Packet
Length which is used by CM side code to send it on the Ethernet Line, which is acknowledged by the CM core
side code over IPC on succesfully receiving a packet It is recommended to run the C28x1 core first, followed by
the CM core.
External Connections

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Connections for Ethernet in MII mode

Watch Variables

pass

8.4 Ethernet + IPC basic message passing example with inter-

rupt
This example demonstrates how to receive the message passed from C28x side containing the Ethernet Packet
over IPC,sends the packet on Ethernet acknowledge the packet received over IPC to C28x core. This extends
the IPC Example. Uses IPC C28x to CM core without message queues. It can be used as a reference for flow
using Ethernet and IPC together. If the Packet data received over Ethernet is to be passed to C28x for control
applications, it can send IPC message to C28x. It is recommended to run the C28x1 core first, followed by the
CM core. The example actually uses the internal loopback mode of MAC hence the MII Tx and Rx signals are
not used, but needs the MII Tx and Rx Clock signals which comes from the External PHY.
External Connections

MII connections on Control card

Watch Variables

None.

8.5 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x to CM core without message
queues. It is recommended to run the C28x1 core first, followed by the CM core.
External Connections

None.

Watch Variables

pass

8.6 IPC basic message passing example with interrupt

This example demonstrates how to configure IPC and pass information from C28x to CM core without message
queues It is recommended to run the C28x1 core first, followed by the CM core.
External Connections

None.

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Watch Variables

None.

8.7 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x to CM core with message
queues. It is recommended to run the C28x1 core first, followed by the CM core.
External Connections

None.

Watch Variables

pass

8.8 IPC message passing example with interrupt and message

queue
This example demonstrates how to configure IPC and pass information from C28x to CM core with message
queues. It is recommended to run the C28x1 core first, followed by the CM core.
External Connections

None.

Watch Variables

None.

8.9 LED Blinky Example

This example demonstrates how to blink a LED using CPU1 and blink another LED using CM
(led_ex1_blinky_cm.c).
External Connections

None.

Watch Variables

None.

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 CM Driver Library Example Applications

9 CM Driver Library Example Applications

These example applications show how to make use of various peripherals of a CM F2838x device. These
applications are intended for demonstration and as a starting point for new applications.
All these examples are setup using the Code Composer Studio (CCS) "projectspec" format. Upon importing
the "projectspec", the example project will be generated in the CCS workspace with copies of the source and
header files included.
All these examples contain two build configurations which allow you to build each project to run from either RAM
or Flash. To change how the project is built simply right click on the project and select "Build Configurations".
Then, move over to set the active build configuration, either RAM or Flash.
The examples provided are built for controlCARD compatibility.
There may be a few examples which need either an external hardware or device not present on the controlCARD
like Ethernet in RevMII mode.
Because CPU 1 is ultimately in control of the entire F2838x device. The config c28x example sets up all of the
peripherals and GPIOs to be owned by CM.
All of these examples reside in the driverlib/f2838x/examples/cm subdirectory of the C2000Ware pack-
age.

9.1 AES ECB Encryption Example (CM)

This example encrypts block cipher-text using AES128 in ECB mode. It does the encryption first without uDMA
and then with uDMA. The results are checked after each operation.
External Connections

None

Watch Variables

errCountGlobal - Error Counter. It should be zero.

testStatusGlobal - Test status. It should be equal to PASS.

9.2 AES ECB De-cryption Example (CM)

This example de-crypts block cipher-text using AES128 in ECB mode. It does the de-cryption first without uDMA
and then with uDMA. The results are checked after each operation.
External Connections

None

Watch Variables

errCountGlobal - Error Counter. It should be zero.

testStatusGlobal - Test status. It should be equal to PASS.

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9.3 AES GCM Encryption Example (CM)

This example encrypts block cipher-text using AES128 in GCM mode. It does the encryption first without uDMA
and then with uDMA. The results are checked after each operation.
External Connections

None

Watch Variables

errorCountGlobal - Error Counter. It should be zero.

testStatusGlobal - Test status. It should be equal to PASS.

9.4 AES GCM Decryption Example (CM)

This example decrypts block cipher-text using AES128 in GCM mode. It does the decryption first without uDMA
and then with uDMA. The results are checked after each operation.
External Connections

None

Watch Variables

errorCountGlobal - Error Counter. It should be zero.

testStatusGlobal - Test status. It should be equal to PASS.

9.5 CAN Loopback

This example shows the basic setup of CAN in order to transmit and receive messages on the CAN bus. The
CAN peripheral is configured to transmit messages with a specific CAN ID. The message that is sent is a 2 byte
message that contains an incrementing pattern.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual.
Before running this example, please run the can_config_c28x example from the c28x folder. It will initialize the
clock, configure the GPIOs and allocate CAN A to CM.
External Connections

None.

Watch Variables

msgCount - A counter for the number of successful messages received.

rxMsgData - An array with the data that was received.
txMsgData - An array with the data being sent.

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 CM Driver Library Example Applications

9.6 CAN External Loopback with Interrupts

This example shows the basic setup of CAN in order to transmit and receive messages on the CAN bus. The
CAN peripheral is configured to transmit messages with a specific CAN ID. A message is then transmitted once
per second, using a simple delay loop for timing. The message that is sent is a 4 byte message that contains an
incrementing pattern. A CAN interrupt handler is used to confirm message transmission and count the number
of messages that have been sent.
This example sets up the CAN controller in External Loopback test mode. Data transmitted is visible on the
CANTXA pin and is received internally back to the CAN Core. Please refer to details of the External Loopback
Test Mode in the CAN Chapter in the Technical Reference Manual.
Before running this example, please run the can_config_c28x example from the c28x folder. It will initialize the
clock, configure the GPIOs and allocate CAN A to CM.
External Connections

None.

Watch Variables

txMsgCount - A counter for the number of messages sent

rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
errorFlag - A flag that indicates an error has occurred

9.7 CAN-A to CAN-B External Transmit

This example initializes CAN module A and CAN module B for external communication. CAN-A module is setup
to transmit incrementing data for "n" number of times to the CAN-B module, where "n" is the value of TXCOUNT.
CAN-B module is setup to trigger an interrupt service routine (ISR) when data is received. An error flag will be
set if the transmitted data doesn’t match the received data.
Before running this example, please run the can_config_c28x example from the c28x folder. It will initialize the
clock, configure the GPIOs and allocate CAN A and CAN B to CM.

Note:
Both CAN modules on the device need to be connected to each other via CAN transceivers.

Hardware Required

A C2000 board with two CAN transceivers

External Connections

ControlCARD CANA is on GPIO37 (CANTXA) and GPIO36 (CANRXA)

ControlCARD CANB is on GPIO12 (CANTXB) and GPIO10 (CANRXB)

Watch Variables

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TXCOUNT - Adjust to set the number of messages to be transmitted

txMsgCount - A counter for the number of messages sent
rxMsgCount - A counter for the number of messages received
txMsgData - An array with the data being sent
rxMsgData - An array with the data that was received
errorFlag - A flag that indicates an error has occurred

9.8 CAN Transmit and Receive Configurations

This example shows the basic setup of CAN in order to transmit or receive messages on the CAN bus with a
specific Message ID. The CAN Controller is configured according to the selection of the define.
When the TRANSMIT define is selected, the CAN Controller acts as a Transmitter and sends data to the second
CAN Controller connected externally.If TRANMSIT is not defined the CAN Controller acts as a Receiver and
waits for message to be transmitted by the External CAN Controller.
Before running this example, please run the can_config_c28x example from the c28x folder. It will initialize the
clock, configure the GPIOs and allocate CAN A to CM.

Note:
CAN modules on the device need to be connected to via CAN transceivers.

Hardware Required

A C2000 board with CAN transceiver.

External Connections

ControlCARD CANA is on GPIO37 (CANTXA) and GPIO36 (CANRXA)

Watch Variables Transmit

MSGCOUNT - Adjust to set the number of messages

txMsgCount - A counter for the number of messages sent
txMsgData - An array with the data being sent
errorFlag - A flag that indicates an error has occurred
rxMsgCount - Has the initial value as No. of Messages to be received and decrements with
each message.

9.9 Demonstrate DMPU usage.

This example demonstrates how to configure CM-MPU for uDMA transfer. uDMA is configured to transfer data
between two memory regions and DMPU is configured to demonstrate memory access protection in uDMA
associated memory regions
The following memory map is set up: -Region 0 - uDMA source buffer -Region 1 - uDMA control table -Region
2 - uDMA destination buffer
External Connections

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 CM Driver Library Example Applications

None

Watch Variables

faultCount - Count for uDMA access faults. This should be non zero.
errCountGlobal - Error Counter. This should be zero.
memTransferCount - Count of memory uDMA transfer blocks

9.10 Demonstrate CM-MPU sub-region configurations

This example demonstrates how to configure sub-regions in CM-MPU for uDMA transfer between memory
regions of desired size. Sub-regions are configured to get desired region size of 6k.
The following memory map is set up: -Region 0 - uDMA source buffer -Region 1 - uDMA control table -Region
2 - uDMA destination buffer
External Connections

None

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
faultCount - Count for uDMA access faults. This should be non zero.
errCountGlobal - Error Counter for valid memory transfers. This should be zero.
memTransferCount - Count of memory uDMA transfer blocks

9.11 Ethernet Low Latency Interrupt

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to handle the Ethernet transmit,receive with minimum latency interrupts. The example interrupt
handlers provided in the Ethernet driver help to achieve user friendly buffer management and the generic inter-
rupt handler handles different interrupt sources, these factors might be more cycle consuming. This example
demonstrates how to achieve lowest possible latency with interrupts and buffer management with the Ethernet
Driver. Before running this Communication Manager code the C28x cpu1 code has to be run to configure the
clocks to Communication manager and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in Internal Loop back mode and hence needs no external connec-
tion on the MII Data lines. But it needs the MII Tx and Rx clocks to be input on those pins Refer to the C28x
CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the PHY
Watch Variables

genericISRCount
transmitISRCount
receiveISRCount

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9.12 Ethernet MAC Internal Loopback

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module and Configure the module in MAC Loop back mode Prepares a
packet to be sent, Sends the packet and reads the statistics to check if the packet is received by the module
Before running this Communication Manager code the C28x cpu1 code has to be run to configure the clocks to
Communication manager and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in Internal Loop back mode and hence needs no external connec-
tion on the MII Data lines. But it needs the MII Tx and Rx clocks to be input on those pins Refer to the C28x
CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the PHY
Watch Variables

None

9.13 Ethernet Basic Transmit and Receive PHY Loopback

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module and Configure the module in External Loop back mode the packet
is looped back at external PHY. Prepares a packet to be sent, Sends the packet and reads the staticstics to
check if the packet is received by the module Before running this Communication Manager code the C28x
cpu1 code has to be run to configure the clocks to Communication manager and required IO pads for Ethernet
module
External Connections
This example programs the Ethernet module in External Loop back mode (at PHY) and hence needs external
connection to the PHY on the MII interface and also the MDIO Pins connected to the PHY. This example
assumes DP83822 PHY for the PHY configurations if a different PHY is used the sequences might change
Refer to the C28x CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the
PHY
Watch Variables

phyRegContent variable can be checked to know if PHY register read,write is working correctly
• stats to know if the packet is received correctly after loopback at PHY side

9.14 Ethernet Threshold mode with level PHY loopback

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module in Threshold mode It Configures the module in MII External Loop
back mode in which the packet is looped back at external PHY. Prepares a packet to be sent, Sends the
packet and reads the staticstics to check if the packet is received by the module It configures the Transmit and
Receive queues of Ethernet DMA in Threshold mode. The Transmit threshold mode generates early transmit
interrupts when each buffer is transmitted from the memory into the transmit FIFO. The Buffer can be reclaimed
by the application. The Receive threshold mode generates early receive interrupts where the module generates
Early receive interrupts when programmed threshold buffer size is transferred into receive buffer memory from

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the receive FIFO. This will be of use when dealing with Time critical receive paths where the application can
consume the packets at programmed burstLength unlike the conventional Store and Forward mode(Default)
where the module generates the interrupts when the complete packet is transmitted on the Line and when the
complete packet is received and checksum validation is succesful This example provides a starting point for
configuring the threshold mode. Refer to the Driver API guide for the different callbacks available in the driver.
It uses the example Interrupt Service Routines provided in the driver library. Users can modify those ISRs or
write another as per their need. Before running this Communication Manager code the C28x cpu1 code has to
be run to configure the clocks to Communication manager and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in External Loop back mode (at PHY) and hence needs external
connection to the PHY on the MII interface and also the MDIO Pins connected to the PHY. This example
assumes DP83822 PHY for the PHY configurations if a different PHY is used the sequences might change.
Refer to the C28x CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the
PHY
Watch Variables

phyRegContent variable can be checked to know if PHY register read,write is working correctly
Ethernet_txInterruptCount - this variable available in driver library provides a count of number
of times Transmit completion interrupt (on full packet transmission onto the line) occured
Ethernet_rxInterruptCount - this variable provides a count of number of times the complete
Receive completion interrupt occured
Ethernet_earlyRxInterruptCount - the number of times the early receive interrupt occured. This
depends on the burstLength configured
Ethernet_earlyTxInterruptCount - the number of times the early transmit interrupt occured.
This depends on the number of fragments of the packets transmitted

9.15 Ethernet PTP Basic Master

This example configures the device in IEEE PTPv2 Master mode and then periodically sends Sync packets to
the slave. On receiving the DelayReq packets from the slave, the master also sends out the DelayResp packets.
External Connections
This example programs the Ethernet module in PTP Basic Master mode. The example project Ethernet PTP
Basic Slave is intended to be used along with this project to see the whole PTP Protocol state in action. The
second device is configured as Slave and both devices in conjunction exchange Sync, DelayReq and DelayResp
packets.
Refer to the C28x CPU1 code of ethernet_config_c28x project for configuring the PTP clock that drives the
system time counter on the Ethernet module.
Watch Variables

gPtpMasterState

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9.16 Ethernet PTP Basic Slave

This example configures the device in IEEE PTPv2 Slave mode and then waits for the Sync packets from
the slave. On receiving configurable number of Sync packets from the master, the slave also sends out the
DelayReq packets. In response to the DelayReq packets, the Master also sends out the DelayResp packets
which is then received by the Slave. The slave parallely maintains the internal state of the PTP in terms of
Master to Slave Delay and Slave to Master Delay . Consequently, the slave also calculates Offset From Master
and Mean Path Delay .
External Connections
This example programs the Ethernet module in PTP Basic Slave mode. The example project Ethernet PTP
Basic Master is intended to be used along with this project to see the whole PTP Protocol state in action.
The second device is configured as Master and both devices in conjunction exchange Sync, DelayReq and
DelayResp packets.
Refer to the C28x CPU1 code of ethernet_config_c28x project for configuring the PTP clock that drives the
system time counter on the Ethernet module.
Watch Variables

gPtpSlaveState

9.17 Ethernet PTP Offload Master

This example configures the device in IEEE PTPv2 Master mode and sets the options that are needed by the
offload engine to operate such as the domainNumber , LogSyncInterval among others. After that it enables
sending SYNC messages periodically according to the interval already set previously.
External Connections
This example programs the Ethernet module in PTP Offload Master mode. The example project Ethernet PTP
Offload Slave is intended to be used along with this project to see the whole PTP Offload engine in action. The
second device is configured as Slave and both devices in conjunction exchange Sync, DelayReq and DelayResp
packets.
Refer to the C28x CPU1 code of ethernet_config_c28x project for configuring the PTP clock that drives the
system time counter on the Ethernet module.
Watch Variables

Ethernet_ptpDelayReqPktCount

9.18 Ethernet PTP Offload Slave

This example configures the device in IEEE PTPv2 Slave mode and sets the options that are needed by the
offload engine to operate such as the domainNumber , LogSyncInterval among others. After that it enables
sending DelayReq messages periodically for every configurable number of Sync packets.
External Connections
This example programs the Ethernet module in PTP Offload Slave mode. The example project Ethernet PTP

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Offload Master is intended to be used along with this project to see the whole PTP Offload engine in action.
The second device is configured as Slave and both devices in conjunction exchange Sync, DelayReq and
DelayResp packets.
Refer to the C28x CPU1 code of ethernet_config_c28x project for configuring the PTP clock that drives the
system time counter on the Ethernet module.
Watch Variables

Ethernet_ptpSyncPktCount
Ethernet_ptpDelayRespPktCount

9.19 Ethernet MAC CRC and Checksum Offload

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager Sub-
system to initialize the Ethernet module and Configure the module in MAC Loop back mode. Demonstrates
how to program the CRC offload and Checksum Offload(IP Checksum) Prepares a packet to be sent, Sends
the packet and reads the statistics to check if the packet is received by the module Before running this Commu-
nication Manager code the C28x cpu1 code has to be run to configure the clocks to Communication manager
and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in Internal Loop back mode and hence needs no external connec-
tion on the MII Data lines. But it needs the MII Tx and Rx clocks to be input on those pins Refer to the C28x
CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the PHY
Watch Variables

None

9.20 Ethernet Transmit Segmentation Offload

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module and Configure the module in MAC Loop back mode. Demonstrates
how to program the Transport Segmentation Offload feature in the Low level driver which in turn programs
the feature in the hardware The Hardware segments a single packet into configured segment size Prepares a
packet to be sent, Sends the packet and reads the statistics to check if the packet is received by the module
Before running this Communication Manager code the C28x cpu1 code has to be run to configure the clocks to
Communication manager and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in Internal Loop back mode and hence needs no external connec-
tion on the MII Data lines. But it needs the MII Tx and Rx clocks to be input on those pins Refer to the C28x
CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the PHY
Watch Variables

None

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9.21 Ethernet MAC Internal Loopback

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module and Configure the module in MAC Loop back mode The packet
sent is inserted with a VLAN tag. A VLAN filter is configured to route it to a different channel Prepares a
packet to be sent, Sends the packet and reads the statistics to check if the packet is received by the module
Before running this Communication Manager code the C28x cpu1 code has to be run to configure the clocks to
Communication manager and required IO pads for Ethernet module
External Connections
This example programs the Ethernet module in Internal Loop back mode and hence needs no external connec-
tion on the MII Data lines. But it needs the MII Tx and Rx clocks to be input on those pins Refer to the C28x
CPU1 code of ethernet_config_c28x project for which GPIOs are used for connecting to the PHY
Watch Variables

None

9.22 Ethernet RevMII Example MII side

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager Sub-
system to initialize the Ethernet module and Configure the module in MII mode. The other device is running
a RevMII mode This demonstrates the sequence for MII - RevMII communication Before running this Commu-
nication Manager code the C28x cpu1 code has to be run to configure the clocks to Communication manager
and required IO pads for Ethernet module This Example has been validated on an TI internal board and will not
run on Control Card. This has been run with RevMII Example Remote MAC side. Once the RevMII mode is
configured this appears like a PHY to the external MAC which is connected over MDIO. Even though there is
no physical PHY the RevMII mode lets the remote MAC see this side as a MAC.
External Connections
TBD
Watch Variables

None

9.23 Ethernet RevMII Example RevMII side

This example demonstrates the steps to be followed in using the Ethernet of the Communication Manager
Subsystem to initialize the Ethernet module and Configure the module in RevMII mode. Before running this
Communication Manager code the C28x cpu1 code has to be run to configure the clocks to Communication
manager and required IO pads for Ethernet module This Example has been validated on an TI internal board
and will not run on Control Card. This has been run with RevMII Example Remote MAC side. Once the RevMII
mode is configured this appears like a PHY to the external MAC which is connected over MDIO. Even though
there is no physical PHY the RevMII mode lets the remote MAC see this side as a PHY.
External Connections
TBD

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Watch Variables

None

9.24 Flash ECC Test Mode

This example demonstrates ECC Test mode.

9.25 GCRC example

This example showcases how to use GCRC to compute CRC for a 8-bit array. This demonstrates 2 methods for
computing the CRC cm_common_config_c28x example needs to be run on C28x1 before running this example
on the CM core
External Connections

None

Watch Variables

crcResult1 - CRC value computed using Method 1

crcResult2 - CRC value computed using Method 2
crcGolden - Golden CRC value

9.26 I2C Loopback with Slave Receive Interrupt

This program shows how to configure a receive interrupt on the slave module. This includes setting up the I2C0
module for loopback mode as well as configuring the master and slave modules. Loopback mode internally
connects the master and slave data and clock lines together. The address of the slave module is set to a value
so it can receive data from the master.
This is a 7-bit slave module address sent in the following format: [A6:A5:A4:A3:A2:A1:A0:RS]
A zero in the R/S position of the first byte means that the master transmits (sends) data to the selected slave,
and a one in this position means that the master receives data from the slave.
External Connections

None

Watch Variables

ui32DataTx - Data to send

ui32DataRx - Received data
result - Status of the I2C communication

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9.27 MCAN Internal Loopback with Interrupt

This example demonstrates Loopback functionality of the MCAN (CAN FD) module. The internal loopback
mode is chosen. The transmitted message will be received by the node. All action is internal to the device,
hence transmission will not be visible on the MCAN_TX pin. Uses the last address of memory for Rx buffer.
Before running this example, please run the mcan_config_c28x example It will initialize the clock, configure the
GPIOs.
External Connections

None.

Watch Variables

error - Checks if there is an error that occurred when the data was sent using internal loopback.

9.28 MCAN External Loopback with Interrupt

This example shows the MCAN External Loopback functionality. The external loopback is done between two
MCAN Controllers. As there is only one MCAN that exist this example can be changed to make MCAN Transmit
or Receive based on define selected. The GPIOs of MCAN should be connected to a CAN Transceiver
Before running this example, please run the mcan_config_c28x example It will initialize the clock, configure the
GPIOs.
Selection of Mode : A define has to be selected to make the MCAN to transmit or receive.

TRANSMIT - MCAN to Transmit messages.

RECEIVE - MCAN to Receive Messages.

Run the example as with RECEIVE Define on one MCAN Controller before running it as Transmit.
Hardware Required

A C2000 board with CAN transceiver

External Connections

MCAN is on GPIO30 (MCANRXA) and GPIO31 (MCANTXA)

Watch Variables

isrIntr0Flag - The flag has initial value as no. of messages to be transmitted and its value
decrements after a message is transmitted.
isrIntr1Flag - The flag has initial value as no. of messages that are received and its value
decrements after a message is successfully received.
error - Checks if there is an error that occurred when the data was sent using internal loopback

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9.29 Demonstrate memconfig diagnostics and error handling.

This example demonstrates how to configure the diagnostic mode and induce ECC errors. This example in-
duces single and two bit ECC errors in E0RAM and tries to read the corrupted location in diagnostic and
functional mode. cm_common_config_c28x example needs to be run on C28x1 before running this example on
the CM core
External Connections

None

Watch Variables

testStatus - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL
errorGlobalCount - Error counter
retx - Individual test status

9.30 Demonstrate CM4 MPU usage.

This example demonstrates how to configure MPU regions for different levels of memory protection using core
MPU. It demonstrates the use of the MPU to protect a region of memory from access, and to handle a memory
management fault when there is an access violation.
The following memory map is set up: -Region 0 - executable, prv(r/w), user(r/w) -Region 1 - executable,
prv(read only), user(read only), code mem(RAM) -Region 2 - executable, prv(read only), user(read only), code
mem(RAM) -Region 3 - non-exec, prv(r/w), user(r/w), for NVIC -Region 4 - non-exec, prv(read only), user(none)
-Region 5 - non-exec, prv(none), user(none) -Region 6 - non-exec, prv(read only), user(read only) -Region 7
- non-exec, prv (r/w), user (none)
External Connections

None

Watch Variables

testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to
TEST_FAIL

9.31 SSI Loopback example with interrupts

This example showcases how to use SSI to transfer and receive data in loopback mode
cm_common_config_c28x example needs to be run on C28x1 before running this example on the CM
core
Configuration:

Frame format : TI mode

Baud rate : 625000

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Data width : 12 bits

External Connections

None

Watch Variables

txData - Data transmitted

rxData - Data received
errCount - Error count

9.32 SSI Loopback example with UDMA

This example showcases how to use UDMA with SSI to transfer and receive data
This configures the SSI in loopback mode and sends and receives data for infinite time.
cm_common_config_c28x example needs to be run on C28x1 before running this example on the CM
core
Configuration:

Frame format : TI mode

Baud rate : 625000
Data width : 16 bits

External Connections

None

Watch Variables

TxData - Data transmitted

RxData - Data received
errCount - Error count

9.33 Systick interrupt example

This example showcases how to use configure Systick interrupt. It increments a counter every time the SysTick
interrupt is asserted cm_common_config_c28x example needs to be run on C28x1 before running this example
on the CM core
External Connections

None

Watch Variables

isrCount - ISR counter

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9.34 CPU Timers

This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
Before running this example, please run the cm_common_config_c28x Example from the c28x folder. It will
initialize the clock and configure the GPIOs.
External Connections

None

Watch Variables

cpuTimer0IntCount
cpuTimer1IntCount
cpuTimer2IntCount

9.35 UART Echoback

This test receives and echo-backs data through the UART0 port.
A terminal such as ’putty’ can be used to view the data from the CM-UART and to send information to the
CM-UART. Characters received by the CM-UART port are sent back to the host.
Running the Application Open a COM port with the following settings using a terminal:

Find correct COM port

Bits per second = 115200
Data Bits = 8
Parity = None
Stop Bits = 1
Hardware Control = None

The program will print out a greeting and then ask you to enter a character which it will echo back to the terminal.
Watch Variables

None

External Connections
Connect the UART0 port to a PC via a transceiver and cable.

GPIO85 is UART0RX/CMUARTRXA(Connect to Pin3, PC-TX, of serial DB9 cable)

GPIO84 is UART0TX/CMUARTTXA(Connect to Pin2, PC-RX, of serial DB9 cable)

Note:
The pin muxing for the UART0 port needs to be done by the master CPU1. The common
configuration example provided in the C28x folder can be used for making GPIO85 as the
UART Rx pin and GPIO84 as the UART Tx pin.

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9.36 UART Loopback example with UDMA

This example showcases how to use UDMA with UART to transfer and receive data
This configures the UART in loopback mode and sends and receives data for infinite time.
cm_common_config_c28x example needs to be run on C28x1 before running this example on the CM core
Configuration:

Find correct COM port

Bits per second = 115200
Data Bits = 8
Parity = None
Stop Bits = 1
Hardware Control = None

External Connections

None

Watch Variables

TxData - Data transmitted

RxData - Data received
errCount - Error count

9.37 uDMA RAM to RAM transfer

This example showcases how to use uDMA to transfer data from one RAM location to another using software
trigger.
This configures the UDMA in AUTO mode and transfers 32-bit words from one location to another using Channel
30. Software trigger is being used here. Once the transfer is completed, a check of the validity of the data will
be performed in the uDMA ISR.
External Connections

None

Watch Variables

srcData - Source
destData - Destination
errCount - Error count

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9.38 uDMA RAM to RAM transfer

This example showcases how to configure uDMA in memory scatter-gather mode and transfer data from varied
locations in memory rather than a set of contiguous locations in a memory buffer.
This example creates an array of structs of length 20. The struct includes a header element and a data element,
each of length 10. The UDMA is configured to tranfer only the data element from all the 20 data packets.
External Connections

None

Watch Variables

packets - ’data’ element contains the actual data to be transferred

consolidatedData - Destination buffer where the data is transferred to
errCount - Error count

9.39 USB Composite Serial Device (usb_dev_cserial)

This example application turns the evaluation kit into a virtual serial port when connected to the USB host
system. The application supports the USB Communication Device Class, Abstract Control Model to redirect
UART0 traffic to and from the USB host system.
Connect USB cables from your PC to both the mini and microUSB connectors on the controlCARD.Figure out
what COM ports your controlCARD is enumerating (typically done using Device Manager in Windows) and open
a serial terminal to each of with the settings 115200 Baud 8-N-1. Characters typed in one terminal should be
echoed in the other and vice versa.
A driver information (INF) file for use with Windows XP, Windows 7 and Windows 10 can be found in the
windows_drivers directory.

9.40 USB HID Mouse Device

This example application turns the evaluation board into a USB mouse supporting the Human Interface Device
class. After loading and running the example simply connect the PC to the controlCARDs microUSB port using
a USB cable, and the mouse pointer will move in a square pattern for the duration of the time it is plugged in.
UART0, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages
from this application.

9.41 USB HID Keyboard Device (usb_dev_keyboard)

This example application turns the evaluation board into a USB keyboard supporting the Human Interface
Device class. The global variable ui32Button should be modified to wake up the USB. Care should be taken to
ensure that the active window can safely receive the text; enter is not pressed at any point so no actions are
attempted by the host if a terminal window is used.

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The device implemented by this application also supports USB remote wake up allowing it to request the host
to reactivate a suspended bus. If the bus is suspended (as indicated on the application display), updating
ui32Button will request a remote wakeup assuming the host has not specifically disabled such requests.
To run the example compile the project, load to the target, and run the example. After the example is run-
ning, connect a USB cable from the PC to the microUSB port on the controlCARD.Modify ui32Button value in
the expressions window and then focus should be on the window so that we can receive keyboard input (i.e.
NotePad).

9.42 USB Generic Bulk Device (usb_dev_bulk)

This example provides a generic USB device offering simple bulk data transfer to and from the host. The
device uses a vendor-specific class ID and supports a single bulk IN endpoint and a single bulk OUT endpoint.
Data received from the host is assumed to be ASCII text and it is echoed back with the case of all alphabetic
characters swapped.
UART0, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages
from this application.
A Windows INF file for the device is provided in C2000Ware. This INF contains information required to install
the WinUSB subsystem on Windows. WinUSB is a Windows subsystem allowing user mode applications to
access the USB device without the need for a vendor-specific kernel mode driver.
A sample Windows command-line application, usb_bulk_example, illustrating how to connect to and communi-
cate with the bulk device is also provided. Project files are included to allow the examples to be built using Mi-
crosoft VisualStudio. Source code for this application can be found in directory MWare/tools/usb_bulk_example.

9.43 USB HID Mouse Host (usb_host_mouse)

This application demonstrates the handling of a USB mouse attached to the evaluation kit. Once attached, the
position of the mouse pointer and the state of the mouse buttons are output to the display.
UART0, which is connected to the FTDI virtual serial port on the controlCARD board, is configured for 115200
bits per second, and 8-N-1 mode. When a HID compliant mouse is connected to the microUSB port on the top
of the controlCARD, position and button information will be displayed to the console.

9.44 USB HID Keyboard Host (usb_host_keyboard)

This example application demonstrates how to support a USB keyboard attached to the evaluation kit board.
The display will show if a keyboard is currently connected and the current state of the Caps Lock key on the
keyboard that is connected on the bottom status area of the screen. Pressing any keys on the keyboard will
cause them to be sent out the UART0 at 115200 baud with no parity, 8 bits and 1 stop bit. Any keyboard that
supports the USB HID BIOS protocol should work with this demo application.
To run the example you should connect a HID compliant keyboard to the microUSB port on the top of the
controlCARD and open up a serial terminal with the above settings to view the characters typed on the keyboard.

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9.45 USB Mass Storage Class Host (usb_host_msc)

This example application demonstrates reading a file system from a USB mass storage class device. It makes
use of FatFs, a FAT file system driver. It provides a simple command console via the SCI for issuing commands
to view and navigate the file system on the mass storage device.
The first UART, which is connected to the FTDI virtual serial port on the controlCARD board, is configured
for 115200 bits per second, and 8-N-1 mode. When the program is started a message will be printed to the
terminal. Type “help” for command help.
After loading and running the example, open a serial terminal with the above settings to open the command
prompt. Then connect a USB MSC device to the microUSB port on the top of the controlCARD.
For additional details about FatFs, see the following site: [FatFs - Generic FAT Filesystem Module](http://elm-
chan.org/fsw/ff/00index_e.html)

9.46 USB Throughput Bulk Device Example

(usb_ex9_throughput_dev_bulk)
This example provides a generic USB device offering simple bulk data transfer to and from the host. The
device uses a vendor-specific class ID and supports a single bulk IN Endpoint and a single bulk OUT Endpoint.
Data received from the host is assumed to be ASCII text and it is echoed back with the case of all alphabetic
characters swapped.
UART0, connected to the FTDI virtual COM port and running at 115200, 8-N-1, is used to display messages
from this application.
A Windows INF file for the device is provided under the windows drivers directory. This INF contains information
required to install the WinUSB subsystem on WindowsXP, Windows 7 and Windows 10. WinUSB is a Windows
subsystem allowing user mode applications to access the USB device without the need for a vendor-specific
kernel mode driver.
A sample Windows command-line application, usb_throughput_bulk_example, illustrating how to connect to
and communicate with the bulk device is also provided. Project files are included to allow the exam-
ples to be built using Microsoft VisualStudio. Source code for this application can be found in directory
∼/utilities/tools/usb_throughput_bulk_example/Release.

9.47 USB HUB Host example

This example application demonstrates how to support a USB keyboard and USB Mouse with a USB Hub. The
display will show the connected devices on the USB hub.
To run the example you should first run the usb_config_c28 example of the C28x Side. Then run the
usb_ex9_host_hub_cm Example. Then connect a USB Hub to the microUSB port on the top of the control-
CARD and open up a serial terminal with the above settings to view the characters typed on the keyboard.
Allow the example to run with the hub connected and then connect the USB Host Mouse or Keyboard.
When a USB Mouse is connected on the Hub the position of the mouse pointer and the state of the mouse
buttons are output to the display. Similarly when a USB Keyboard is connected, any key press on the keyboard
will cause them to be sent out the UART at 115200 baud with no parity, 8 bits and 1 stop bit.

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This example is for depicting the usage of Hub.

There are some limitations in this example : 1. The Example fails to recognize the USB Hub and the device if
the Mouse/Keyboard is already connected to the USB Hub and the Hub is connected to the Micro USB of the
Control Card. 2. The same port should not be used to connect a Keyboard and mouse.

9.48 Windowed watchdog expiry with NMI handling

This program demonstrates an NMI generation to the CM4 core when the Windowed watchdog ( WWD ) expires.
A delay is provided after enabling the WWD to make the watchdog count up from 0 to 0xFF. Once 0 is reached,
an NMI is triggered. Currently on triggering an NMI, a status flag is set indicating if the NMI was handled after
the WWD expired.
External Connections

None

Watch Variables

wdstatus - Indicates if the WWD caused an NMI on expiry.

cmnmi - Indicates if the NMI was handled after the WWD expired
fail - Status if the Windowed watchdog expired generating an NMI with proper NMI handling

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 Device APIs for examples

10 Device APIs for examples

10.1 Introduction
This chapter provides information on the APIs included in device.c file

10.2 API Functions

Functions
void __error__ (const char ∗filename, uint32_t line)
void Device_bootCM (uint32_t bootmode)
void Device_bootCPU2 (uint32_t bootmode)
void Device_enableAllPeripherals (void)
void Device_enableUnbondedGPIOPullups (void)
void Device_enableUnbondedGPIOPullupsFor176Pin (void)
void Device_init (void)
void Device_initGPIO (void)
bool Device_verifyXTAL (float freq)

10.2.1 Function Documentation

10.2.1.1 __error__

Error handling function to be called when an ASSERT is violated.

Prototype:
void
__error__(const char *filename,
uint32_t line)

Parameters:
∗filename File name in which the error has occurred
line Line number within the file

Returns:
None

10.2.1.2 void Device_bootCM (uint32_t bootmode)

Function to boot CM.

Parameters:
bootmode is the mode in which CM should boot.

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Device APIs for examples

Description:
Available bootmodes :
BOOTMODE_BOOT_TO_FLASH_SECTOR0
BOOTMODE_BOOT_TO_FLASH_SECTOR4
BOOTMODE_BOOT_TO_FLASH_SECTOR8
BOOTMODE_BOOT_TO_FLASH_SECTOR13
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM
BOOTMODE_BOOT_TO_S0RAM
BOOTMODE_BOOT_TO_USEROTP
Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM, BOOT-
MODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
This function must be called after Device_init function
Returns:
None.

10.2.1.3 void Device_bootCPU2 (uint32_t bootmode)

Function to boot CPU2.

Parameters:
bootmode is the mode in which CPU2 should boot.

Available bootmodes :

BOOTMODE_BOOT_TO_FLASH_SECTOR0
BOOTMODE_BOOT_TO_FLASH_SECTOR4
BOOTMODE_BOOT_TO_FLASH_SECTOR8
BOOTMODE_BOOT_TO_FLASH_SECTOR13
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
BOOTMODE_BOOT_TO_M0RAM
BOOTMODE_BOOT_TO_USEROTP

Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM, BOOT-

MODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
This function must be called after Device_init function
Returns:
None.

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 Device APIs for examples

10.2.1.4 Device_enableAllPeripherals

Function to turn on all peripherals, enabling reads and writes to the peripherals’ registers.

Prototype:
void
Device_enableAllPeripherals(void)

Description:
Note that to reduce power, unused peripherals should be disabled.

Parameters:
None
Returns:
None

10.2.1.5 Device_enableUnbondedGPIOPullups

Function to enable pullups for the unbonded GPIOs on the 176PTP package.

Prototype:
void
Device_enableUnbondedGPIOPullups(void)
Parameters:
None
Returns:
None

10.2.1.6 void Device_enableUnbondedGPIOPullupsFor176Pin (void)

Function to enable pullups for the unbonded GPIOs on the 176PTP package: GPIOs Grp Bits 95-132 C 31 D
31:0 E 4:0 134-168 E 31:6 F 8:0.
Parameters:
None
Returns:
None

10.2.1.7 void Device_init (void)

Function to initialize the device. Primarily initializes system control to a known state by disabling the watchdog,
setting up the SYSCLKOUT frequency, and enabling the clocks to the peripherals.

Parameters:
None.
Returns:
None.

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 Device APIs for examples

10.2.1.8 void Device_initGPIO (void)

Function to disable pin locks on GPIOs.

Parameters:
None

Returns:
None

10.2.1.9 bool Device_verifyXTAL (float freq)

Function to verify the XTAL frequency.

Parameters:
freq is the XTAL frequency in MHz

Returns:
The function return true if the the actual XTAL frequency matches with the input value

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Sun Apr 7 02:08:58 IST 2024 225
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