MOSROMarrays. Consider first the 4-bit X4-bit memory array shown in Fig. 10.3.

Here,
each column consists of a pseudo-nMOS NOR gate driven by some of the row signals,
i.e., the word lines.

DD

R1

R1 R2 R3 R4 C1 C2 c3 c4
1 0 1 0 1
R2
0 1 0 1 1

1 1 0 1

R3 + 0 0 1 1 1

R4

3
C1 C2 C3 C4

Figure 10.3. Example of a 4-bit x4-bit NOR-based ROM array.

As described in the previous section, only one word line is activated (selected) at a
time by raising its voltage to Vp while all other rows are held at a low voltage level. If
an active transistor exists at the cross point of a column and the selected row, the column
voltage is pulled down to the logic low level by that transistor. Ifno active transistor exists
at the cross point, the column voltage is pulled high by the pMOS load device. Thus, a
logic "1"-bit is stored as the absence of an active transistor, while a logic*"0"-bit is stored
as the presence of an active transistor at the crosspoint. To reduce static power
consumption, the pMOS load transistors in the ROM array shown in Fig. 10.3 can also
be driven by a periodicprecharge signal, resulting ina dynamic ROM.
 Now consider the write "0" operation, assuming that a logic "1" is stored in the
SRAM cellinitially. Figure 10.27 shows the voltage levels in the CMOS SRAM cell at
the beginning of thedata-write operation. The transistors Ml and M6 are turned off, while
the transistors M2 and M5 operate in the linear mode. Thus,the internal node voltages
are V,= VpD and V,=0V before the cell access (or pass) transistors M3 and M4 are turned
On.

VDD
OV
Vop
M5 M6
M3 M4

VoD OV

M1 M2

C VDD VoD

Figure 10.27. Voltage levels in the SRAM cell at the beginning of the "write' operation.

The column voltage V, is forced to logic "0" level by the data-write circuitry; thus, 427
we may assume that V, is approximately equal to 0 V. Once the pass transistors M3 and
M4 are turned on by the row selection circuitry,we expect that the node voltage V, Semiconductor
remains below the threshold voltage of M1, since M2 and M4 are designed according to Memories
condition (10.5).Consequently, the voltage level at node (2) would not be sufficient to
turn on M1. To change the stored information, i.e., to force V, to 0V and V, to Vpn the
node voltage V,must be reduced below the threshold voltage of M2, so that M2 turns off
first. When V,= Vp the transistor M3 operates in the linear region while M5 óperates
in saturation.

(10.6)

Rearranging this condition results in:

kps2(Vpo -15V.)Vin
kn.3
W
2(Vop-15 )Vn (10.7)

,
To summarize, the transistor M2 will be forced into cut-off mode during the write
"0" operation if condition (10.7) is satisfied. This will guarantee that M1l subsequently
turns on, changing the stored information. Note that asymmetrical condition also dictates
the aspect ratios of M6 and M4.
 read select

parasitlc
storage
capacitance

bit line (write) bit line (read)

write select
(b)

word line
(readwrite select)

explicit
storage
capacitor

bit line
(data read/write)
(c)

Figure 10.36. Various configurations of the dynamic RAM cell. (a) Four-transistor DRAM
with two storage nodes. (b) Three-transistor DRAM cell with two bit lines and two word lines
One-transistor DRAM cell with one bit line and one word line.

and diffusion capacitances of the nodes indicated in the circuit diagram. Since no current
path is provided to the storage nodes for restoring the charge being lost to leakage, the
cell must be refreshed periodically. It is obvious that the four-transistor dynamic RAM Semiconduc
cell can have only a marginal area advantage over the six-transistor SRAM cell. Memor
The three-transistor DRAM cell shown in Fig. 10.36(b) was the first widely used
dynamic memory cell. It utilizes a single transistor as the storage device (where the
transistor is turned on or off depending on the charge stored on its gate capacitance), and
one transistor each for the "read" and "write" access switches. The cell has two control
and two VOlines. Its separate read and write select lines make it relatively fast, but the
four lines with their additional contacts tend to increase the cell area.
The one-transistor DRAM cell shown in Fig. 10.36(c) has become the industry
standard dynamic RAM cell in high-density DRAM arrays. With only one transistor and
one capacitor, it has the lowest component count and, hence, the smallest silicon area of
all the dynamic memory cells. The cell has one read-write control lihe (word line) and one
IO line (bit line). We have to emphasize at this point that, unlike in the other dynamic
memory cells shown in Figs. 10.36(a) and 10.36(b), the storage capacitance of the one
transistor DRAM cell is explicit. This means that aseparate capacitor must be manufac
tured for each storage cell, instead of relying on the parasitic oxide and diffusion
capacitances of the transistors for data storage. The word line of the one-transistor DRAM
cell is controlled by the row address decoder. Once the selected transistor is turned on,
the charge stored in the capacitor can be detected and/or modified through the bit line.
Before we examine the operation of the one-transistor DRAM cell, we will first
investigate the three-transistor cell shown in Fig. 10.36(b), which has avery straightfor
ward operation principle. This will help us to illuminate the basic issues involved in the
design and operation of dynamic memory cells in general.
 Figure 12.30 shows the circuit diagram of a BiCMOS NOR2 gate. Here, the base of
the bipolar pull-up transistor Q1 is being driven by two series-connected pMOS
transistors. Therefore, the pull-up device can be turned on only if both of the inputs are
logic-low.

Voc Vcc.

Q1

Vout
Foad
VB

MB2
K

Figure 12.30. Circuit diagram of the BiCMOS NOR2 gate.

The base of the bipolar pull-down transistor Q2 is driven by two parallel-connected

nMOS transistors. Therefore, the pull-down device can be turned on if either one or both
of the inputs are logic-high. Also, the base charge of the pull-up device is removed by
two minimum-size nMOS transistors connected in parallel between the base node and the
ground. Notice that only one nMOS transistor, MB2, is being used for removing the base
charge of Q2, when both inputs are logic-low.
 (UO) Circuits
13.2. ESD Protection

Electrostatic discharge is one of the most prevalent causes for chip failures in both chip
manufacturing and field operation. ESD can occur when the charges stored in machines
or the human body are discharged to the chip on contact or by static induction. Figure 13.1
shows different models for ESD testing, namely the human body model (HBM), the
machine model (MM), and the charged device model (CDM).

1 MQ 1.5 k2 1MQ
W

Vesd 100 pF Vesd. 200 pF DUT

(a) (b)

1G2 DUTY
Charging Discharging
Probe
Supply

(c)

Figure 13.1. (a) Human body model, (b) machine model, and (c) charged device model, for ESD
testing.

A human walking across synthetic carpet in 80% relative humidity can potentially
induce 1.5kV of staticvoltage stress. In the HEBM(MIL-STD-883C, Method 3015, 1988)
shown in Fig. 13.1(a), a touch of a charged person's finger is simulated by discharging
a 100-pF capacitor through a 1.5-k2 resistor. It is important that some protection
network be designed into the VO circuits of the chip so that the ESD effect can be filtered
out before its propagation to the internal logic circuit. Effective protection networks can
withstand as high as 8-kV HBM ESD stress.
In addition to human handling, contact with other machines can also cause ESD
stress. Since body resistance is absent, the stress can be more severe with higher current
levels. The schematic diagram of the machine model is shown in Fig. 13.1(b).
The third model is the charged device model shown in Fig. 13.1(c). It is intended to
model the discharge of the packaged integrated circuits. The charge can be accumulated

536 either during the chip assembly process or in the shipping tubes. The CDM ESD testers
electrically charge the device under test (DUT) and then discharge it to ground, thus
CHAPTER 13 probing the high short-duration current pulse to DUT.