teed The output of a 2-input multiplexer is connected back to one of its inputs as Soar B enn itst laos Match the function equivalence of this circuit to one of the following options. emt ! Deity Latch © haltadder X [GATE-2023-CS: 1M] Rms S=9, Q(ntl)= Q(n) Cena tp) yee eesti aon ma7) Oe) Dei#Q. Given below is the diagram of a synchronous sequential circuit ae) one J-K flip-flop and one T flip-flop with their outputs denoted as A and B respectively, with J, = (A' + B'), K, = (A+B), and T, = A. Starting from the initial state (AB = 00), the sequence of states (AB) Siem aero ie ry aa eee ee emer) ora ea) Sh OAR on Le) Cy il ee eo) —) > eT) KW Pt Ce el ee felted bo0- ol I-06 otetee) Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q, and Q, are set to 1 (before the 1st clock cycle). The outputs [GATE-2017-CS: 1M] TIPE TCH GD) Re CtLeADIC“ OCD can ri Ca va! aT ONCE) ae HT) id sins ny a i Clock a ic (a Q,Q) after the 3rd cycle are 11 and after the 4th cycle ES tit) ae Q,Q after the 3rd cycle are 11 and after the 4th cycle are 01 respectively Cc) CRON cg the 3rd cycle are 00 and after the 4th cycle are 11 respectively CD) Q,Q) afté the 3rd cycle are 01 and after the 4th cycle are 01 respectively.#Q. The propagation delay of the exclusive-OR (XOR) gate in the circuit mi Ue ite ce eM UCR yee lect cl MeOC MMe ee Memo eeceee coin to be zero. The clock (CLK) frequency provided to the circuit is 500 tr Nem ei MOM CMC Re mealies iene ion ticRe mere ts as ase with D, = 1, the minimum number of triggering clock edges after which the flip-flop outputs Q, Q,; Q), becomes 1 0 0 (Cebtcsoe etyCee) A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to UIT me Mem PMI ios teem ET iec Amer melee ime mere DM i lente om Kea com los la one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip- FIC MOV Mence ited ie) e te mae eae ok Wicca nil -meeunietme ele eames n that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK ou Both the flip-flops have non-zero propagation delays. [GATE-2015-CS: 1M] CSET SOC acne Ah RA i LTE Oe EON CNT NC OX or00100.. » —&lnty = Do= Qin) ©% 011101110. © % 011001100...aite) The above synchronous sequential circuit built using JK flip-flops is initialized Rive) 2:Q,Q0 = 000. The state sequence for this circuit for the next 3 clock cycles H [GATE-2014-CS: 1M] Bs - z , CA c “ ; a d c o a ae) fs kK & 7 ion or) ar) rh jl M4 Ch ESAT A USE Te a —— — 001, 010, 011 eo roe OX111, 110, 101 crc oe = Qn) SCT ECC Ee Re oa Tear OEChES) 100, 011, 001ite) The minimum number of D flip-flops needed to design a mod-258 counter is : am [GATE-2011-CS: 1M] oo nN ar i) ay ry iy#Q. Two T-flip flops are interconnected as shown in the figure. The — |} state of the flip flops are: A = 1, B = 1. The input x is given as 1, 0, 1 in the next three clock cycles. The decimal equivalent of (ABy), with A being the MSB and y being the LSB, after the 3" clock cycle is ___7 CTO RPE SCR SGD) Wee ECT CR RECT) ie 1) Hl UNCED aa ACE TIED) tea Py . ea OD)[McQ] Ch, LOS omentm Ce ehiUiel Matval imi Ve Mult Mele om Page eile ieee eRe Meseciiy type of counter configuration. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR Poneto ECC mee [GATE-2011-CS: 1M] CCE aay S00) CEM (2. da CLD ic a o Se Aa eat a ae are a 5 a . i Ce Be[McQ] Ch, Oops omentm Ce oUt Metvar imi Ve hui melet om Page miles ieee Be Meseciiy type of counter configuration. If at some instance prior to the occurrence of the alle aes ORM CL MRO ee aceon ARE areca ee value of PQR after the clock edge? [GATE-2011-CS: 1M] aa Ca © 001 © 010 O outee) Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as SoBe te omO OM CBC Reme lee aiietimcmeteratiam memoria On om Q2 and Q3 have values 0, 1 and 1, respectively. Which one of the given values of (Q1, Q2, Q3) can NEVER be obtained with this digital circuit? Cet eg [GATE-2023-CS: 2M] Teil (0, 0, 1) COT nO) CAS a TOTO NC) wit ( : SICH) mane tS sa one \ mee ie ec re ary s(n) #5 ca if eats ce D)Lockout (Caro Shag WA Ces (otl)— * eeeas er ea aes ; meme ast ¢ oe (-- oe |. ritee) Consider a 3-bit counter, designed using T flip-flops, as shown below. Assuming the initial state of the counter given by PQR as 000. What are the next Por ced 011,101,000 RSS St SRS Et 001,010,000 ia Vise eee TTT#Q. For the synchronous sequential circuit shown below, the output Z mi) PZaveR oomere nec mae te (eli) OT Tk ON ete OLY The minimum number of clock cycles after which the output z would again become zero isOo Do[NAT] The minimum number of JK flip-flops required to construct a synchronous eet tet) A count sequence (0,0,1,1,2,2,3,3,0,0....jis. [GATE-2021-CS: 2M] a 10 el ee oa 9 . pa aoa d i 00 oa | (eke) roma oo O| (anne) | ao lo| ae Ca ve ees ' ror] a iCe No beaa Sied?ol| ad CRs ale SY ees = 9 ry anal CT rT cama} xa ey nT anor Seay cas aT eo- 3a a oop R2Q, 2 a ea aeraro 1B Which one of the following statements is true about the digital circu QD Stem mer mittee It can be used for dividing the input frequency by 3. Itcan be used for dividing input frequency by 5. sTaeT eM IO CO MeUC TMU eet eect ae It cannot be reliably used as a frequency divider due to disjoint internal cycles.tee) The next state table of a 2-bit saturating up-counter is given below. The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T, and Ty are a ° SLC a eer Oy ° SEO Ory tc} SERCO a0 [BAO GATE-2017-CS: 1M] (Fae ee 0/0 ) a ame a 0 1| 0 ss Bf jee sg Eeite) Consider a 4-bit Johnson counter an initial value of 0000. The counting sequence of this counter is - [GATE-2015-CS: 1M] lee ooh ileal ek-y- eee CONN ieaneysy aon © 013,7,15,14,12,8,0 © 01355,7,9,11,13,15,0 © 0246,8,10,12,14,0 ro Aa STEEREDite) Let k = 2". A circuit is built by giving the output of an n-bit binary counter as input to an n-to- 2" bit decoder. This circuit is equivalent to a ne CBD) Q2. QQ. n Cs Moora ena ce a Co) CB ) ea Sets Reel ae ae OK ring counter. Z k-bit Johnson counter. CV pe Moe TT] nn el ° [on ee! ee ee a bier ee Cee Te mee nr) 4. sd 0 . a By aie Rea cas#Q. A three-bit pseudo random number generator is shown. Initially nc value of output Y = Y, Y, Yo is set to 111. The value of output Y after three clock cycles is 000 > Dp, CCE CD) Ro(nt) =& ln) t t 1 xo Ss co = By(nyBa(n) Sh ae | one oy oaro The circuit shown consists of J-K flip-flops, each with an active iow asynchronous reset (Ry input). The counter corresponding to this circuit is EBC mune ma Reeth a Eee Onmo nem acme ios Eten enema meet ics a modulo-6 binary up counter#Q. For the circuit shown, the clock frequency is f, and the duty cycle @ 25%, For the signal at the Q output of the Flip-Flop, " aad Eos Flip-Flop nak frequency is f,/4 and duty cycle is 50% frequency is f,/4 and duty cycle is 25% ieee MCS PA Rel ame cee LL) frequency is f) and duty cycle is 25%#Q. In the following sequential circuit, the initial state (before the rsh clock pulse) of the circuit is Q; Qy = 00. The state (Q, Q,), immediately after the 333 clock pulse is ad 00 2|#Q. The figure shows a digital circuit constructed using negative cae triggered J-K a flops. Assume a starting state of Q, Q; Q, = 000 will number of cycles of the clock CLK repeat after Qo(ntt)= Qa(n) SEE eae ae — 7 CONC Es Att aL Sa Qalt-ey) CTICD) CCS aly Q@\(v) EST EaCOST | le Ae i ons i nn) ao cn) ae Ooo sh | a Ie