MODULE 2
• SEM: IV
• Course: Computer Organization and Architecture.
• Course Code: 22CS2405
• Faculty: Dr. Savitha Hiremath
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Contents:
• Logical and Arithmetic: Flags and their Use, Compare
instructions, Data Processing Instructions
• Loops and Branches: Branching, Looping, Conditional
Execution, Straight
Line Coding • Subroutines and Stacks:
Stack, Subroutines, Passing parameters to subroutines, The
ARM APCS.
• (Text Book-1 “William Hohl, “ARM Assembly Language”,
2nd Edition, CRC Press, 2009”: 6.1 to 6.4; 7.1 to 7.4; 8.2 to
8.6; 13.1 to 13.4
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Data processing Instructions
• They are move, arithmetic, logical, comparison
and multiply instructions.
▪Data processing instructions are the one which
modify data values.
Data processing Instructions
General rules:
– All operands are 32-bit, coming
from registers or literals.(Assembly
language source code can contain numeric, string,
Boolean, and single character literals)
– The result, if any, is 32-bit and
placed in a register (with the
exception for long multiply which produces a
64- bit result)
– 3-address format
• Typical ARM data processing instructon
ADD R0, R1, R2 ; R0:= R1+R2
- Arithmetic operations
• ADD R0, R1, R2
• ADC R0, R1, R2 ; R0=R1+R2+C
• SUB R0, R1,R2 ; R0=R1-R2
• SBC R0,R1,R2 ; R0= R1-R2+C-1
• RSB R0, R1, R2 ; R0= R2-R1, Reverse
Subtraction • RSC R0, R1, R2 ; R0= R2-
R1+C-1
- Bit wise logical operations
• AND R0, R1, R2 ; R0= R1 AND R2
• ORR R0, R1, R2 ; R0= R1 OR R2
• EOR R0, R1, R2 ; R0= R1 XOR R2
• BIC R0, R1, R2 ; R0= R1 AND NOT R2 ,
Bit clear
• BIC: Every 1 in the second operand clears the
corresponding bit in the first operand.
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- Register movement operations
MOV R0, R1 ; then R0:=R1
MNV R0, R1 ; then R0:- NOT R1
Immediate operands
ADD R3, R3, #4
AND R3, R3, #&E4
Comparison
• These instructions do not generate a
result, but set condition code bits (N, Z, C,
V) in CPSR. Often, a branch operation
follows to change the program flow.
Comparison compare
• CMP R1, R2 @ set cc on R1-R2
compare negated
• CMN R1, R2 @ set cc on
R1+R2 bit test
• TST R1, R2 @ set cc on R1
and R2 test equal
• TEQ R1, R2 @ set cc on R1 xor R2
Comparison
In the above example,
Z flag is affected
• TST R1, R2 @ set cc on R1
and R2 TST R3,#0X10
• TEQ R1, R2 @ set cc on R1
xor R2 TEQ R3,#0
13
Conditional execution
• Almost all ARM instructions have a condition field which
allows it to be executed conditionally.
movcs R0, R1
Shifted register operands
C
Logical shift left
register
0
MOV R0, R2, LSL #2 @ R0:=R2<<2
@ R2 unchanged
Example: 0…0 0011 0000
Before R2=0x00000030
After R0=0x000000C0
R2=0x00000030
Working
0000 0000 0000 0000 0000 0000
0011 0000 0000 0000 0000
0000 0000 0000 1100 0000
Logical shift right 0
register C
MOV R0, R2, LSR #2 @ R0:=R2>>2
@ R2 unchanged Example:
0…0 0011 0000
Before R2=0x00000030
After R0=0x0000000C
R2=0x00000030
Arithmetic shift right
MSB register C
MOV R0, R2, ASR #2 @ R0:=R2>>2
@ R2 unchanged
Example: 1010 0…0 0011 0000
Before R2=0xA0000030
After R0=0xE800000C
R2=0xA0000030
Working:
1010 0000 0000 0000 0000
0000 0011 0000 1101 0000
0000 0000 0000 0000 0001
1000 1110 1000 0000 0000
0000 0000 0000 1100
Rotate right register
MOV R0, R2, ROR #2 @
R0:=R2 rotate @ R2
unchanged Example: 0…0
0011 0001
Before R2=0x00000031
After R0=0x4000000C
R2=0x00000031
Rotate right extended
C register C
MOV R0, R2, RRX @ R0:=R2 rotate
@ R2 unchanged
Example: 0…0 0011 0001
Before R2=0x00000031, C=1
After R0=0x80000018, C=1
R2=0x00000031
Working
0000 0000 0000 0000 0000 0000
0011 0001 1000 0000 0000 0000
0000 0000 0001 1000 c=1
Shifted register operands
Shifted register operands
• It is possible to use a register to specify
the number of bits to be shifted;
• @ array index calculation
ADD R0, R1, R2, LSL R3
For your Reference
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Shifted register operands
For your Reference 8 4 2 1 Value
0 0 0 0 0
0 0 0 1 1 1 0 1 1 B
0 0 1 0 2 1 1 0 0 C
0 0 1 1 3 1 1 0 1 D
0 1 0 0 4 1 1 1 0 E
0 1 0 1 5 1 1 1 1 F
0 1 1 0 6
0 1 1 1 7
8 4 2 1 Value
1 0 0 0 8
1 0 0 1 9
1 0 1 0 A
F E 4 6 1 0 A C
1111 1110 0100 0110 0001 0000 1 010 1100
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Multiplication
• MUL R0, R1, R2 @ R0 = (R1xR2)[31:0]
• Features:
• Second operand can’t be immediate
• The result register must be different from the
first operand • Cycles depends on core type
Multiplication
• MUL R0, R1, R2 @ R0 = (R1xR2)[31:0]
• Features:
• Second operand can’t be immediate
• The result register must be different
from the first operand
Multiplication
• Multiply-accumulate (2D array indexing)
MLA R4, R3, R2, R1 @ R4 =
R3xR2+R1
Multiplication
Multiplication
Multiplication
Multiplication
00000001 EOOOOOO4
3.2 Data transfer instructions
• Move data between ARM
registers and memory • Three basic
forms
• Single register load/store (LDR, STR)
• Multiple register load/store
Ex. LDMIA R1, {R0, R2, R5}
• Single register swap
Ex. SWP R0, R1,[R2] ; R0:=[R2]
[R2]:= R1
• Single register
swap
Ex. SWP R0,
R1,[R2] ;
R0:=[R2]
[R2]:= R1
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Swap instruction
• Swap between memory and register.
Single register load/store
• Data transfer instructions are all based on
register indirect addressing mode.
LDR R0, [R1] @ R0 := mem32[R1]
STR R0, [R1] @ mem32[R1] := R0
LDR, LDRH, LDRB for 32, 16, 8 bits
STR, STRH, STRB for 32, 16, 8 bits
Addressing modes • Pre-
index addressing (LDR R0, [R1, #4])
without a writeback
• Auto-indexing addressing (LDR R0,
[R1, #4]!) Pre-index with writeback
calculation before accessing with a writeback
• Post-index addressing (LDR R0, [R1], #4)
calculation after accessing with a writeback
Pre-index addressing
LDR R0, [R1, #4] @
R0=mem[R1+4] @ R1
unchanged
LDR R0, [R1, ]
R1 +
R0
Auto-indexing addressing
LDR R0, [R1, #4]! @
R0=mem[R1+4] @ R1=R1+4
LDR R0, [R1, ]!
R1 +
R0
Post-index addressing
LDR R0, [R1], #4 @
R0=mem[R1] @ R1=R1+4
LDR R0,[R1],
R1 R0 +
Comparisons
• Pre-indexed addressing
LDR R0, [R1, R2] @
R0=mem[R1+R2] @ R1
unchanged • Auto-indexing
addressing
LDR R0, [R1, R2]! @
R0=mem[R1+R2] @
R1=R1+R2 • Post-indexed
addressing
LDR R0, [R1], R2 @
R0=mem[R1] @
R1=R1+R2
Example:
Answer?? Contents of
Register after Execution of Instruction. Post ?
Example
Example
Example
Load an address into a register table DCD 10
LDR r0,=table
LDR r1,[r0]
48
LDR R1, =table
Application of LDR loop: LDR R0, [R1], #4
LDR R1, =table @ operations on R0
loop: LDR R0, [R1] ADD R1, …
R1, #4
@ operations on R0
… table R1
Multiple register load/store
• Transfer a block of data more
efficiently.
LDMIA R1, {R0, R2, R5} @ R0 =
mem[R1
] @ R2
=
mem[r1
+4]
@ R5 = mem[r1+8]
Multiple load/store register
LDM load multiple
registers STM store
multiple registers
suffix meaning
IA increase after
IB increase before
DA decrease after
DB decrease before
R0
Multiple load/store
register R1: 10
R2: 20
LDMIA R0, {R1,R2,R3} R3: 30
or R0: 0x10
LDMIA R0, {R1-R3}
addr data 0x010 10 0x014 20 R0
0x018 30 0x01C 40 0x020 50
0x024 60 R1: 10
R2: 20
Multiple load/store R3: 30
R0: 0x01C
register LDMIA R0!,
{R1,R2,R3}
addr data 0x010 10 0x014 20
0x018 30 0x01C 40 0x020 50
0x024 60
R1: 20
Multiple load/store R2: 30
R3: 40
register LDMIB R0!, R0: 0x01C
{R1,R2,R3}
addr data 0x010 10 0x014 20
0x018 30 0x01C 40 0x020 50
0x024 60
R0 Multiple load/store
R2: 50
register LDMDA R0!,
R3: 60
{R1,R2,R3}
addr data 0x010 10 0x014 20
R1: 40
0x018 30 0x01C 40 0x020 50
R0: 0x018 0x024 60
R0
R1: 30
Multiple load/store R2: 40
R3: 50
register LDMDB R0!,
{R1,R2,R3}
addr data 0x010 10 0x014 20
0x018 30 0x01C 40 0x020 50
R0: 0x018 0x024 60
R0
Example
Example
LDMIA
r0!, {r1-r3}
Example
LDMIB r0!, {r1-r3}
What are the advantages of
using multiple load/store
instructions compared to
single load/store
instructions?
LDR R2,[R4] @ R2 = mem[R4]
LDMIA R1, {R0, R2, R5} @ R0 = mem[R1]
@ R2 = mem[r1+4]
@ R5 = mem[r1+8]
Conditional execution Instructions
CMP R0, #5
BEQ bypass @ if (R0!=5) {
ADD R1, R1, R0 @ R1=R1+R0-R2
SUB R1, R1, R2 @ }
bypass: …
smaller and faster
CMP R0, #5
ADDNE R1, R1, R0
SUBNE R1, R1, R2
Rule of thumb: if the conditional sequence
is three instructions or less, it is better to
use conditional execution than a branch.
Conditional execution
if ((R0==R1) && (R2==R3)) R4++
CMP R0, R1
BNE skip
CMP R2, R3
BNE skip
ADD R4, R4, #1
skip: … END
CMP R0, R1
CMPEQ R2, R3
ADDEQ R4, R4, #1
Control Flow instructions
• Determine the instruction to be
executed next
• Branching can happen depending
on the some conditions.
Flow control instructions
• Branch instruction
B label
…
label: …
• Conditional branches
MOV R0, #0
loop: …
ADD R0, R0, #1
CMP R0, #10
BNE loop
END
Branches
Branch and link • BL
instruction save the return address to R14 (lr)
BL sub @ call sub
CMP R1, #5 @ return to
here MOVEQ R1, #0
…
sub: … @ sub entry point …
MOV PC, LR @ return
Working of BL instruction
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• Stack
- Last In First Out store
- Stack grows up and down the memory
- grows up when Data is added
- Goes down as data is removed
- Stack pointer holds the Address of the current
top the stack
Arm supports 4 forms of STACK
- Full ascending (FA) – SP points to highest address
containing valid data - Empty ascending (EA) –SP points to
the first empty location above stack - Full Descending (FD)-
SP points to lowest address containing valid data - Empty
descending (ED)- SP points to the first empty location below
the stack
LDMFD R13!, {R2-R9}
STMFD R13!, {R2-R9}
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Example
Application
mode POP =LDM PUSH =STM
LDMFA LDMDA STMFA
LDMFD LDMIA STMFD
LDMEA LDMDB STMEA
Full ascending (FA) STMIB Full
descending (FD) STMDB Empty
ascending (EA) STMIA Empty
descending (ED) LDMED LDMIB STMED
STMDA
Branch and link
BL sub1 @ call sub1
…
use stack to save/restore the return address and
registers
sub1:STMFD R13!, {R0-R2,R14}
BL sub2
…
LDMFD R13!, {R0-R2,PC}
sub2:…
…
MOV PC, LR
Sample Programs
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Thank you
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