INTERRUPT
Mohamed Abd El Baset
Contents
• Volatile keyword.
• Interrupt.
• Interrupt unit.
• Context switching.
• Vector table.
• Interrupt timing.
• Interrupt nesting.
• Interrupt in AVR.
• Exceptions.
• Interrupt in ARM.
• Tail chain , Late arriving
Volatile (keyword)
• Volatile tells the compiler that the value of the variable may change at
any time " without any action being taken by the code the compiler
finds nearby“.
• So it will prevent compiler from optimize the code related to the
variable ,and force it to load/store variable every time it is used .
• The compiler without volatile might load value from ram to register
and use it several time before restore it to reduce memory accessing
as a type of optimization "to increase the execution time ".
So we always use volatile with:
• Memory-mapped peripheral registers.
• Global variables modified by an interrupt service routine.
• Global variables accessed by multiple tasks within a multi-threaded
application.
Volatile (keyword)
• We can make parameter const and volatile like SREG.
• It is volatile because hardware change it.
• It is const because the program should not change it.
• We can make const pointer to volatile variable “ (volatile unsigned char
*const p)”.
• We can make a volatile pointer if its value change in interrupt or other
task “ int * volatile p “.
What is interrupt?
• In systems programming, an interrupt is a signal comes
from out side the processor indicating an event that needs
immediate attention.
The source of this signal could be a peripheral device inside the micro
controller like (Timer, ADC, UART) so it called internal.
The source could be a device from out side the microcontroller like
(button, sensor, signal from other MCU ) so it called external.
We can trigger the interrupt source by software ,and a context switch
to an interrupt handler happed so it called software interrupt.
Interrupt unit
What happens when an interrupt occurs?
• The microcontroller CPU completes the execution of the current
instruction.
• Stores the address of the next instruction that should have been
executed (the contents of the PC)in stack.
• Microcontroller CPU jump to Interrupt Vector Table to get the ISR
address of the triggered interrupt.
• The interrupt vector of the triggered interrupt (ISR start address of this
interrupt) is then loaded in the PC.
• Stores(save) all the CPU data registers and SREG “pushed to the
stack”.
• CPU starts execution the code in ISR until reaches the end of it .
• All the CPU registers and SREG are restored “popped from the stack”.
• The address that was stored on the stack is reloaded in the PC.
• The CPU then continue executing the main program.
Interrupt Vector Table
Interrupt timing
• Interrupt latency:
Is the time between the generation of an interrupt signal by a
device and the start of the context switching.
• Interrupt Response:
Is the time between the generation of an interrupt signal ,and the
execute of the code inside ISR
“Interrupt latency + Time to save the CPU context”.
• Interrupt Recovery:
Is defined as the time required for the processor to return to
the interrupted code.
Interrupt timing
Interrupt latency
• When an interrupt occur, the service of the interrupt by
executing the ISR may not start immediately by context
switching because of :
• Disable the global interrupt to execute a critical section.
• More code in interrupt handler will increase the latency of
other interrupt if the nested is disabled(not supported by
hardware), or the other interrupt is less in priority.
Interrupt Nesting:
• Ability to leave the current interrupt and serve
another interrupt.
• If the interrupt nesting is supported ,hardware mechanism is needed
to check the priority of the coming interrupt.
• If the priority of the new interrupt is higher than the one which served
by the processor a context switching is happening and the processor
start serve the higher on.
• If the new interrupt is in same priority or lower, the signal is saved
,and the processor will start serve the new interrupt after finished the
current one .
• If more than one interrupt came but all lower in priority
all the signal are saved and the processor will start serve them in order
of priority .
Interrupt Types
• Maskable Interrupts
Maskable interrupt can be disabled and enabled by using global
interrupt enable in processor status register or the corresponds flag.
• External interrupt from external pin.
• Internal interrupt from peripheral.
• Non-Maskable Interrupts
Non-maskable interrupts can not be disabled and are always enabled.
Usually it’s external interrupt like reset interrupt.
Interrupt Types
• Classification of Interrupts According to the Temporal
Relationship with System Clock:
• Synchronous Interrupt: The source of interrupt is in phase to the
system clock is called synchronous interrupt. In other words interrupts
which are dependent on the system clock. Example: timer service that
uses the system clock.
• Asynchronous Interrupts: If the interrupts are independent or not in
phase to the system clock is called asynchronous interrupt.
Interrupt in AVR
• When an interrupt occurs, the Global Interrupt Enable I-bit is cleared
by hardware ( and all interrupts are disabled).
• The user software can write logic one to the I-bit to enable nested
interrupts but in this case All enabled interrupts can then interrupt the
current interrupt routine (no mechanism to handle priority). .
• The I-bit is automatically set when a Return from Interrupt instruction
– RETI – is executed.
• When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending
interrupt is served.
Interrupt in AVR
• The interrupt latency for all the enabled AVR interrupts is four clock
cycles minimum.
• After four clock cycles, the program vector address for the actual
interrupt handling routine is executed.
• During this 4-clock cycle period, the Program Counter is pushed onto
the Stack.
• The vector is normally a jump to the interrupt routine, and this jump
takes three clock cycles.
• A return from an interrupt handling routine takes four clock cycles.
• During these 4-clock cycles, the Program Counter (two bytes) is
popped back from the Stack, the Stack Pointer is incremented by two,
and the I-bit in SREG is set.
Exceptions
• Exceptions are events that disrupt the normal execution flow of the
program. When an exception occurs the processor handles it by
usually executing dedicated piece of code called exception handler.
Each type of exception can have its own exception handler.
• In some literature sources exceptions and interrupts are analyzed
as two different things. Exceptions being generated internally by the
microprocessors itself and interrupts being generated by external
source . For the sake of simplifying the categorization we are looking
at the interrupts as a specific type of exception.
Exceptions types
• Interrupt requests (IRQ)
• Faults
These events are detected by the processor and their source is
an abnormal event. For example:
• Divide By Zero
• Undefined instruction that the processor cannot decode. Potential
reasons are
a) Use of instructions not supported by the microprocessor
b) Corrupted memory contents
• Segmentation faults.
• Memory fault “dereference an address outside memory
range”(could be use to detect stack overflow).
Exceptions types
• Supervisor call (SVC)
• SVCs are instructions that cause an exception. They are
usually used to request an access to system resources
like (hardware peripheral) from an operating system.
INTERRUPT IN ARM
• The processor and the Nested Vectored Interrupt
Controller (NVIC) prioritize and handle all exceptions.
• When handling exceptions:
• All exceptions are handled in Handler mode.
• Processor state is automatically stored (by hardware) to
the stack on an exception, and automatically restored from
the stack at the end of the Interrupt Service Routine (ISR).
• • The vector is fetched in parallel to the state saving,
enabling efficient interrupt entry (Harvard Architecture).
INTERRUPT IN ARM
• The processor supports tail-chaining that enables back-
to-back interrupts without the overhead of state saving
and restoration.
• You configure the number of interrupts, and bits of
interrupt priority, during implementation.
• Software can choose only to enable a subset of the
configured number of interrupts, and can choose how
many bits of the configured priorities to use.
Tail-chaining
• is a mechanism used by the processor to speed up interrupt
servicing.
• On completion of an ISR, if there is a pending interrupt of
higher priority than the ISR or thread that is being returned
to, the stack pop is skipped and control is transferred to the
new ISR.
Late-arriving
• A mechanism used by the processor to speed up pre-
emption. If a higher priority interrupt arrives during state
saving for a previous pre-emption, the processor switches
to handling the higher priority interrupt instead and
initiates the vector fetch for that interrupt.
• The state saving is not effected by late arrival because
the state saved is the same for both interrupts, and the
state saving continues uninterrupted.
• Late arriving interrupts are managed until the first
instruction of the ISR enters the execute stage of the
processor pipeline.
• On return, the normal tail-chaining rules apply.
ARM-CORTEX VECTOR TABLE
ARM-CORTEX VECTOR TABLE
