INTRODUCTION

TO
NETWORK SYNCHRONIZATION
Synchronization of Digital Networks

BN 3035 / 89.02
 Network synchronization

An effective network synchronization

concept increases the availability and
reliability of the transmission network

Poorly synchronized networks cause

disturbances in transmission and lead to
customer complaints
 Discussion Area

• What a Synchronous Network ?

• Why do networks need to be synchronized ?
• How to implement a synchronization network
• Synchronisation standards
• Performance parameters
• Planning of Synchronization
• Issues
• Challenges
• Conclusion
 What is synchronous network?

• When can we call our SDH network

SYNCHRONISED
– All ADMs are receiving Clock from some SSU in the
vicinity ?
• SSUs ARE NOT CLOCK SOURCES IN
THEMSELVES
– THEY JUST CLEAN A CLOCK SIGNAL COMING FROM A
MASTER SOURCE
• A synchronous network is one where the clock
used by any ADM can be traced back to the PRC
 Goals of a synchronization
system
Maintain Network Frequency
within the performance PERFORMANCE
boundary LIMIT

Know when the network is

drifting beyond the boundary

Isolate problems BEFORE they

degrade network performance
PRIMARY
REFERENCE
CLOCK
 WHY NETWORK SYNCHRONIZATION?

• To transport bits across a network or multiple

networks, as well as national boundaries,
without losing bits.
• Technical
• Minimize data loss
• Increase speed
– Political
• Comply with International standards
– Overall
• Deliver superior quality telecom services
 What is Synchronisation
• Synchronization : keeping all digital equipment in a
communications network operating at the same
average rate.
• Synchronization must exist at three levels:
– bit, time slot, and frame.
• Bit synchronization : transmit and receive ends of
the connection operate at the same clock rate, so
that bits are not misread.
• Time slot synchronization aligns the transmitter
and receiver so that time slots can be identified for
retrieval of data.
• Frame synchronization refers to the need of the
transmitter and receiver to be phase aligned so that
the beginning of a frame can be identified.
 What is Synchronisation
• A network clock located at the source node controls
the rate at which the bits, frames, and time slots are
transmitted from the node.
• A second network clock is located at the receiving
node, controlling the rate that the information is being
read.
• The objective of network timing is to keep the source
and receive clocks in step, so that the receiving node
can properly interpret the digital signal.
• Differences in timing at nodes within a network will
causethe receiving node to
– either drop or
– reread information sent to it.
• This is referred to as a SLIP.
 What is Synchronisation
• In E1 communications, buffers are used to control
slips
• Data is written into buffer and is read from the buffer
at different rates

• Receive equipment will drop an entire frame

• This is called Controlled Slip
 What is Synchronisation
• The basic objective of network
synchronization is to limit the
occurrence of controlled slips.
• Slips can occur for two basic reasons.
– the lack of frequency synchronization
among the clocks
– phase movement (such as jitter and
wander) between the source and receiver
clock.
 How does slip affect communications
signals ?

• Voice Crackling
• Fax Incorrectly transmitted pages,
missing characters
• Data Low throughput (10ms – 1.5s)
• Video Picture freezes briefly
• Encrypted Re-transmission of
data encryption code
• Wireless Dropped calls and delayed
handover
 Synchronization of SDH Network
Elements
• Slips are not the only impairments due
to poor synchronisation
• Poor synchronization can lead to excessive
jitter and misframes in SDH
• In private networks, the poor synchronization
of customer premises equipment (CPE) can
cause error bursts in the network.
– These excessive errors cannot be
distinguished from normal errors of
transmission
Synchronization of SDH Network Elements

SDH Network Element

Internal 2 Mbit/s
155 Mbit/s Oscillator
Data Signal Data Signal
± 4.6 ppm

Osc.

Synchronous
SDH Signal

2 048 kHz
Central Clock
 The Difference with SDH
• Unlike PDH, the SDH systems introduce
unusually higher jitter on the PCM tributaries
• The PCMs working on SDH are unsuitable for
sending clock signals from one point to
another
• But this was the convention in the past for
synchronising our TAXs and other systems
• Our synchronisation plan has to be reviewed
 What is a Synchronous Network
• A Network in which all nodes (Switch and
Transmission) synchronize to one reference
clock (PRC)
• In other words
– The clock used by any elements can be traced
back to the reference master clock
• A network can have one or more PRCs
• The clock signal of these PRCs are to be
distributed all over the network
– Redundancy against failures
• The infrastructure used for this clock
distribution is called synchronization network.
network
 Synchronisation Planning
Concept
• Synchronisation Plan is basically determination of
the distribution of Synchronisation in the network.
It involves
• Selection of the clocks and references
• Follow up of Rules and procedures in the
distribution
• To maintain the quality of the clock signal
 Overview of synchronization clocks

Primary
reference PRC
clock 10-11

Synchronization

Accuracy
supply SSU 10-9 (TNC)
unit 10-8 (LNC)

SDH
equipment SEC
clock 4.6 x 10-6

PDH
slave PDH
clock
 Which Recommendations define
Synchronization Networks

ITU-T ANSI / Bellcore ETSI

Definitions G.810 T1.101 / GR-253 ETS 300 462-1

Network G.825 T1.105 / GR-253 ETS 300 462-3
Primary Reference Clocks G.811 T1.101 ETS 300 462-6
Synchron. Supply Clocks (ST2) G.812 T1.101 ETS 300 462-4
Equipment Clocks (ST3) G.813 (G.81s) GR-253 ETS 300 462-5
 The influence of clock quality

User A Digital network User B

DE DE

Clock source A Clock source B

Clock A Clock B 1 slip per Slips per day

+ 1 x 10-11 -1 x 10-11 72 days 0

+ 1 x 10-10 - 1 x 10-10 7 days 0
+ 1 x 10-9 - 1 x 10-9 17 hours 1
+ 1 x 10-8 - 1 x 10-8 2 hours 14
+ 1 x 10-7 - 1 x 10-7 10 minutes 138
+ 1 x 10-6 - 1 x 10-6 62 seconds 1328
+ 1 x 10-5 - 1 x 10-5 6 seconds 13824
 Synchronisation Methods
• Plesiosynchronous
• Master-slave (Hierarchical Source-
Receiver)
• Mutual Synchronisation
• Distributive method

BSNL adopted Master-slave/ centralized

/(Hierarchical Source-Receiver)
architecture.
 Hierarchical clock distribution
"Inter-node"

G.811
Master / slave principle PRC Primary reference
clock

Slave clock
G.812 G.812
SSU (transit node
TNC TNC
clock)

Slave clock
G.812
LNC
(local node
G.812 clock)
SSU G.812
LNC G.812
LNC LNC
SSU: Synchronous supply unit
 Synchronisation Supply Unit
• Synchronisation Supply Unit (SSU) is an
equipment, which minimizes the excess
accumulated jitter and wander in the network due
to cascading of SDH NE. can accept no. of inputs
and can select on priority.
• Two types – Transit and Local
- Transit confirming to ITU-T Rec. G.812
- Local node confirming to ITU-T Rec. G.813
SSU provides multiple 2Mbps/2MHz signals for
distribution.
 Synchronization reference model
SDH / SONET (acc. ITU-T)

G.811 G.812 G.812

PRC TNC SSU TNC SSU

G.813 G.813 G.813

SEC SEC SEC

Limits:

Max. 10 x G.812 TNC

Max. 60 x G.813 SEC,
no more than
20 between two TNCs
 PRC National layer

All SSU are with

SSU
G.812 Clock

SSU SSU regional

SSU SSU SSU SSU

Local

SSU SSu SSU SSU

Centralised Synchronisation Network Architecture

HIERARCHICAL SYNCHRONISATION
DISTRIBUTION LAYERS
PRC Layer

PRC

SSU Layer
SSU SSU
SSU SSU

SEC Layer
 Critical points in a synchronous
network

• Interfaces between the networks of

different providers
• International network gateways
• Non-traceable clocks
• Clock distribution (clock looping)
• Jitter, wander, propagation time, clock
stability
 Timing Loops in SDH network
• when a clock uses a timing reference that is
traceable to itself, then it is known as Timing loop.
• When SDH ring consisting of no. of elements is
fed by a SSU and follows a defined path gets a
break then Timing loop may be formed.
• The performance is worse in a timing loop than
free running/holdover mode.
• No combination of primary and/or secondary
references should result in timing loop.
 Synchronisation Performance
Parameters
• Slip : A slip is a bit error occurring as a result of
difference between the incoming signal clock rate
and node clock rate.
• Jitter: refers to phase variations in a digital signal
and is described in terms of its amplitude and its
frequency. This effects in short term stability
• Wander : If the jitter frequency is below 10 Hz
then it is known as Wander. This effects in long
term stability
 How does jitter influence a digital
signal ?
0 1 2 3 4 5 6 7 8 9 ...

Time Line

1 UI

Bit Sequence 0 1 0 1 1 0 1 0 0 1 1 0

Ideal Signal (NRZ)

Actual Signal
(with Jitter
and Wander)

Sampling at uniform
intervals
 Jitter sources

• Noise
• Pattern of the transmission signal
• Stuffing with plesiochronous multiplexers
• Delays when the data is read
• Mapping in synchronous systems
• Pointer operations in synchronous systems
• Side-to-side crosstalk
• Signal reflection
 Pointer Adjustments
1 9 270

RSOH
H1 H2 H3 Start of VC-4
Actual pointer
MSOH

125µs
RSOH
Pointer with
inverted D bits H1 H2 H3

MSOH

250µs
RSOH
H1 H2 negative justification byte (data)

MSOH

375µs
New pointer RSOH
H1 H2 H3

MSOH
500µs
 Wander

Since the introduction of synchronous networks,

wander has become a familiar concept. It occurs
whenever network elements are required to function
synchronously with one another, in order to prevent
disturbances in transmission or at least to restrict
them to a tolerable minimum.
 The differences between
wander and jitter
Amplitude / dB

10 Hz
Wander range Jitter range

uHz MHz
Frequency
 Wander sources

• Sporadic pointer operations in synchronous

networks
• Different clock reference sources
(quasi-synchronous operation)
– National gateways
– Network gateways between different providers
• Propagation time variations in connection with
clock distribution
• Low-frequency noise
 Wander characteristics II
TIE: Represents the time deviation in a clock signal relative to a
reference clock during one observation interval

MTIE: Maximum time interval error in a clock signal compared with a

reference signal within a specified observation time

TDEV: Measure of the time variation in a digital signal versus the

integration time.
 Influence of wander

• Wander accumulates in synchronous

networks and can therefore reach very
high levels
• Buffers in network nodes and digital
exchanges may overflow
– Bit slips generated in network nodes
– Frame slips generated in digital exchanges
• Mutilation of color values in TV signals
 Synchronization Performance
• Synchronization performance depends on three factors
– Accuracy of master clock
– Performance of facilities distributing the reference
– Performance of receiver clock
• PRC performance : slip rate is usually negligible. It ranges
from one slip every five year to three slips per year
• Facility performance : jitter and wander
– Jitter on PDH < 600ns
– Jitter on Satellite 1.8ms
– Wander on SDH >10µs
 Synchronization Performance
• Receiver clock performance
– Ideal operation
– Stressed operation
– Hold over operation
 Planning of Synchronization
• Maintain Hierarchy
• Avoid Timing Loops
• BITS/SSU Concept
• Use Best Facility to Transport Timing Reference
• Cascading of timing reference through a network
should be minimized
 Planning Issues

• Not all Planning Concepts can be Simultaneously Adhered

To in Private Networks
– Lack of external timing references and long chains
– Use of poor quality clocks
 CONCLUSION

• Synchronization has an impact on digital data services,

encrypted services & on SDH
• The real contribution to synchronization is the frequency
offset of the receiver clock relative to the Primary
Reference clock
• Performance degradation can be controlled by:
– Use of several PRC’s
– Use of Robust clocks
– Proper Synchronization Planning
THANK YOU