Introduction to 2019.

06 VCS
CONFIDENTIAL INFORMATION
The information contained in this presentation is the confidential and proprietary
information of Synopsys. You are not permitted to disseminate or use any of
the information provided to you in this presentation outside of Synopsys
without prior written authorization.

IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans, such plans
are as of the date of this presentation and are subject to change. Synopsys is not
obligated to update this presentation or develop the products with the features and
functionality discussed in this presentation. Additionally, Synopsys’ services and products
may only be offered and purchased pursuant to an authorized quote and purchase order
or a mutually agreed upon written contract with Synopsys.

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Agenda

• VCS Setup and Use model Information

• Debugging with VCS
• Coverage with VCS
• Profiling designs with VCS
• References

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VCS Setup and Use Model Information
VCS Tool Flow
Setup and Environment
Analysis
Elaboration/Compilation
Simulation

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Introduction
What is VCS? VCS Supports two major flows

• Complete verification • 2-step flow for pure-Verilog

environment users
• Multi-language simulator • Compilation, Simulation
• VHDL, Verilog, SystemC, • 3-step flow for mixed-language
SystemVerilog, C/C++ users
• Optimized for maximum • Analysis, Compilation,
simulation performance! Simulation
• Why have 2 flows?
• VHDL requires bottom-up
analysis
• Many Verilog users are
familiar with old “Verilog-XL”
flow

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Pure Verilog Flow (2-step)

•Elaborate/Compile the design

– Specify all Verilog source code Elaborate/Compile Design
– Command: vcs vcs <option> <files.v>
•Simulate the design
– Command: simv
•Notes: Simulate
– No setup file is needed simv <options>
– Verilog has no concept of logical libraries

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Mixed-Language Flow (3-step)
Map Logical Libraries
•Map Logical Libraries synopsys_sim.setup
– Setup file: synopsys_sim.setup
•Analyze all Verilog source
Analyze VHDL and Verilog
– Command: vlogan vlogan <files.v>
•Analyze VHDL source, bottom-up vhdlan <files.vhd>
– Command: vhdlan
•Elaborate/Compile the design Elaborate/Compile Design
– Command: vcs vcs <options> <design_top>
•Simulate the design
– Command: simv
Simulate
Note: SystemC also uses this flow simv <options>

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VCS Setup

Setting Up Displaying Setup Information

• Set VCS_HOME environment variable to • Use show_setup utility

installation path • Displays settings of all VCS MX
• %> setenv VCS_HOME variables
<VCS_Install_Dir> • %> show_setup
• %> set path=($VCS_HOME/bin • To display library mapping information
$path) only
• Set license variable • %> show_setup -lib
• %> setenv SNPSLMD_LICENSE_FILE
port@host
• OR
• %> setenv LM_LICENSE_FILE
port@host

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Simulator Setup File
Map Logical Libraries
synopsys_sim.setup
• During analysis, VCS stores design information in a library
referred to as a logical library.
• This logical library is mapped to a physical library, which is Analyze VHDL and Verilog
a physical directory in your UNIX file system. vlogan <files.v>
vhdlan <files.vhd>
• You specify this mapping in the synopsys_sim.setup file as
shown in the example.
• Can be used for Verilog, VHDL or mixed-HDL designs Elaborate/Compile Design
vcs <options> <design_top>

Simulate
simv <options>

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Example synopsys_sim.setup

-- Logical Library Mappings

WORK > TB_LIB
TB_LIB : /prj/libs/tb_lib
DUT_LIB : /prj/libs/dut_lib
vendor : ../../vendor/libs

-- Simulator Variable Settings

TIMEBASE = NS
TIME_RESOLUTION = 1 PS

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Analysis
• Analysis step is only required for pure VHDL or mixed-HDL designs Map Logical Libraries
– vlogan or vhdlan parses the hdl file(s), does syntax checks, minimal synopsys_sim.setup
semantic checks and generates database.
– Analysis creates the following database files.
– .mra , .sim files following VHDL analysis Analyze VHDL and Verilog
– .DB directory following Verilog analysis
vlogan <files.v>
vhdlan <files.vhd>
• Analyze Verilog source
– Verilog has no order dependencies
– For pure Verilog designs, all files can be given on a single compile line Elaborate/Compile Design

• Analyze VHDL source

– VHDL is analyzed bottom-up
– If vhdl design unit instantiates verilog and the verilog file is Simulate
already analyzed or vhdl contains configuration specification simv <options>
(vhdl configurations), binding information is captured in the database

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 Mixed-Language Flow (3-step)
Analyzer (Verilog) Map Logical Libraries
%> vlogan [-help] [+define+macro] [-f file] [+v2k][-work synopsys_sim.setup
logical_lib] [+incdir+idir] [-l logfile][-v file][-y libdir]
[+libext+lext] [-sverilog][-timescale=time_unit/time_precision
]verilog_design_files
Analyze VHDL and Verilog
• Parses Verilog source into logical libraries vlogan <files.v>
• Instantiated VHDL design units are resolved during elaboration
vhdlan <files.vhd>
• Common Verilog file parsing options are available (-y, -v, -f etc.)

Analyzer (VHDL) Elaborate/Compile Design

%> vhdlan [-nc][-work library][-vhdl87][-output outfile][-f vcs <option> <design_top>
optionsfile] [-xlrm][-help][-vhdl08]VHDL_design_files

• Parses VHDL files into logical libraries

• Analyze VHDL blocks bottom up Simulate
• Partial elaboration during “configuration” analysis
simv <options>
• Resolves lower level instances by default

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Elaboration/Compilation
VCS command performs elaboration and compile Map Logical Libraries
• vcs entity_or_config_or_module <options> synopsys_sim.setup

Methodology: Elaborate/Compile once, Run multiple times

Analyze VHDL and Verilog
• The following tasks are performed in this process vlogan <files.v>
• Generic and parameter resolution - Resolves Generics/parameters in the vhdlan <files.vhd>
design with their specified values.
• File handle resolution - Opens file handles for reading or/and writing files.
vcs <option> <design_top>
• Design hierarchy and architecture resolution - Resolves multiple architectures.
• Code generation - Generates C code for the entire design.
• Elaboration/Compilation and Linking - Elaborates the generated code and Elaborate/Compile Design
statically links all objects to generate the simulation executable

Elaboration/Compilation creates the following files:

Simulate
• simv – Simulator executable
• simv.daidir/ – Simulator database files simv <options>
• csrc/ - Files used for incremental reElaboration/Compilation
• Output log files

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Review of File Parsing Options
In 3-step flow, these are
passed to vlogan instead
+define <macro> - Defines a macro in the Verilog source
-f file - Specify files as well as command options
-l logfile - Log file generation
-q - Quiet (no internal messages and banner)
-v <lib_file> - Specify a verilog library file
-y <libdir> - Specify a directory of Verilog library files
+libext_ext+<ext> - Specify library file extensions (used with -y)
-work <libdir> - Analyze into specified logical library
+nospecify - Remove timing in specify blocks
+notimingchecks - Remove timingchecks
+v2k - Enable Verilog 2001 constructs
-sverilog - Enable SystemVerilog constructs
-timescale=1ns/1ps - Specify default timescale
+incdir+<dir> - Specifies search directory for included files

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Executing the Simulator
%> ./simv <runtime_options>
• Run-time switches are available to do the following
– User-defined run-time controls
– Control VPD creation
– Modify assertion behaviors
– Collect code-coverage
• Some run-time options depend on how the simulation was compiled

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Common simv Options

-gv <gen=value> - Override runtime VHDL generics*

-ucli - Stop at Tcl prompt upon start-up
-i <run.tcl> - Execute specified Tcl script upon start-up
-l <logfile> - Create runtime logfile
-gui - Start interactive GUI session
-xlrm - Allows relaxed/non-LRM compliant code
-cm <options> - Enable coverage options

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Debugging with VCS
Compilation/Runtime step (KDB)
Debugging flow
Interactive debug
Post process debug
Performance effective debug

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Compilation/Runtime step
Compile time Use Model

• Just add the –kdb option to VCS executables when running simulation

• Three steps flow:

– % vlogan/vhdlan/syscan –kdb
– Compile design and generate un-resolved KDB to ./work
– % vcs –kdb –debug_access+all <other option>
– Generate elaborated KDB to ./simv.dadir
• Two steps flow:
– % vcs –kdb –debug_access+all <other option>
– Compile design and generate elaborated KDB to ./simv.dadir

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Run Time Use Model
Load KDB to Verdi
• Interactive Mode (debug with simulator):
– Add –verdi option to simv executable:
– % simv –verdi (or) -gui

• Post-Processing Mode (After getting the FSDB):

– Load KDB without FSDB
– % verdi –simflow –dbdir <path to>/simv.daidir
– Simply load the FSDB (using -ssf), the KDB will be loaded automatically:
– % verdi –ssf my.fsdb
– If you have move the simv.dadir directory to somewhere else, use the –dbdir option to load it:
– % verdi –ssf my.fsdb –dbdir <path to>/simv.dadir

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Debugging flow

• Two methods of debugging:

– Interactive Debug
– Source browsing, line stepping, breakpoints, etc
– Use model:
– vcs –debug_access+line –kdb <>
– ./simv –gui &
– Post-simulation Debug
– Generate a FSDB containing all waveforms
– Debug simulation after-the-fact
– Speeds up debugging!
– Instant access to all values at all times during the simulation
– Makes better use of your simulation licenses
– Standalone GUI does not use a simulation runtime license
– Use model:
– vcs –debug_access –kdb <>
– ./simv
– verdi –ssf <fsdb file> &

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Interactive Debug
Simulation
Control

Hierarchy
Signal Pane
Pane
Source Pane

Console Pane

Execute Batch
mode (UCLI)
command
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Post Process Debug

Source
pane

Hierarchy
Pane

Signal
List Schematic
Window

Waveform

Driver/Load
pane

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 nWave Overview
In the main window, invoke Tools -> New Waveform or click on the New Waveform icon to open nWave frame
• The nWave frame is opened in the bottom frame of the main window
• Click the Be Window icon can make it to be a standalone window
Marker Position

Cursor Position Delta Time

Ruler Zoomed Time

Signal
Cursor Signal Pane Value Position
Position Synopsys Confidential Information © 2020 Synopsys, Inc. 23
nWave Overview

• View FSDB in Signal pane:

– “nWave->Tool-> Preference->Waveform->View Options->Signal Pabe -> Display Ahead of Signal Name”
• View Full Hierarchy of Signal
– “View - > Hierarchical Name (H)”

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Performance Effective debug (-debug_access –debug_region) :

• Background:
– VCS Debugging in the past releases were more tuned to ease of use with a tradeoff on simulation runtime performance.
• Motivation to improve debug performance :
– Performance is important for everyone who does interactive, postprocess debug or just run regressions
• Value of –debug_access switch:
– The switch –debug_access is optimized for simulation runtime performance
– It provides fine grain control to the user by allowing incremental addition of desired debug capability
– Debug_access also provides umbrella options to improve ease of use

• Value of –debug_access with –debug_region switch:

– The switch –debug_region, further improves the runtime performance by restricting the capabilities only to desired design regions
– Use-Model:
-debug_access –debug_region+cell
• Value of Instance Based debug with –debug_region switch (LCA ):
– Maximizes debug productivity by restricting the capabilities only to desired instance
– Very easy to pass desired instance hierarchy thru vcs cmd line (No need to edit $fsdbDumpvars…in source)
– Use-Model: -debug_region=<depth,instance name>
-debug_access –debug_region=0,top.dut

Note: -debug_region without –debug_access will result in Error

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Performance Effective debug (-debug_access –debug_region) :
Option Name
Description
r This option enables the read capability for the entire design. This enables PLI access to get value, and enables the UCLI getcommand.
w This option applies write (deposit) capability tothe registers andvariables for the entire design.
wn This option applies write (deposit) capability to thenets for the entire design.
fn This option applies force capability to the nets for the entire design. This option is equivalent to -debug_access+r+fn.
fwn This option applies write (deposit) and force capability to all nets in the design. This option is equivalent to -debug_access+r+wn+fn.
f This option enables the following:
• Read capability on registers, variables, and nets
• Write (deposit) capability on registers and variables
• Force capability on registers, variables, and nets
This option is equivalent to -debug_access+r+w+fn+f
drivers This option enables driver debugging capability.
This option is equivalent to -debug_access+r+drivers.
line This option enables line debugging. It allows you to use the commands for step/next and line breakpoints.This option is equivalent to -debug_access+r+line.
cbk This option enables PLI-based callbacks on nets, registers, and variables. This option is equivalent to -debug_access+r+cbk.
cbkd This option enables both dumping andPLI-based callbacks on dynamic nets, registers, and variables defined in classes. Class object debugging is also enabled.
This option is equivalent to -debug_access+r+line+cbkd.
thread This option enables the debugging of the SystemVerilog threads. This option is equivalent to -debug_access+r+thread.
class This option enables debugging of the SystemVerilog classes and class objects, but the capability is also applied to the remainingportion of the design as specified by the -debug_region
option.
This option is equivalent to: -debug_access+r+w+thread+line+cbk+cbkd
pp This option enables write capability on registers and variables, callbacks for the entire design, driver capability, and assertion debug capability.
This option is equivalent to: -debug_access+w+cbk+drivers
reverse This option enables the reverse debugging feature.
all This option enables all the above options. This option is equivalent to:
-debug_access+r+w+wn+f+fn+fwn+drivers+line+cbk+cbkd+thread+class+pp+reverse
The -debug_access+alloption enables debug capabilities equal to -debug_all(except it does not apply capability inside cells and encrypted modules).
-memcbk The -debug_access-memcbkoption disables callbacks for memories and multidimensional arrays (MDAs). By default, -debug_accessenables callbacks for memories and MDAs.
For more information, see the “Incrementally Removing Debug Capabilities” section.
dmptf This option enables dumping of ports and internal nodes/memories of tasks/functions.

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Performance Effective debug (-debug_access –debug_region) :
-debug_access : -debug_region :
▪ New groups of debug capabilities. – cellports :
▪ simctrl : (-debug_access+r+cbk+assert_c) – Enable Dumping/Debug capability only on cell ports
▪ PLI and value change callback – SV (or) sv
▪ Assertion control (not assertion dumping) – Apply debug capabilities to any program, package, interface or
▪ FSDB/VPD Dumping module-containing-SV-constructs, and to SystemC.
▪ designer : (-debug_access+line+r+w+wn+cbk -debug_region+cellports) – Do not apply debug capability to V2K modules, fully encrypted blocks
– Read and write for both variables and nets and VHDL.
– PLI and value change callbacks and line callback – VERILOG (or) verilog
– FSDB/VPD dumping capability
– Apply debug caps to all VERILOG. Do not apply debug capability to
– Debugging or dumping of cell ports fully encrypted blocks and VHDL.
▪ Support to remove debug cap from debug_access (-X) – VHDL (or) vhdl
– Allow to remove debug capability from groups (all,class,designer,simctrl) – Apply debug caps to all VHDL Do not apply debug capability to
Ex: -debug_access+all-f // force capability removed from +all VERILOG.
▪ Enable/Disable Dumping/control assertion
– -assert_d : Remove Assertion dumping capapbilities from the “+designer” and +simctrl” options
– +assert_c : Enable assertion control
– +assert_f :
– Dumping failures and successes for both concurrent and immediate assertions
– Enables controlling assertions.
▪ Enable Verdi One Search
– +idents_so :Enable symbol search in the C/C++ domain
– +idents_db : Enable identifier search in the Design.
– Note: This feature is currently enabled by the -gen_db compile option.

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Coverage with VCS
• Introduction to coverage
• Generating coverage reports
• Analyzing coverage reports
• Advanced coverage features

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Introduction

• What is Coverage?
– Measures how much code is being exercised when the tests are run

• Code coverage analysis is the process of:

– Finding areas of a program not exercised by a set of test cases
– Creating additional test cases to increase coverage
– Determining a quantitative measure of code coverage, which is an indirect measure of quality.

• How is it useful?
– High coverage => lower chance of containing undetected software bugs

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How to enable Coverage
Basic coverage options

Compiling design files • Coverage metrics:

• Line
• Two step
• vlogan/vhdlan – Analyzing design files • Toggle
Code
• vcs top –cm line+tgl+cond+fsm+branch • Condition Coverage
• One step
• Branch
• vcs <Verilog files> -cm line+tgl+cond+fsm+branch
• FSM
Simulation and Monitoring coverage • Assertion
• Testbench/Functional
• simv –cm line+tgl+cond+fsm+branch
coverage
Post processing

• urg –dir simv.vdb

• verdi –cov –covdir simv.vdb

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Line Coverage Report

• Information Provided
– How many lines are covered during simulation
• Score Calculation
– Number of covered lines/Number of coverable lines
• Color Annotation
– Uncovered lines in RED color
– Unreachable/Excluded lines in GREY color
• Covers all types of statements
– procedural statements
– continuous assignment statements
– conditional statement
– Branches for conditional statements etc.

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Toggle Coverage Report

• Toggle coverage: How well design was exercised by testbench

• Score: Number of covered signals/Number of coverable signals

• Color Annotation
– Covered signals in GREEN color
– Uncovered signals in RED color
– Unreachable/Excluded in GREY color

• Identify signals which were not initialized

• Locate areas of the design which are not properly tested by the TB

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Finite State Machine Coverage Report

• FSM coverage: Report, whether the simulation run could reach all of the states and cover all
possible transitions

• Identify block of code that make up Finite State Machines. Reports states, transitions and
sequences of states during simulation

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Condition Coverage Report

• Condition coverage: How well variables and expressions are evaluated.

• All possible cases are analyzed and reported in truth table format
• Condition coverage tests whether both true and false states of these conditions were covered
during simulation.

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Branch Coverage Report

• Branch coverage: Which part of condition is executed in simulation. Statements are evaluated in
both true and false cases

• Monitors the execution of conditional statements such as if/else statements, case statements,
and the ternary operator "?:" in a design

• Analyzes how if and case statements and the ternary operator (?:) establish branches of
execution in design.

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Post processing command
Unified Report Generator -- Options
• URG generates reports for all types of coverage information.
% urg –dir simv.vdb –format <text/both>
– Text reports: Static, useful to parse/analyze using scripts
– asserts.txt dashboard.txt groups.txt grpinfo.txt hierarchy.txt modinfo.txt modlist.txt tests.txt
– HTML reports: Interactive, can be loaded using firefox
– asserts.html dashboard.html groups.html hierarchy.html modlist.txt tests.html

% urg –dir simv.vdb –report My_urgReport

% urg –dir simv.vdb –report My_urgReport -parallel
% urg –dir simv.vdb –metric line+tgl
- Generate report only for line and toggle metric
% urg -help

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Post processing command
Unified Report Generator -- Merge
• Merging:
– Process that generate single coverage data base from given list of VDBs

% urg –dir simv1.vdb simv2.vdb –dbname merge1.vdb –report urgMerge

% urg –dir simv1.vdb simv2.vdb –dbname merge2.vdb –noreport
% urg –f list_vdb.txt –dbname merge3.vdb
cat list_vdb.txt
simv1.vdb
a/b/c/simv2.vdb
../b/simv3.vdb

% urg –dir merge1.vdb merge2.vdb –dbname mergeFinal.vdb

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Post processing command
Verdi
% verdi –cov –covdir simv.vdb
– Load coverage database
% verdi –help
– URG command can be executed via Verdi

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Analyzing Reports
• Text reports: Static, useful to parse/analyze using scripts
– asserts.txt dashboard.txt groups.txt grpinfo.txt hierarchy.txt modinfo.txt modlist.txt tests.txt
• HTML reports: Interactive, can be loaded using firefox
– asserts.html dashboard.html groups.html hierarchy.html modlist.txt tests.html

dashboard

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Analyzing Reports • SCORE:
• Average of (No. of covered
Dasboard.html objects for each metric/Total no.
of coverable objects for each
metric) for all instances

• Total Coverage Summary:

• 89.10 + 46.05 + 68.40 + 63.30 +
75.49 + 42.86 + 1.59 = 386.79/7
= 55.2557 Rounded to 55.26

• Hierarchical Coverage data:

• 89.10 + 46.05 + 68.40 + 63.30 +
75.49 + 42.86 = 385.2/6 = 64.2

• Module definition coverage:

• Average of (No. of covered
objects for each metric/Total no.
of coverable objects for each
metric) for each module

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 Score of (test_jukebox + cd1 +
Analyzing Reports fifo1 + jb1 + st0 + st1 + st2 +
st3 + st4)
Hierarchy.html
• Calculation of Metric wise (COND) score for ‘fifo1’

• Calculation of score for each instance ‘cd1’

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 Score of
Analyzing Reports (fifo+kp_fsm+coin_fsm+jukebo
x+station+test_jukebox+cd)
Module list

• Module wise per metric

calculation:

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Analyzing Reports
Using Verdi GUI

• Hierarchical view in Verdi GUI

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Analyzing Reports
Using Verdi GUI

• Module view in Verdi GUI

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Advanced Coverage features

Test grading

• Grading enables to compare the effectiveness of a set of tests against each other.
• Help to eliminate redundant tests from a test suite. Test grading results are reported in the tests.html/tests.txt pages.
•% urg –grade help to know details of grading techniques

Merging of block level to SOC level VDBs

• Merging block level to SOC coverage database results in URG warnings if the design hierarchy changes across VDBs.
Tool cannot merge coverage data in such cases.
•-map, -mapfile option allow merging of coverage data from non-identical designs if design hierarchy changes
• More details are documented in coverage user guide/reference guide

Exclusions

• Tool do not monitor objects which are not interested to user, thus increasing coverage score
• Defualt mode: Allows covered or uncovered object to exclude
• Strict mode: Allows only uncovered objects to exclude
• Look for option –dump full_exclusions in urg -help

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Coverage database
Generation
• Coverage data for all the metrics (Line, Toggle, Branch, Condition, FSM, Assertion, and
Functional coverage) is accumulated in a single directory, simv.vdb

– vcs -sverilog jukebox.v -cm line+tgl+cond+branch+fsm+assert

– simv -cm line+tgl+cond+branch+fsm+assert
– urg -dir simv.vdb -format both -report urgTrial

• Coverage data is collected both at compile time, run time

– Compile time database: simv.vdb
– Run time database: simv.vdb

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Coverage database
How to rename coverage database

Method 1:

• vcs -sverilog jukebox.v -cm line+tgl+cond+branch+fsm+assert –o simv1

• simv1 -cm line+tgl+cond+branch+fsm+assert
• urg -dir simv1.vdb -format both -report urgTrial
• Compile/Run time database: simv1.vdb

Method 2:

• vcs -sverilog jukebox.v -cm line+tgl+cond+branch+fsm+assert -cm_dir comp.vdb

• simv -cm line+tgl+cond+branch+fsm+assert -cm_dir run.vdb
• urg -dir comp.vdb run.vdb -format both -report urgTrial
• Compile time database: comp.vdb
• Run time database: run.vdb

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Code coverage metrics
Sub options of code coverage metrics

Metric Switch to How to pass Values of sub-options

enable Sub-option
LINE -cm line -cm_line contassign
Condition -cm cond -cm_cond full, allops, std, basic,for, event, tf, ports,
allops
Branch -cm branch -cm_branch values
FSM -cm fsm -cm_fsmopt reportvalues, allowTmp, reportWait,
Toggle -cm tgl -cm_tgl mda, portsonly, structarr, fullintf

How well the design code has been executed by the tests.

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Test grading
• Grading:
– Grading enables to compare the effectiveness of a set of tests against each other.
– Help to eliminate redundant tests from a test suite
– Types of grading
– Index (Default)
– Score
– Cost based
– urg grade -help

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Test grading
• Example:
– Given a testsuite which has tests from T1, T2,…. T10
– This option help to find which test is more effective in verifying the design.
– Cumulative scores will also be reported in “tests.html/txt” reports

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Mapping code coverage

• Mapping:
– Merge coverage data from non-identical designs if design hierarchy changes
– Merging results in URG warnings if the design hierarchy changes across VDBs. Tool cannot merge
coverage data in such cases.
– To overcome this use the option “-map, -mapfile”

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Mapping code coverage
Module based Mapping
Command: urg -dir base.vdb -dir input.vdb -map m11

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Mapping code coverage
Instance based Maping
Command: urg -dir base.vdb -dir input.vdb -mapfile mapfile.cfg
The mapping configuration file for this example will contain the following information:
MODULE: m11
INSTANCE:
SRC: design2.tb1.m11.inst11, design2.tb2.m2.inst2
DST: design1.m1.m11.inst11

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Exclusions
Unified Report Generator -- Exclusions
• Exclusions
– Important in coverage closure
– Does not monitor objects which are not interested to user, thus increasing coverage score
• Defualt mode
– Allows covered object to exclude
• Strict mode
– Allows only uncovered objects to exclude
% urg –dir simv.vdb –dump full_exclusions
– Generate elfiles with fullexclude.<metric>, fullexclude_module.<metric>
– Uncomment the exclusions in the file and generate report with urg
% urg –dir simv.vdb –elfile fullexclude.line

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Exclusions
Unified Report Generator -- Exclusions
• Option to urg “-dump full_exclusions” dumps the files
– fullexclude.line
– fullexclude_module.line Signature

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Exclusions
Verdi
• Save excluded items
• Load exclusions
• Load exclusions from a file
• Exclude instance, tree, module
• Exclude specific metric for instance/module

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Exclusions
Verdi

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Exclusions
Verdi
• Before exclusions

• After exclusions

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Profiling designs with VCS
Introduction to Profiling
Runtime Profiling
Constraint Profiling
UVM Time Profiling

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Introduction to Profiling Multiple Views facilitate deep analysis

• Why profile the design?

– To identify reasons of slow runtime.
– To identify causes of high memory usage

• Simple use model

– vcs –simprofile …
– simv –simprofile [time|memory]…
– profrpt –view time_all|memory_all –filter 0 simprofile_dir –output report_dir

• Detailed yet easy to navigate report

– Source Information available

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Simprofile Use Model
• After the simulation is over the following files/directories will be created:-
– simprofile_dir directory
– A directory called “simprofile_dir”, this will have the samples.
– profileReport directory
– A directory called “profileReport”, this will have the HTML docs.
– profileReport.html file
– An HTML document called “profileReport.html”, this will have the summary report.
– profileReport.txt file
– An Text document called “profileReport.txt”, this will have the summary report.
– The content of the above files/directories depend on the kind of profiling happened during the runtime.

• User can use “profrpt” executable post process to extract customized report.
– “profrpt –h” will show all possible switches and explain them.

• Reports are available in HTML or Text format.

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Runtime Profiling Summary View,
provides overview of
time consumed at
high level

Construct View,
helps to locate
code blocks
consuming most
time

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Identify Performance Bottlenecks in Constraint solving
• Unified Runtime Profiler

% vcs –simprofile …
% simv –simprofile time …
Simprofile reports include constraint profile data

• Constraint-only Performance Profiler

% simv +ntb_solver_debug=profile …

to use the same runtime options when profiling

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Constraint Profiling

• General Statistics
– Total user time
– Total randomize time
– Total randomize count
– Largest memory increment

• Top randomize/partition based on

– CPU time
– Memory increment
– Cumulative CPU time

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What’s in a Constraint Profile Report?

• General Statistics
– at the top of the report

• High Level Breakdown of Time

– at the bottom of the report

– Core Solver
– Problem Generation

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Ranking of Top Randomize (Runtime)
• Top randomize calls
– by CPU Runtime

– by Cumulative CPU Runtime

• Top partitions

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Ranking of Top Randomize (Memory)
• Top randomize calls
– by Memory Increment

– by Cumulative Memory

• Top partitions

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UVM Time Profiler
• Introduction
– Provides user view of profile data
– Provides object level details for each call to UVM class methods
• Value
– Faster debug TAT to narrow down Performance issues related to UVM Testbench

• Use model
– Compile Time: -simprofile=uvm
simprofile=uvm:user : Dumps data for user classes
simprofile=uvm:component (default) : Dumps data for UVM component and derived classes
simprofile=uvm:all : Dumps data for all classes
– Run Time: No change. By default uvm_profiler.db is generated.
– Report Generation: uvmprofrpt -uvm_profiler=db:uvm_profiler.db
– Additional report options are available. Please refer to LCA user guide.

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 UVM Time Profiler
• Flat View – Based on Count and Time Consumption

UVM Base
Class
Functions

User Class
Functions

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UVM Time Profiler
• Hierarchical View – Based on UVM Object Hierarchy

UVM Object
Hierarchy

Limitation
UVM Phase based reporting is currently not supported
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References

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References

• VCS® MX Quick Start Guide – describes usage of

– Simulating your design
– Perform basic debugging tasks
– Monitor Coverage to measure Verification status and completeness
– Check design correctness using assertions

• Simprofile Video Tutorial

– Memory Profiling
– Runtime Profiling

• Coverage
– https://solvnet.synopsys.com/dow_retrieve/latest/ni/vcs.html
– Coverage technology User guide
– Coverage technology Reference Manual
– https://knowledgeshare/Pages/home.aspx
– KnowledgeShare Webinars

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Thank You