Design and Analysis of

Power Supply Networks 23

Rajendran Panda, Sanjay Pant, David Blaauw, and Rajat Chaudhry

CONTENTS
23.1 Introduction 590
23.1.1 Power Supply Noise 590
23.1.2 Performance and Power Issues 591
23.1.3 Reliability Issues 591
23.1.4 Electromagnetic Compatibility Issues 592
23.2 Impedance and Resonance 592
23.3 Power Network Analysis 596
23.3.1 Static and Dynamic Analyses 596
23.3.2 Hierarchical Analysis 597
23.3.3 Vectorless Analysis 599
23.3.4 Incremental analysis 600
23.4 Power Network Design 602
23.5 Conclusions 604
Acknowledgments 604
References 604

589

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590    23.1 Introduction

23.1 INTRODUCTION

Device scaling over several process technology generations has permitted the integration of an
extremely large number of transistors on a single die. Combined with faster switching speeds
achievable with advanced lithographic and fabrication technologies, the power dissipation of
chips has grown at a very rapid pace. The operating voltage has been scaled down to reduce
power dissipation, thus shrinking the voltage drop allowed on the chip power and ground
distribution for the correct operation of the circuit. Unless the overall power distribution net-
work is designed adequately for the power demands of the chip, the entire design will be vulner-
able to many issues as discussed in this section. These issues and the related design challenges
are obvious for high-performance processors that need to deliver a very large amount of power
and accommodate more severe power transients. In reality, the problem is no less important or
less challenging for low-power processors such as mobile application processors, as their power
distribution network design has to consider many different operating modes resulting from
clock gating, power gating, multiple power domains, dynamic voltage, and frequency-scaled
operation and also has to be implemented using fewer routing layers and cheaper packages due
to cost consideration.
The power supply network encompasses all devices and wiring involved in the generation
of DC power supply voltages for the chip’s circuits. It also includes all wiring (and decoupling
capacitances) distributed across the die and package of the chip, and the discrete com-
ponents (and their wiring) for generation and regulation of power supply voltages on the
circuit boards in the system. The current return (ground) network is also a key element of
the power supply distribution. In the remainder of this chapter, we will use the popular acro-
nym PDN (for power distribution network) to refer to both the on-chip and off-chip power
supply systems.

23.1.1 POWER SUPPLY NOISE

Due to resistance in the PDN, a voltage difference, commonly referred to as the IR drop, is
observed between the supply origin and loads. For an instantaneous current i(t) flowing through
a wire segment of resistance R, a voltage of i*R is dropped across the segment in the direction of
current flow. The voltage drop seen at any point in the network is the sum of voltage drops of
segments of any path from a supply source to that point.
The package brings power and ground supplies to the die either by means of package leads
in wire-bonded chips or through controlled collapse chip connections, known as C4 bumps [1],
in flip-chip technology. While the resistance of the package PDN itself is quite small, the induc-
tance, contributed mainly by the package-to-die interconnections (leads or bumps), is significant.
The inductance responds sluggishly to fast changes in the delivered current by causing a dynamic
change in local supply voltage that is proportional to the amount of inductance (L) and the rate of
change of current (di/dt). This component is referred to as the L*di/dt drop (although it may be a
negative or positive contribution to the supply voltage). The sum of resistive and inductive losses,
namely, i*R + L*di/dt, is the power supply noise seen by the chip’s circuits and can be problematic
if it is excessive.
Capacitors between power and ground distribution networks, referred to as the decoupling
capacitors (or decaps for short), act as local charge storage and help in mitigating the L*di/dt
voltage drop at loads. Parasitic capacitances between power and ground wires, diffusion and
gate capacitances of devices, and capacitances between wells and substrate provide a certain
amount of decoupling intrinsically. Unfortunately, these parasitic capacitors are not enough to
smooth out the noise to within safe limits, and hence additional dedicated decoupling capaci-
tance structures need to be placed on the die at strategic locations [2–4]. These added devices
are not free; they increase the die area and the leakage power dissipation. The distributed
resistance, decoupling capacitance, and inductance in the power network form a complex
resistance, inductance, and capacitance (RLC) network with resonant nodes [5,6]. During the

© 2016 by Taylor & Francis Group, LLC

 Chapter 23 – Design and Analysis of Power Supply Networks    591

operation of the chip, if power transients occur at frequencies close to these resonance nodes,
large voltage drops can develop in the grid.

23.1.2 PERFORMANCE AND POWER ISSUES

Voltage droops at the gates of a logic signal transition path slow the signal propagation along
that path, and so the maximum speed at which a circuit can be operated safely is limited by the
worst-case voltage noise in the PDN [7,8]. In clock generation circuits, the power supply noise
contributes to clock jitter [9], which reduces the useful part of the clock cycle time available for
logic computation.
The impact of PDN noise on total dissipated power and the preservation of operating margins of
a design are other concerns. As the dynamic power dissipation of a chip is proportional to the square
of the supply voltage, raising the supply voltage by, say, 15% to compensate for the worst-case noise
in the chip will result in a 30% increase in power dissipation. Moreover, the voltage regulator (VR)
designed to handle a wider noise band needs a bulkier low-pass filter and is less efficient.
Timing margins are impacted adversely by power supply noise either directly (e.g., additional setup
and hold margins at clocked sequential circuits for supply variation) or indirectly (e.g., greater
margins for higher clock arrival skew [10] and jitter [9]). Noise from the power supply also
propagates as noise in both analog and digital signals. As a result, the functional (glitch) noise
will have to be margined appropriately. PDN noise thus creates a need for higher design efforts to
tackle functional noise issues.

23.1.3 RELIABILITY ISSUES

A poorly designed power network contributes to chip reliability problems such as electromigra-
tion failure in the wires and gate oxide failure in the devices.
The flow of unidirectional current in a metal wire segment for an extended time period causes
transport of some metal mass itself in the direction opposite to that of current flow. The metal ions
move by gaining momentum from the conducting electrons, creating gaps and hillocks at certain
locations of the conductor over a period of time, and may eventually lead to open or short circuit
failures. The mean time to failure of the conductor is dependent (superlinearly) on the inverse
of the current density in the conductor [11]. Even before a catastrophic open/short failure,
the resistance of the conductors can increase substantially, causing the IR drop to be elevated.
To guarantee a certain lifetime of the reliable operation of a chip, the current densities through
the PDN wires will have to be limited to levels appropriate for the chip and the fabrication
process technology. The power network design should therefore ensure that conductors are sized
adequately and the current distribution has no current density hot spots.
Reversing the direction of current in a conductor segment contributes to some recovery and
healing of the electromigration mechanism. However, this recovery is only partial. Therefore, a
conservative check for current densities could use time-averaged currents in a single direction
(ignoring the recovery due to the flow in the other direction) or, if using time-averaged bidirec-
tional currents, rely on conservative margins in the determination of load currents or the duty
factor. The structure of a typical multilayered PDN, with supply connections on the highest metal
layer and loads connected to the lower layers, causes the current in wire segments to exhibit
unidirectional flow. This is due to the gradual decrease in pitch from higher to lower layers, and
as a result, the current in a segment of upper tiers is the aggregate of currents in several segments
of lower tiers. Current in segments of lower layers may switch direction more often due to spatial
shifting of switching activity from one region of the chip to another and thus may show weaker
directionality. However, higher layer segments show strong directionality and are thus more prone
to electromigration failure.
Gate oxide failures may be triggered and accelerated by repeated overstressing of the gate
terminals of devices with overshooting input voltages resulting from a poorly designed PDN.
Even when there is no failure, the excess stress will contribute to increased gate leakage.

© 2016 by Taylor & Francis Group, LLC

592    23.2 Impedance and Resonance

23.1.4 ELECTROMAGNETIC COMPATIBILITY ISSUES

PDN design has to consider electromagnetic compatibility issues in certain products as well, for
example, microcontrollers for automotive applications [12]. High frequency noise in long wire
traces of the power supply system (typically in the package and board traces) is a significant source
of electromagnetic radiation. For systems where radiation is regulated very stringently, the power
delivery design has to filter noise with adequate decoupling capacitance on the die and ensure that
the energy in the high frequency band of the noise spectrum in power traces is within limits.

23.2 IMPEDANCE AND RESONANCE

Figure 23.1a shows a simplified model of the chip power distribution system consisting of the
system board, package, and the die. A VR placed off-chip is shown as a variable DC source with
a series resistance. Later in this section, we will discuss the integration of on-chip VRs. The electrical
models for the board and package are shown as series–parallel RLC. The die is represented by
a single independent current source element, which is the aggregate of the currents drawn by
all the active devices, in series with an effective resistance of the on-die PDN and in parallel to a
capacitance, which is the sum of intrinsic and intentionally added decoupling capacitors.
Figure 23.1b shows the characteristic of the looking-in impedance Z in the frequency domain.
The impedance graph shows a peak at the natural or resonant frequency of the overall power
system [6]. Since the R, L, and C components are in reality distributed, the system may have more
than one resonant node [5]. Current variations occurring at different frequencies each contribute
to noise in the power supply voltage in the amount of I( f )*Z( f ). If a power system is to have not
more than x% noise on the node voltages, we need to satisfy that

òZ ( f ) * I ( f ) df £ xV
0
dd / 100

The power supply noise problem is so acute in today’s designs that it becomes necessary to focus
on both the variables on the left side of this equation, with very significant consequences for the
needed design effort. Reducing Z( f ) is largely the task involved in the power distribution design
itself, while controlling the magnitude and frequency of currents (characterized by the I( f )
spectrum) requires design efforts that span the architecture, circuit design, and physical imple-
mentation teams. We will defer the discussion of controlling currents and current transients to a
later section and focus here instead on controlling the impedance factor.
Figure 23.2a shows the impedance of an initial network and Figures 23.2b and c illustrate how
this impedance is reduced and reshaped during power network design. The resistive component
R (which equates to Z(0) and is also called the active component) is a highly effective control

Die Package PCB VR

V
|Z( f )|

+
Decap

Decap
Decap

I Vo
--

f
f0
Z = (Vo – V)/I
(a) (b)

FIGURE 23.1 (a) Simple model of a power distribution network (PDN) with off-chip VR. (b)
Looking-in impedance Z of the PDN.

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 Chapter 23 – Design and Analysis of Power Supply Networks    593

|Z( f )| |Z( f )| |Z( f )|

f0 f f0 f f0 f
f0΄
(a) (b) (c)

FIGURE 23.2 (a) Frequency dependence of impedance of a power distribution network.

(b) Reduction of impedance by reducing the resistance. (c) Reduction of peak impedance.

variable as its effect pervades the entire frequency spectrum. Reducing wiring resistances has the
effect of pushing the entire impedance curve down while approximately preserving the shape.
This is illustrated in Figure 23.2b. This task requires significant routing resources and design
efforts. Common measures include

◾◾ Widening of power and ground wires

◾◾ Adopting denser wiring pitches
◾◾ Strapping wires with more vias
◾◾ In some extreme cases, adding another layer to the metal stack

The reshaping of impedance shown in Figure 23.2c is done by altering its reactive component.
The impedance peaks are reduced by reducing the inductive parasitic elements and increasing the
decoupling capacitance in the PDN. Measures to reduce the peaks include

◾◾ Increasing the number of power/ground connections at the board/package and package/

die interfaces
◾◾ Trimming inductances of traces and vias in the board and package
◾◾ Adding more decoupling capacitors on the die, package, and the circuit board

The resonance frequency is shown to move down (from f0 to f0′) in Figure 23.2c, as is typical when
on-die decaps are added. It may, however, be noted that the resonance frequency may shift in the
other direction if package inductance is reduced or is shielded by addition of embedded decaps
in the package or by moving the package decaps closer to the die. In either case, the impedance
peak will be reduced.
Attention should be paid to the magnitude of current variations at or close to the resonance
frequencies since their contribution is weighted heavily by the impedance peaks. It should be
noted that reducing the resistance of the power network has a side effect of rendering the
resonance peaks to be quite sharp. A simple LRC model shown in Figure 23.3 is helpful in
understanding the noise and resonance behaviors.

L
R
∆v(t)

0V
C ∆i

FIGURE 23.3 A simplified model of the power distribution network.

© 2016 by Taylor & Francis Group, LLC

594    23.2 Impedance and Resonance

The capacitance in this model is predominantly the decoupling capacitance on the die and the
inductance is primarily from the package. The response ΔV(t) to a step input of ΔI is the familiar
waveform given by

R
L - 2L t
DV (t ) = DI * R + DI * e sin(wr t - q)
C

where
1
wr =
LC

is the chip-package resonance frequency.

The noise voltage is a damped sinusoidal waveform superimposed on a ΔI*R base. The noise is
damped by the R/2L factor and oscillates at the resonance frequency, ωr. The maximum noise is
determined by ΔI, L, and C. As inductance is governed by physical dimensions [13,14], it cannot
be easily reduced beyond a limit. Decoupling capacitors help to reduce the noise, but they have a
diminishing return owing to the 1/ C relationship. In view of this behavior, controlling sudden
power variations (or fast ramps) is the most direct and effective method available to reduce the
PDN noise.
The chip-package resonance frequencies of current technologies are typically much smaller
than their core clock frequencies. This has certain consequences. On-chip decoupling capaci-
tance effectively suppresses the high frequency noise (due to power variations within a clock
cycle). However, low frequency noise due to power fluctuations averaged over many cycles, espe-
cially noise at frequencies close to the resonance frequency, sustains oscillations over many clock
cycles, and the capacitors on the die cannot supply charge for that many cycles. Adding more
capacitance further decreases the chip-package resonance frequency, making the decoupling less
effective. Thus, controlling power fluctuations becomes a very important design objective and
will be discussed in Section 23.4.
On-chip voltage regulation is an attractive alternative solution to the transient noise issues.
Figure 23.4 shows a power system with an on-chip VR. Linear, as well as switched, regulators have
been used for on-chip integration [15,16]. The benefits of on-chip integration of VR are multifold:

◾◾ The VR on the die is closer to the loads and intercepts the inductance and resistance of
the package and the printed circuit board (PCB), reducing the mid-frequency resonance
depicted in Figure 23.2 significantly. The result is a faster response time to power transients.
◾◾ Multiple regulators can be distributed on the chip near different load centers, such as
the core-cache clusters. The distributed scheme allows individual regulators to respond
appropriately to correct the local noise they sense and thus facilitate operating all the
regulators more efficiently.
◾◾ For a chip design with multiple discrete power domains, a distributed VR scheme yields
better shielding of noise between the power domains.
◾◾ Real estate on the PCB occupied by off-chip VR components is freed up, resulting in a
better form factor of the system and potentially an overall cost reduction.
◾◾ On-chip switched regulators can achieve faster switching speeds and so will need
smaller filtering elements (L and C). This makes the trade-off between response time
and efficiency more attractive for the on-chip implementation.

However, on-chip voltage regulation also has many challenges for design and integration. A low
dropout (LDO) linear regulator designed to eliminate an external capacitor [15] is an easy
integration option, and it provides a faster response time though at lower efficiency. Power con-
siderations, especially for high-performance systems, favor the use of switched regulators and LC
filtering (even for LDO). Capacitance is more easily integrated on the die, whereas integration of
inductance is challenging and costly. Air core inductors placed in the package or mounted directly
on the die have been considered. Air core inductors do not saturate, but the efficiency is poor due
to their relatively high DC resistance (DCR). Inductors based on ferromagnetic materials, on

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 Chapter 23 – Design and Analysis of Power Supply Networks    595

Die VR Package PCB Power

supply
V
On-
chip +

Decap

Decap

Decap
I
voltage –
regulator

FIGURE 23.4 Power distribution network with on-chip voltage regulator.

the other hand, have a lower DCR, but suffer from saturation at higher load currents. Regulator
design with multiple switch and inductor pairs connected in parallel, but switching in a multi-
phase staggered manner, has been proposed as it inherently reduces the ripples to be filtered and
thus will require smaller filtering components to be integrated. It can thus be seen that one of
the challenges in designing on-chip voltage regulation is achieving the best trade-off between effi-
ciency, response time, and ease of integration. Another challenge lies in ensuring that the design
has no stability issues from the complex interactions between the multiple regulators and load
domains [17]. Since the PDN is very large and also includes the active devices from regulators,
sensors, and controllers, circuit simulation and stability analysis required to guide the design
become extremely challenging.
The R, L, and C of the PDN with on-chip or off-chip VR need to be accurately modeled to
analyze and modify its dynamic behavior. Most components can be extracted and modeled quite
accurately using the extraction tools for PCB, package, and chip layouts. The modeling of intrinsic
(i.e., parasitic) decoupling capacitance in circuits, however, is not straightforward. The gate, diffu-
sion, well, and wiring capacitance in circuit blocks that are coupled from internal nodes to power/
ground provide a nontrivial amount of decoupling action when the internal nodes are stationary
(i.e., not switching). Ignoring this contribution leads to overestimation of decoupling capacitance
cells to be added to the design. A simple and effective way to model the intrinsic decoupling
capacitors is to characterize the basic circuit structures as capacitance (with series resistance)
when these circuits are not switching and instantiate the characterized RC values after discount-
ing C by a factor equal to the switching factor of that circuit instance [18]. Figure 23.5 illustrates
this characterization idea. The circuit is put in random but valid quiet states. The Vac variation
(about 10% of Vdd) around the Vdd bias mimics the supply noise. The capacitance is measured and
averaged over multiple quiet states and over the Vac frequency range of about 0.1X–10X of the
clock frequency.

Vac Iac

~
VDD Iac

Ceff

Vdd

Reff

GND
θ

Vac

Inputs set “quiet”

FIGURE 23.5 Characterization of intrinsic decoupling capacitance of circuits.

© 2016 by Taylor & Francis Group, LLC

596    23.3 Power Network Analysis

23.3 POWER NETWORK ANALYSIS

Power network verification is a very challenging task, primarily due to the very large size of the
electrical circuits that need to be simulated. All the active devices on a chip, several millions to
billions in count, are connected to only a handful of power nets. Since the parasitic elements
and devices on a power net form a tightly connected system, meaning the voltage response in
every part of the network is affected by the excitation current in some part, the entire net has to
be simulated as a whole for best accuracy. However, Spice-like simulation of a circuit with such
a large number of active and passive elements is impractical. So this giant task is split into two
simpler decoupled tasks as defined here:

1. Transistor-, gate-, or RTL-level power estimation simulations for the circuit blocks,
assuming an ideal power supply
2. Simulation of the power nets with the passive parasitic elements and currents obtained
from the first task attached to the PDN at the appropriate nodes

Although currents drawn by active circuits and supply voltages at the locations of these
circuits are dependent on each other, this circular dependency is ignored by treating the
currents as independent of the voltages. As a second order effect, the error due to this is small
(typically about 0.5% of Vdd) and conservative. This simplification is necessary to make PDN
analysis practical, but this still requires a very large passive network with 10 6 –109 circuit
nodes to be solved.

23.3.1 STATIC AND DYNAMIC ANALYSES

Power grid simulation involves solving a system of differential equations using circuit simulation
approaches, such as the nodal or modified nodal analysis [19]:

(23.1) Gx ( t ) + Cx¢ ( t ) = b(t )

where
G is the conductance matrix
C is the matrix resulting from capacitive and inductive elements
b(t) is the vector of ideal voltage sources and time-varying current sources
x(t) is the vector of node voltages, inductor currents, and currents drawn from voltage
sources
x′(t) is the time derivative of x(t)

This differential system is very efficiently solved in the time domain by reducing it to a linear
algebraic system:

æ Cö C
(23.2) ç G + ÷ x ( t ) = b ( t ) + x(t - h)
è hø h

using the backward Euler technique with a small fixed time step, h. As the new conductance
matrix on the left-hand side, (G + C/h), does not change during simulation, it can be preprocessed
or factored for a one-time cost and efficiently reused to solve the system at successive time points
in a transient simulation.
In static analysis, only resistances in the power network are considered and constant (DC)
currents are applied as loads to drive the analysis, so that the results show the IR component of
the noise. Equation 23.2 in this case reduces to

(23.3) G ×V = I

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 Chapter 23 – Design and Analysis of Power Supply Networks    597

where
G is the conductance matrix
V is the vector of node voltages (unknowns)
I is the vector of load currents

Power supply sources to the network are modeled as Norton current sources that contribute
elements to the diagonal of the G matrix and to the vector I on the right hand side.
Solution of sparse linear systems is a well-studied area and numerous direct, iterative, and
hybrid techniques are available to solve Equation 23.2 [20,21]. However, the extremely large size
of PDN systems has demanded a continued research into solution methods. Direct methods
decompose the left-hand side matrix for a one-time cost as a product of invertible upper and
lower triangular matrices, known as the L and U factors, and then solve the system at every time
step of a transient simulation in an inexpensive backward and forward substitution procedure
using these factors. When Equation 23.2 is formulated to have only node voltages as variables, the
conductance matrix can be shown to be positive definite and can be factored more efficiently into
LLT. If sufficient memory is available, factorization of the matrix can be done for multiple time
steps, for instance, h, 2* h, 4* h, and 8* h, so that the transient simulation can be carried out more
efficiently by dynamically choosing the time step, depending on input activity, output response,
and error behavior.
The single biggest problem with direct methods is the need for large memory to store the factors.
Memory management relies on very high sparsity of the factored matrix and the resultant
factors so that only their nonzero entries need be stored. However, as the fills (i.e., nonzeroes in
the factors) grow superlinearly if not in a quadratic fashion, the memory requirement of factoring
methods is very sensitive to the sparseness of the matrix. The amount of fills also depends on the
ordering of the matrix. Fortunately, the power network matrix is very sparse since each node in
the network is connected only to a very few nodes. The high sparseness, combined with matrix
reordering heuristics, achieves a very slow growth of fills during the factoring process and thus
makes it a viable approach even for very large size systems. Where a matrix is not very sparse or
the memory resource in the computer is limited, iterative methods become more advantageous
than direct methods.
Iterative methods start with a guess value for the solution and progressively refine it by reducing a
norm of the error vector with computations involving chiefly matrix-vector multiplication. Thus,
their memory demand does not grow significantly. However, this comes at the price of longer
solution times of iterations whose convergence is slowed by the ill-conditioning of the matrix.
Improving the condition number of the matrix by preconditioning [20–22] makes the iterative
methods competitive with direct methods. The preconditioned conjugate gradient (PCG) method
is widely used in the industry for PDN simulation. Successful use of other iterative methods, such
as the multigrid [23,24] and random walk [25] methods, has also been reported. Since faster
convergence is critical in achieving practical and competitive run times for PDN simulation, much
attention has been given to designing very effective preconditioners [26]. Preconditioners based
on incomplete Cholesky factors, fast transforms [27], multigrid reduction [24], and random walk
[25,28] have been used quite successfully in conjunction with the PCG method.

23.3.2 HIERARCHICAL ANALYSIS

As a strongly coupled system, the power network needs to be simulated as one system for correct
results. The work reported in [29] demonstrates strong locality of currents in regions bounded by
the C4 bump power supply connections to the die. This work proposed a method to divide the
network into partitions and simulate each partition independently to get an approximate solution
that is very close to the exact solution when the locality is strong. The authors of [30] formulated a
hierarchical analysis approach that gives the same (exact) solution as the full flat simulation, with
partitions formed arbitrarily or defined naturally by the design hierarchy. Considering a two-level
design hierarchy for simplicity of description, the network in each hierarchical block is mod-
eled independently as a local partition. The global partition includes the interface nodes between
the global and the hierarchical blocks. Mathematical abstracts of the partitions, which are the

© 2016 by Taylor & Francis Group, LLC

598    23.3 Power Network Analysis

current–voltage relations at the interface of the partitions (referred to as the macromodels), are
generated. A global simulation using only the macromodels is done to determine the interface
node voltages, and then individual partitions are solved using the interface voltages. This idea is
extendable to hierarchies deeper than two levels.
Figure 23.6 illustrates the idea of macromodeling. Assuming the network is partitioned into m
partitions and all the interface nodes are in partition 1 (called the global partition), then the linear
system in Equation 23.2 or 23.3 can be written in the following form:

é g11 g12 g13 ¼ g1m ù é v1 ù é i1 ù

ê g 21 g 22 úê ú ê ú
ê 0 ¼ 0 ú ê v2 ú ê i2 ú
(23.4) ê g 31 0 g 33  ú ê v3 ú = ê i3 ú
ê úê ú ê ú
ê     úê  ú ê  ú
ê g m1 0 ¼ ¼ g mm ú êvm ú êim ú
ë ûë û ë û

By eliminating the nodes of partitions 2 through m, one can reduce this equation to a system
containing only the global partition nodes:

(23.5) Av1 = i1 - S

Matrix A is the Schur complement of initial matrix with respect to g 11, and S is a vector of
currents at the interface nodes whose effect is the same as all the internal currents. A and S are
obtained from
m
(23.6) A = g11 - åg
k =2
1k
-1
g kk gk1

(23.7) S= åg
k =1
1k
-1
g kk ik

The hierarchical approach presents both memory and performance advantages due to parallelism.
Factoring of the gkk matrices and computation of contributions to A and S from the partitions
can be done in parallel. After solving the global system (Equation 23.5), the voltages of nodes
in the partitions can also be back-solved in parallel. The reduced matrix A is very dense, so in
situations when it is also very large, an iterative solver is more useful to solve the global partition
(Equation 23.5), while other partitions can be solved with a direct solver, thus utilizing a hybrid
solution approach overall. Needless to say, a good partitioning strategy minimizes the number of
interface nodes between partitions. Hypergraph partitioning utilities such as hMetis [31] can be
used to help achieve that goal.

Sparse
1 g11 g12 g13 g1m
4
g21 g22
. Dense
2 . g31 g33 A
.

gm1 gmm
3 m

FIGURE 23.6 Hierarchical analysis and matrix reduction.

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 Chapter 23 – Design and Analysis of Power Supply Networks    599

23.3.3 VECTORLESS ANALYSIS

The number of operational modes for which a chip must be verified is increasing due to wider
adoption of power gating, clock gating, dynamic voltage, frequency scaling, and other design
features. The complexity of power grid analysis is exacerbated by the need to carry out long
simulations with many current traces from functional vectors such that a chip’s various operat-
ing modes and input vector patterns are adequately covered [32]. However, simulation is never
exhaustive, and even limited simulation demands lots of resources. Moreover, vector-based
simulation is not appropriate for an incomplete and evolving design, where only partial information
about currents is available.
Techniques to determine maximum currents in a pattern-independent manner [33] or to
generate simulation vectors for maximum instantaneous currents [34] have been proposed.
One difficulty with vectors that maximize currents is that they do not necessarily maximize
IR drop or transient noise in the PDN. Artificial instruction sequences (known as power viruses
or smoke vectors) composed by a chip’s architects to target various high power modes and create
severe power transients may be the best inputs a power grid designer has for verification. Yet,
these may be excessively pessimistic leading to overdesign and may still miss some worst-case
power grid conditions. In view of these difficulties, providing guarantees as to the performance
of a power grid using vector-based simulation is nearly impossible.
The authors of [35] advanced the idea of vectorless PDN verification and proposed an approach
for determining the maximum static voltage drop at nodes of interest in a power network without
requiring exact current distributions, using only a set of constraints on the currents. This vectorless
approach is extended in [36,37] to determine worst-case transient power noise.
For the static case, when the local and global currents are constrained, the problem is solved
[35] as an optimization problem using linear programming. In practice, it is common to have
current constraints (viz., lower and upper bounds) on each circuit instance as a whole, whether
the instance is a leaf instance or a nonleaf instance. This is illustrated in Figure 23.7. In such
circumstances, the worst-case analysis can be very efficiently carried out using sensitivities of
node voltages to instance currents (known as adjoint sensitivities) and allocating the maximum
total current to individual instances in a systematic manner as per the sensitivities [5]:

k1 £ I A £ k2

k 3 £ I B1 , I B 2 £ k 4

k5 £ I B 3 £ k 6

k 7 £ IC 1 , IC 2 £ k8

B1 B2 B3

C1 C2

FIGURE 23.7 An example of hierarchical current constraints.

© 2016 by Taylor & Francis Group, LLC

600    23.3 Power Network Analysis

For the system GV = I, the (adjoint) sensitivity of voltage at node k, V k, to the current drawn
from node j, Ij, can be computed by solving the system with a unit current injected at node j and
no other currents and measuring the voltage V k. It is easy to see that the sensitivities of V k to
all the currents are really the entries in the kth column of the G−1 matrix and all dV k/dIj are
therefore obtained by solving the system once as

T
é dVk dVk dVk ù
ê dI ¼ ¼ = G -1ek T
ë 1 dI 2 dI n úû

In this, ek is a vector of zeroes except the kth entry, which is 1. The voltage drop at node k is

å
dVk
maximized by maximizing I j through allocation of node currents based on sensitivi-
j dI j
ties, subject to the current constraints. It is convenient to derive and use voltage-to-current
sensitivities between collections of nodes. Using the additive property of the node sensitivity, the
sensitivity of a node voltage to the total current of a block, bj, can be expressed as

åk
dVk dVk
= ji
dI bj i
dI i

where kji is the fraction of current of block j contributed to current at node i.

Likewise, if X is a collection of nodes (such as a collection of representative nodes from one or
more regions), the voltage sensitivity of that collection to a node current is the sum of sensitivities
of the nodes in the collection with appropriate weighting:

åµ
dVX dVi
= i
dI j i
dI j

Using these two collective sensitivities, worst-case analysis can be carried out targeting regions
or nodes of interest and such analysis would require only as many number of solutions of the
linear system as the number of nodes of interest.
Figure 23.8 illustrates the application of the worst-case analysis. It shows IR drop plots from
nine worst-case analyses of a PDN. Each analysis targeted one of the nine regions (marked by the
red square boxes in their respective graphs) that together cover the entire PDN. Approximately
50 nodes in each region, specified by the designer, were taken to represent each region. The volt-
age drops at these nodes were maximized with equal weights subject to the specified maximum
total current for the chip and the hierarchical current constraints as shown in Figure 23.7. In the
graphs, the voltage drops at the loads are plotted on a color scale spanning from the dark green
color (signifying the lowest drop) to the dark red color (signifying the highest drop).

23.3.4 INCREMENTAL ANALYSIS

In the course of a chip design, many corrections made to a power network may involve only
localized modifications while the bulk of the network is unchanged. Fast incremental analysis
techniques that can reuse much of the computations done in a previous full scale analysis
will help to reduce the design-analysis-design iteration time. They are useful for what-if
studies also.
When the changes affect very few circuit components, a large scale sensitivity method [38] can
be used to quickly compute the new solution. For N changes, this requires N forward–backward
substitutions using the original matrix factors, as well as solution of an N × N system. However, N
can be quite large (e.g., few millions) even for a modest change to the network. So, highly efficient
incremental methods are needed. The hierarchical analysis discussed in Section 23.3.3 inherently
has some incremental capability. When modifications are made in one of the partitions, the new
analysis can reuse the macromodels of the unmodified partitions. The random walk method for
power network analysis [25] is another method suited for incremental local updates. A hybrid

© 2016 by Taylor & Francis Group, LLC

 Chapter 23 – Design and Analysis of Power Supply Networks    601

FIGURE 23.8 Application of worst-case analysis.

(direct and iterative) approach proposed in [39], which is based on fictitious domains, provides
a very competitive method that can handle very large PDN modifications in an incremental
manner. Figure 23.9 illustrates the idea behind the method.
In the figure, R1 is the unmodified network, R2 is the region in the original network to be
modified, and R2* is the modified R2. The method solves three simpler problems P1, P2, and P3
iteratively. P1 solves the original network, but injecting at the interface between R1 and R2 a
fictitious current ΔI. The new voltages V at the interface are used to compute the currents enter-
ing R2* (in P2) and R2 (in P3). The difference in these currents, ΔI, is used in the next iteration
of P1. When V and ΔI do not change appreciably, the iterations have converged and the voltages
in P1 give the solution to the modified network. As only the currents change in P1, solving P1

R1

R2* R2
R2
I + ∆I I* I

P2 P3
P1

∆I = I *– I

FIGURE 23.9 Subproblems and iterative solution based on fictitious domain decomposition.

© 2016 by Taylor & Francis Group, LLC

602    23.4 Power Network Design

is accomplished through a forward and backward substitution. P2 and P3 solve only a fraction
of the original network and their solutions can be accelerated through a one-time factorization.
The convergence is improved by enlarging the modified region slightly to include a thin layer of
the unmodified region.

23.4 POWER NETWORK DESIGN

Invariably, all high-performance microprocessors (and most other chip designs) use a mesh grid
topology using multiple layers of metal interconnects for power distribution on the die. Some
high-performance designs have also used dense mesh power planes on some layers [40]. The
mesh topology is characterized by a very uniform footprint of power and ground wires that run
horizontally and vertically in alternate layers, with vias at their intersections. A mesh provides
advantages of very low resistance, a high degree of redundancy for failure, a highly uniform cur-
rent distribution, and ease of design and construction. A mesh can be specified by the layers it
spans and the width and spacing of wires in each layer. A mesh topology is used for both the global
(chip-level) distribution, as well as for local distributions within large circuit blocks, though with
different footprint parameters depending on the local loading.
Since many different power mesh configurations meet the specified IR drop criteria, it is
valuable to recognize the inherent strengths of certain configurations over others. At nanometer-
level scaling, the resistivity of metal wires is strongly influenced by the wire cross section. Very
slim wires suffer 30%–50% higher resistivity, due to scattering, dishing, and cladding, than wide
wires [41]. However, this consideration needs to be weighed appropriately with choices for wiring
pitches, especially for the lower-level routing layers, because densely pitched power/ground grid
wiring provides shielding or semishielding to a larger number of signal routes than a sparsely
pitched configuration.
The challenge in PDN design, besides its complexity, is that there are many unknowns until the
very end of the design cycle. Nevertheless, decisions about design parameters (viz., the number
of layers, widths, and pitches of wires), collateral inputs for package design (viz., the number and
placement of bumps or bond wires), and on-chip decoupling capacitance requirements have to
be made at very early stages, when a large part of the chip design has not even begun. Power grid
problems revealed at very late stages are usually very difficult and expensive to fix. A methodol-
ogy was presented in [42], which helps to design an initial power grid and refine it progressively
at various design stages. Needless to say, such a methodology will need a very flexible analysis
framework, providing tools and techniques for performing sign-off quality analysis, as well as
early and mid design stage analysis with approximate models of R, L, C and currents constructed
from incomplete design data.
Considering the risk that a bad power distribution poses to the success of a design project,
early power grid design decisions are made, understandably, in a very conservative manner in the
presence of many unknowns. When a previous generation of the design is available, many param-
eters of the new design are derived by scaling the old ones for the change in process technology,
operating voltage, frequency, and the (scaled) size of circuits in functional blocks. Layerwise,
wiring resources to be allocated for the PDN and the grid foot prints may be derived in this man-
ner. Alternatively, a uniform trial power mesh, down to the lowest metal layer, may be constructed,
iteratively refined through analysis, and used as the basis. For very early estimates, one could
make quick calculations using closed form expressions [43] assuming a uniform grid topology
and a uniform loading of the network. However, if nonuniformities need to be considered, a static
analysis can provide accurate estimates.
For the most part of the design cycle, static (DC) analysis in one of the modes (hierarchical,
vectorless, or incremental) serves as the workhorse for constructing and debugging PDN issues
based solely on IR drop targets, which are often padded to provide for transient noise, uncertain-
ties in current estimates, etc. The effort needed to run transient analysis (viz., extracting and
preparing the R, L, and C models for the on-chip and off-chip components, as well as the current
excitation traces) is very high and the run times for analysis are longer. In view of this, transient
analysis is often carried out with simplified models for the die network or the package, to assist
with package evaluation and decap placement.

© 2016 by Taylor & Francis Group, LLC

 Chapter 23 – Design and Analysis of Power Supply Networks    603

During early design phases, simpler 1-D models for resistances and area-based DC currents
suffice for static analysis. Likewise, per-pin or per-bump inductance estimates and area-based
decoupling estimates suffice for transient analysis. These models are to be refined and extracted
more accurately as the design progresses and reliable collateral data from completed parts of
the design become available. For valid results from analysis carried out on incomplete designs,
a designer will have to provide approximate models for the incomplete parts, and so it is very
important that the tool and flow is flexible enough to allow such usage models.
As noted in Section 23.2, many of the measures to guarantee reliable operation of the PDN
during power transients go beyond PDN design and span circuit, microarchitectural, power manage-
ment, and even software design. Circuit designs for voltage droop monitoring and adaptive clocking
provide droop-compensated clock periods to enable operating the chip at lower timing margin and
lower nominal Vdd [40,44]. Load lining is another technique where the VR module raises the sup-
ply voltage during low processor activity to provide voltage headroom for potential supply droops.
The transient noise issues are best addressed at the source by exercising control over operational
events causing abrupt changes in the magnitude of current drawn. Clock gating and fine-grained
DVFS induce high frequency noise that, to a certain extent, can be effectively handled by on-chip
decoupling capacitors. Excessive noise can be avoided by fine-tuning gating actions using mod-
ule decay counters or avoiding simultaneous gating using queue-based control mechanisms [45].
Voltage sensors can be used to detect noise emergencies and initiate appropriate control actions
such as power throttling. Analysis of software routines has been proposed to identify and correct
code sequences and loops causing voltage emergencies [46]. In essence, power saving and power
management actions need to be cognizant of the di/dt that will result from these actions [47].
Power gating is another potential source for severe di/dt issues if the design is not properly
done and verified. Fine-grained power gating [48] (shown in Figure 23.10) partitions a large cir-
cuit block into multiple clusters of logic gates and turns on and off these clusters individually.
Due to the finer control, this scheme has higher leakage power saving potential and also lends to
better control of di/dt.
Coarse-grained power gating (shown in Figure 23.11), on the other hand, turns on and off
an entire circuit block or a core, saves the state retention elements, and so is vulnerable to

Vdd _constant

Header switches
Controller

Logic Logic Logic

cluster 1 cluster 2 cluster N

FIGURE 23.10 Fine-grained power gating.

Vdd _constant

Controller τ τ τ
Vdd _const
Vdd _gated
Switches
Circuit Vdd _gated
block Block
switches

FIGURE 23.11 Coarse-grained power gating.

© 2016 by Taylor & Francis Group, LLC

604    23.5 Conclusions

severe di/dt issues. Modular switches (typically PMOS devices) are arranged in arrays and
controlled by delay chains so that the block can be powered up or down gradually. The number
of switch modules needed is determined by the IR drop caused by the switches when they are
ON and the speed at which the module needs to be powered on. The delay elements in the
chain and the driver strength of the controller determine the operating point on the trade-off
between power-on speed and in-rush current (or transient noise). Simulation for power-up or
power-down analysis needs to include nonlinear active devices of the sensing and controller
circuits, and a simplified RC model of the powered network is helpful in reducing the simula-
tion run time [5].

23.5 CONCLUSIONS

Design and verification of the power supply and distribution systems are critical tasks in the
design of integrated chip systems since power supply integrity issues have dire consequences.
We presented various analysis techniques for verifying and optimizing the PDN at different
design stages. A linear system solution, which forms the core of power grid simulation, was
discussed, highlighting the complexity of the problem and presenting popular approaches
for different types of analysis. It was emphasized that while static voltage drop issues can be
addressed with adequate layout resources, dynamic noise issues arising from power transient
events demand much engineering effort. All stages of chip design, from architecture to circuit
and physical implementation, need to be cognizant of these issues in order to avoid them or to put
in place adequate mechanisms to control them. With further reduction in the supply voltage due
to process scaling and increasing architectural complexity of processors, PDN noise issues will
continue to demand significant design and verification effort.

ACKNOWLEDGMENTS

Thanks to Oracle’s Tom Dillinger, Bob Masleid, and Alexander Korobkov for reviewing this
chapter and making several suggestions to improve the contents and the presentation.

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