CE 2704 - Digital Logic Design

Dr. Ehsan Ali

Assumption University of Thailand
ehsanali@au.edu

Semester 2/2024
Contents

1 Module 5 - MSI Logic 2

1.0.1 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Example: One-Hot Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.2 Example: 7-Segment Display Decoder . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 Example: One-Hot Binary Encoder . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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Chapter 1

Module 5 - MSI Logic

This week lecture notes introduce a group of combinational logic building blocks that are commonly
used in digital design. As we move into systems that are larger than individual gates, there are naming
conventions that are used to describe the size of the logic. Table 1.1 gives these naming conventions. In
this week, we will look at Medium-Scale Integrated (MSI) circuit logic. Each of these building blocks
can be implemented using the combinational logic design steps covered in Week 2 and 3. The goal of
this week is to provide an understanding of the basic principles of MSI logic.

Name Example # of Transistors

SSI - Small Scale Integrated Circuits Individual Gates (NAND, INV) 10’s
MSI - Medium Scale Integrated Circuits Decoders, Multiplexers 100’s
LSI — Large Scale Integrated Circuits Arithmetic Circuits, RAM 1k 10k
VLSI - Very Large Scale Integrated Circuits Microprocessors 100k - 1M
Table 1.1: Naming convention for the size of digital systems.

While there are names for logic sizes above 1M transistor such as ULSI (Ultra), the term "VLSI"
is now used to describe all integrated circuits that are so large they require CAD tools for their design,
synthesis and implementation.

1.0.1 Learning Outcomes

• Design a decoder circuit using both the classical digital design approach and the modern HDL-
based approach.
• Design an encoder circuit using both the classical digital design approach and the modern HDL-
based approach.
• Design a multiplexer circuit using both the classical digital design approach and the modern HDL-
based approach.
• Design a demultiplexer circuit using both the classical digital design approach and the modern
HDL-based approach.

1.1 Decoders
A decoder is a circuit that takes in a binary code and has outputs that are asserted for specific values of
that code. The code can be of any type or size (e.g., unsigned, two’s complement, etc.). Each output will

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assert for only specific input codes. Since combinational logic circuits only produce a single output, this
means that within a decoder, there will be a separate combinational logic circuit for each output.

1.1.1 Example: One-Hot Decoder

A one-hot decoder is a circuit that has n inputs and 2n outputs. Each output will assert for one and only
one input code. Since there are 2n outputs, there will always be one and only one output asserted at any
given time. Example in Fig. 1.1 shows the process of designing a 2-to-4 one-hot decoder by hand (i.e.,
using the classical digital design approach).

Figure 1.1: 2-to-4 one-hot decoder: logic synthesis by hand.

As decoders get larger, it is necessary to use hardware description languages to model their behavior.

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 Example in Fig. 1.2 shows how to model a 3-to-8 one-hot decoder. The Verilog source code with
continuous assignment and logic operators are shown after that in Listing 1.1.

Figure 1.2: 3-to-8 one-hot decoder.

Listing 1.1: 3-to-8 one-hot decoder: Verilog modeling using logical operators.
1 module d e c o d e r _ l h o t _ 3 t o 8
2 ( o u t p u t w i r e F0 , Fl , F2 , F3 , F4 , F5 , F6 , F7 ,
3 i n p u t w i r e A, B , C ) ;
4

5 assign F0 = ~A & ~B & ~C ;

6 assign Fl = ~A & ~B & C;
7 assign F2 = ~A & B & ~C ;
8 assign F3 = ~A & B & C;
9 assign F4 = A & ~B & ~C ;
10 assign F5 = A & ~B & C;
11 assign F6 = A & B & ~C ;
12 assign F7 = A & B & C;
13

14 endmodule
This description can be further simplified by using vector notation for the ports and describing the
functionality using conditional operators. Example in Fig. 1.3 shows how to model the 3-to-8 one-hot
decoder in Verilog using continuous assignment with conditional operators.

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 Figure 1.3: 3-to-8 one-hot decoder (version 2).

Listing 1.2: 3-to-8 one-hot decoder: Verilog modeling using conditional operators (version 2).
1 module d e c o d e r _ l h o t _ 3 t o 8 (
2 output wire [ 7 : 0 ] F ,
3 i n p u t w i r e [ 2 : 0 ] ABC) ;
4

5 a s s i g n F = (ABC == 3 ’ b000 ) ? 8 ’ b0000_0001 :

6 (ABC == 3 ’ b001 ) ? 8 ’ b0000_0010 :
7 (ABC == 3 ’ b010 ) ? 8 ’ b0000_0100 :
8 (ABC == 3 ’ b011 ) ? 8 ’ b0000_1000 :
9 (ABC == 3 ’ b100 ) ? 8 ’ b0001_0000 :
10 (ABC == 3 ’ b101 ) ? 8 ’ b0010_0000 :
11 (ABC == 3 ’ b110 ) ? 8 ’ b0100_0000 :
12 (ABC == 3 ’ b l 1 l ) ? 8 ’ b1000_0000 :
13 8 ’bXXXX_XXXX;
14 endmodule

1.1.2 Example: 7-Segment Display Decoder

A 7-segment display decoder is a circuit used to drive character displays that are commonly found in
applications such as digital clocks and household appliances. A character display is made up of seven
individual LEDs, typically labeled a-g. The input to the decoder is the binary equivalent of the decimal
or Hex character that is to be displayed. The output of the decoder is the arrangement of LEDs that will
form the character. Decoders with 2-inputs can drive characters "0" to "3." Decoders with 3-inputs can
drive characters "0" to "7." Decoders with 4-inputs can drive characters "0" to "F" with the case of the
Hex characters being "A, b, c or C, d, E and F."
Let’s look at an example of how to design a 3-input, 7-segment decoder by hand. The first step in the
process is to create the truth table for the outputs that will drive the LEDs in the display. We’ll call these
outputs Fa , Fb , ..., Fg . Fig. 1.4 shows how to construct the truth table for the 7-segment display decoder.
In this table, a logic 1 corresponds to the LED being ON.

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 Figure 1.4: 7-Segment display decoder: truth table.

If we wish to design this decoder by hand, we need to create seven separate combinational logic
circuits. Each of the outputs (Fa - Fg ) can be put into a 3-input K-map to find the minimized logic
expression. Example in Fig 1.5 shows the design of the decoder from the truth table in Fig 1.4 by hand.

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 Figure 1.5: 7-Segment display decoder: logic synthesis by hand.

This same functionality can be implemented in Verilog using concurrent modeling techniques. List-
ing 1.3 shows how to model the 7-segment decoder shown in Fig. 1.6 in Verilog using continuous

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 assignment with logic operators.

Figure 1.6: 7-Segment display decoder.

Listing 1.3: 7-Segment display decoder: Verilog modeling using logical operators.
1 module d e c o d e r _ 7 s e g ( o u t p u t w i r e Fa , Fb , Fe , Fd , Fe , Ff , Fg ,
2 i n p u t w i r e A, B , C ) ;
3

4 assign Fa = ( ~A & ~C ) | ( B ) | (A & C ) ;

5 assign Fb = ( ~B & ~C ) | ( ~A) | ( B & C ) ;
6 assign Fc = (A) | ( ~B ) | (C) ;
7 assign Fd = ( ~A & ~C ) | ( ~A & B ) | ( B & ~C ) | (A & ~B & C ) ;
8 assign Fe = ( ~A & ~C ) | ( B & ~C ) ;
9 assign Ff = ( ~B & ~C ) | (A & ~C ) | (A & ~B ) ;
10 assign Fg = ( ~A & B) | (A & ~C ) | (A & ~B ) |
11

12 endmodule
Again, a more compact description of the decoder can be accomplished if the ports are described
as vectors and a conditional operator is used. Listing 1.4 shows how to model the 7-segment decoder
showns in Fig. 1.7 in Verilog using continuous assignment with conditional operators.

Figure 1.7: 7-Segment display decoder (Version 2).

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 Listing 1.4: 7-Segment display decoder (Version 2): Verilog modeling using conditional operators.
1 module d e c o d e r _ 7 s e g ( o u t p u t w i r e [ 6 : 0 ] F ,
2 i n p u t w i r e [ 2 : 0 ] ABC) ;
3

4 a s s i g n F = (ABC == 3 ’ b000 ) ? 7 ’ b111_1110 :

5 (ABC == 3 ’ b001 ) ? 7 ’ b011_0000 :
6 (ABC == 3 ’ b010 ) ? 7 ’ b110_1101 :
7 (ABC == 3 ’ b011 ) ? 7 ’ b111_1001 :
8 (ABC == 3 ’ b100 ) ? 7 ’ b011_0011 :
9 (ABC == 3 ’ b101 ) ? 7 ’ b101_1011 :
10 (ABC == 3 ’ b110 ) ? 7 ’ b101_1111 :
11 (ABC == 3 ’ b111 ) ? 7 ’ b111_0000 :
12 7 ’bXXXX_XXXX;
13 endmodule
In-class Question 1: In a decoder, a logic expression is created for each output. Once all of the output
logic expressions are found, how can the decoder logic be further minimized?

A) By using K-maps to find the output logic expressions.

B) By buffering the inputs so that they can drive a large number of other gates.

C) By identifying any logic terms that are used in multiple locations (inversions, product terms, and
sum terms) and sharing the interim results among multiple circuits in the decoder.

D) By ignoring fan-out.

1.2 Encoders
An encoder works in the opposite manner as a decoder. An assertion on a specific input port corresponds
to a unique code on the output port.

1.2.1 Example: One-Hot Binary Encoder

A one-hot binary encoder has n outputs and 2n inputs. The output will be an n-bit, binary code which
corresponds to an assertion on one and only one of the inputs. Example in Fig. 1.8 shows the process of
designing a 4-to-2 binary encoder by hand (i.e., using the classical digital design approach).

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 Figure 1.8: 4-to-2 binary encoder: logic synthesis by hand.

In Verilog, an encoder can be implemented using continuous assignment with either logical or con-
ditional operators. Listing 1.5 shows how to model the encoder in Fig. 1.9 in Verilog using these
techniques.

Figure 1.9: 4-to-2 binary encoders.

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 Listing 1.5: 4-to-2 binary encoder: Verilog modeling using logical and conditional operators.
1 / / (1) Logical operators
2 module e n c o d e r _ 1 h o t _ 4 t o 2 ( o u t p u t w i r e [ 1 : 0 ] YZ ,
3 i n p u t w i r e [ 3 : 0 ] ABCD) ;
4

5 a s s i g n YZ [ 1 ] = ABCD[ 3 ] | ABCD [ 2 ] ;
6 a s s i g n YZ [ 1 ] = ABCD[ 3 ] | ABCD [ 1 ] ;
7

8 endmodule
9

10 / / (2) Conditional operators

11 module e n c o d e r _ 1 h o t _ 4 t o 2 ( o u t p u t w i r e [ 1 : 0 ] YZ ,
12 i n p u t w i r e [ 3 : 0 ] ABCD) ;
13

14 a s s i g n YZ = (ABCD == 4 ’ b0001 ) ? 2 ’ b00 :

15 (ABCD == 4 ’ b0010 ) ? 2 ’ b01 :
16 (ABCD == 4 ’ b0100 ) ? 2 ’ b10 :
17 (ABCD == 4 ’ b1000 ) ? 2 ’ b11 :
18 2 ’bXX ;
19

20 endmodule
In-class Question 2: If it is desired to have the outputs of an encoder produce 0’s for all input codes
not defined in the truth table, can “don’t cares” be used when deriving the minimized logic expressions?
Why?

A) No. Don’t cares aren’t used in encoders.

B) Yes. Don’t cares can always be used in K-maps.

C) Yes. All that needs to be done is to treat each X as a 0 when forming the most minimal prime
implicant.

D) No. Each cell in the K-map corresponding to an undefined input code needs to contain a 0 so don’t
cares are not applicable.

1.3 Multiplexers
A multiplexer is a circuit that passes one of its multiple inputs to a single output based on a select input.
This can be thought of as a digital switch. The multiplexer has n select lines, 2n inputs, and one output.
Example 6.10 shows the process of designing a 2-to-1 multiplexer by hand (i.e., using the classical digital
design approach).

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 Figure 1.10: 2-to-1 multiplexer: logic synthesis by hand.

In Verilog, a multiplexer can be implemented using continuous assignment with either logical or
conditional operators. Listing 1.7 shows how to model the multiplexer in Fig 1.11 in Verilog using these
techniques.

Figure 1.11: 4-to-1 multiplexer.

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 Listing 1.6: 4-to-1 multiplexer: Verilog modeling using logical and conditional operators.
1 / / (1) Logical operators
2 module mux_4to1 ( o u t p u t w i r e F ,
3 i n p u t w i r e A, B , C , D,
4 input wire [ 1 : 0 ] Sel ) ;
5

6 a s s i g n F = (A & ~Sel [1] & ~Sel [0]) |

7 (B & ~Sel [1] & Sel [0]) |
8 (C & Sel [1] & ~Sel [0]) |
9 (D & Sel [1] & Sel [0]) ;
10 endmodule
11

12 / / (2) Conditional operators

13 module mux_4to1 ( o u t p u t w i r e F ,
14 i n p u t w i r e A, B , C , D,
15 input wire [ 1 : 0 ] Sel ) ;
16

17 a s s i g n F = ( S e l == 2 ’ b00 ) ? A :
18 ( S e l == 2 ’ b01 ) ? B :
19 ( S e l == 2 ’ b10 ) ? C :
20 ( S e l == 2 ’ b11 ) ? D :
21 1 ’bX ;
22 endmodule
In-class Question 3: How are the product terms in a multiplexer based on the identity theorem?

A) Only the select product term will pass its input to the final sum term. Since all of the unselected
product terms output 0, the input will be passed through the sum term because anything OR’d with
a 0 is itself.

B) The select lines are complemented such that they activate only one OR gate.

C) The select line inputs will produce 1’s on the inputs of the selected product term. This allows the
input signal to pass through the selected AND gate because anything AND’d with a 1 is itself.

D) The select line inputs will produce 0’s on the inputs of the selected sum term. This allows the input
signal to pass through the selected OR gate because anything OR’d with a 0 is itself.

1.4 Demultiplexers
A demultiplexer works in a complementary fashion to a multiplexer. A demultiplexer has one input that
is routed to one of its multiple outputs. The output that is active is dictated by a select input. A demux
has n select lines that chooses to route the input to one of its 2n outputs. When an output is not selected,
it outputs a logic 0. Example 6.12 shows the process of designing a 1-to-2 demultiplexer by hand (i.e.,
using the classical digital design approach).

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 Figure 1.12: 1-to-2 demultiplexer: logic synthesis by hand.

In Verilog, a demultiplexer can be implemented using continuous assignment with either logical
or conditional operators. Example 6.13 shows how to model the demultiplexer in Verilog using these
techniques.

Figure 1.13: 1-to-4 demultiplexer.

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 Listing 1.7: 4-to-1 multiplexer: Verilog modeling using logical and conditional operators.
1 / / (1) Logical operators
2 module demux_1to4 ( o u t p u t w i r e W, X, Y, Z ,
3 i n p u t w i r e A,
4 input wire [ 1 : 0 ] Sel ) ;
5

6 assign W = (A & ~Sel [1] & ~Sel [0]) ;

7 assign X = (A & ~Sel [1] & Sel [0]) ;
8 assign Y = (A & Sel [1] & ~Sel [0]) ;
9 assign Z = (A & Sel [1] & Sel [0]) ;
10

11 endmodule
12

13 / / (2) Conditional operators

14 module demux_1to4 ( o u t p u t w i r e W, X, Y, Z ,
15 i n p u t w i r e A,
16 input wire [ 1 : 0 ] Sel ) ;
17

18 assign W = ( Sel == 2 ’ b00 ) ? A : 1 ’ b0 ;

19 assign X = ( Sel == 2 ’ b01 ) ? A : 1 ’ b0 ;
20 assign Y = ( Sel == 2 ’ b10 ) ? A : 1 ’ b0 ;
21 assign Z = ( Sel == 2 ’ b11 ) ? A : 1 ’ b0 ;
22

23 endmodule
In-class Question 4: How many select lines are needed in a 1-to-64 demultiplexer?

A) 1

B) 4

C) 6

D) 64

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1.5 Assignments
1. Design a 4-to-16 one-hot decoder by hand. The block diagram and truth table for the decoder are
given below. Give the minimized logic expressions for each output (i.e., F0 , F1 ,... , F15 ) and the
full logic diagram for the system.

2. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and gate-
level primitives. Use the module port definition given in Listing. 1.8 and submit your functional
simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Listing 1.8: decoder_1hot_4to16.v
1 module d e c o d e r _ 1 h o t _ 4 t o 1 6 ( o u t p u t w i r e [ 1 5 : 0 ] F ,
2 i n p u t w i r e [ 3 : 0 ] ABCD) ;
3

4 / / Your d e s i g n g o e s h e r e
5

6 endmodule

3. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and logical
operators. Use the module port definition given in Listing. the module port definition given in
Listing. 1.8 and submit your functional simulation waveform obtained from Xilinx ISE 14.7 that
ensures your design is correct.

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4. Design a Verilog model for a 4-to-16 one-hot decoder using continuous assignment and condi-
tional operators. Use the module port definition given in Listing. 1.8 and submit your functional
simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

5. Design a 4-input, 7-segment HEX character decoder by hand. The system has four inputs called
A, B, C, and D. The system has seven outputs called Fa , Fb , Fc , Fd , Fe , Ff , and Fg . These
outputs drive the individual LEDs within the display. A logic 1 on an output corresponds to the
LED being ON. The display will show the HEX characters 0-9, A, b, c, d, E, and F corresponding
to the 4-bit input code on A. A template for creating the truth tables for this system is provided in
Fig. 1.14. Provide the minimized logic expressions for each of the seven outputs and the overall
logic diagram for the decoder.

Figure 1.14: Question 5.

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6. Design a Verilog model for a 4-input, 7-segment HEX character decoder using continuous assign-
ment and logical operators. Use the module port definition given in Listing 1.9 for your design
and submit your functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your
design is correct. The system has a 4-bit input vector called ABCD and a 7-bit output vector called
F. The individual scalars within the output vector (i.e., F[6:0]) correspond to the character
display segments a, b, c, d, e, f, and g, respectively. A logic 1 on an output corresponds to the
LED being ON. The display will show the HEX characters 0-9, A, b, c, d, E, and F corresponding
to the 4-bit input code on A. A template for creating the truth table is provided in Fig. 1.14. The
signals in this table correspond to the ports in this problem as follows: Fa = F(6), Fb = F(5), Fc =
F(4), Fd = F(3), Fe = F(2), Ff = F(1), and Fg = F(0).
Listing 1.9: decoder_7seg_4in.v
1 module d e c o d e r _ 7 s e g _ 4 i n ( o u t p u t w i r e [ 6 : 0 ] F ,
2 i n p u t w i r e [ 3 : 0 ] ABCD) ;
3

4 / / Your d e s i g n g o e s h e r e
5

6 endmodule

7. Design an 8-to-3 binary encoder by hand. The block diagram and truth table for the encoder are
given in Fig. 1.15. Give the logic expressions for each output and the full logic diagram for the
system.

Figure 1.15: Question 7.

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 8. Design a Verilog model for an 8-to-3 binary encoder using continuous assignment and gate-level
primitives. Use the module port definition given in Listing 1.10 and submit your functional simu-
lation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Listing 1.10: encoder_8to3_binary.v
1 module e n c o d e r _ 8 t o 3 _ b i n a r y ( o u t p u t w i r e [ 2 : 0 ] F ,
2 i n p u t w i r e [ 7 : 0 ] A) ;
3

4 / / Your d e s i g n g o e s h e r e
5

6 endmodule

9. Design a Verilog model for an 8-to-3 binary encoder continuous assignment and logical opera-
tors. Use the module port definition given in Listing 1.10 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

10. Design a Verilog model for an 8-to-3 binary encoder continuous assignment and conditional oper-
ators. Use the module port definition given in Listing 1.10 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

11. Design an 8-to-1 multiplexer by hand. The block diagram and truth table for the multiplexer are
given in Fig. 1.16 Give the minimized logic expressions for the output and the full logic diagram
for the system.

Figure 1.16: Question 11.

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12. Design a Verilog model for an 8-to-1 multiplexer using continuous assignment and gate-level prim-
itives. Use the module port definition given in Listing 1.11 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.
Listing 1.11: mux_8to1.v
1 module mux_8to1 ( o u t p u t w i r e [ 7 : 0 ] A,
2 i n p u t wire [ 2 : 0 ] Sel ,
3 output wire F) ;
4

5 / / Your d e s i g n g o e s h e r e
6

7 endmodule

13. Design a Verilog model for an 8-to-1 multiplexer continuous assignment and logical operators. Use
the module port definition given in Listing 1.11 and submit your functional simulation waveform
obtained from Xilinx ISE 14.7 that ensures your design is correct.

14. Design a Verilog model for an 8-to-1 multiplexer continuous assignment and conditional opera-
tors. Use the module port definition given in Listing 1.11 and submit your functional simulation
waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

15. Design a 1-to-8 demultiplexer by hand. The block diagram and truth table for the demultiplexer
are given in Fig. 1.17. Give the minimized logic expressions for each output and the full logic
diagram for the system.

Figure 1.17: Question 15.

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16. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and gate-level
primitives. Use the module port definition given in Listing 1.12 for your design.
Listing 1.12: demux_1to8.v
1 module demux_1to8 ( o u t p u t w i r e [ 7 : 0 ] F ,
2 i n p u t w i r e A,
3 input wire [ 2 : 0 ] Sel ) ;
4

5 / / Your d e s i g n g o e s h e r e
6

7 endmodule

17. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and logical op-
erators. Use the module port definition given in Listing 1.12 for your design and submit your
functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

18. Design a Verilog model for a 1-to-8 demultiplexer using continuous assignment and conditional
operators. Use the module port definition given in Listing 1.12 for your design and submit your
functional simulation waveform obtained from Xilinx ISE 14.7 that ensures your design is correct.

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