MICRO-PROCESSOR AND

MICROCONTROLLERS
(EC1506)

DR. Jayendra Kumar

Deptt. Of ECE, NIT Jamshedpur
1
Introduction to Microprocessors
• Definition:

Microprocessor is the controlling unit or CPU

of a micro-computer, fabricated on a very
small chip capable of performing arithmetic
and logical operations and communicating
with the external devices connected to it.

2
 A Computer
• A computer:
– Accepts the data from the user.
– Stores the data and the set of instructions
supplied by the user in memory.
– Processes the data according to the
instructions in the processing unit.
– Communicates the result to the user or stores
it for further reference.

3
 A Computer
• A computer has the
following units:
– Input Unit
– Output Unit
– Memory Unit
– Central Processing Unit

4
 A Computer
• ARITHMETIC AND LOGIC UNIT (ALU)
– This unit perform all the logical and arithmetic operations.
– Various arithmetic operations are: addition, subtraction,
increment and decrement etc.
– Various logical operations are: AND, OR, NOT, XOR, etc.
• TIMING AND CONTROL UNIT
– This unit controls the entire operations being performed by
the system.
– It controls the operations of ALU, input/output devices and
memory unit.
– This unit interprets the instructions and generates various
timing and control signals.
• REGISTERS
– A register is a very small amount of very fast memory that is
built into the CPU in order to store the current data and
instructions which are being executed by the CPU.

5
 A Computer
• MEMORY UNIT
– It stores the program statement and the data i.e.
the information supplied from the input unit.
– It also stores the final output.
– This is connected to the CPU by means of a
bidirectional bus.
– The CPU processes the information as taken
from the memory and performs the operations
in the ALU section.
– The results are either transferred to the output
unit or stored in the memory for later use by the
CPU.

6
 A Micro-Computer
• As the name implies, microcomputers are
small computers.
• The block diagram of the microcomputer
is similar to the computer except that the
central processing unit of the
microcomputer is contained in a single IC
called the microprocessor.

7
 A Micro-Computer
• A microprocessor is a LSI (Large Scale Integration)
IC that does almost all the functions of the CPU.
• It is also defined as a CPU contained in a single chip.
• The basic function of the microprocessor is:
– to fetch the instructions stored in the main memory
– identify the operations and the devices involved in it
– and accordingly generate control signals to determine
when a given action is to take place.
• We can say that a computer with a microprocessor
as its CPU, is known as Microcomputer.

8
 Some Definitions
• Microprocessor:
– The central processing unit built on a single IC
is called Microprocessor.
– A microprocessor (sometimes abbreviated as
µP) is a digital electronic component with
miniaturized transistors on a single
semiconductor integrated circuit (IC).
– One or more microprocessors typically serve
as a central processing unit (CPU) in a
computer system or handheld device.

9
10
Microprocessor Characteristics
• Instruction Set:
– The set of instructions that a microprocessor can
understand.

• Bandwidth:
– The number of bits processed in a single instruction.

• Capability:
– It depends upon the number of instructions and
capability of each instruction.

11
Microprocessor Characteristics
• Clock Speed:
– The clock speed determines how many operations
per second the processor can perform.
– It is also called Clock Rate.
– Every computer contains an internal clock that
regulates the rate at which instructions are executed
and synchronizes the various computer components.
– The faster the clock, the more instructions the CPU
can execute per second.
– Clock speeds are expressed in megahertz (MHz) or
gigahertz (GHz).
– The microprocessors of personal computers have
clock speeds of anywhere from 300 MHz to over 3.8
GHz.
12
Microprocessor Characteristics
• Word Length:
– It depends upon the width of internal data bus,
registers, ALU etc.
– An 8-bit microprocessor can process 8 bit data
at a time.
– A processor with longer word length is more
powerful and can process data at a faster
speed as compared to processor with shorter
word length.
– The word length ranges from 4 bits for small
microprocessor, to 64 bits for high-end
microcomputers.
13
Microprocessor Characteristics
• Width of Data Bus:
– This is the size of the data bus. It defines the number of bits
that can be transferred through data bus.

• Width of Address Bus:

– This parameter decides the memory addressing capability
of the microprocessor. The maximum size of the memory
unit is decided by this parameter.

• Input/Output Addressing Capability:

– The maximum number of the input/output ports accessed
by the microprocessor depends upon the width of the
input/output address provided in the input/output
instruction.

14
Microprocessor Characteristics
• Data Types:
– The microprocessor handles various types of
data formats like binary, BCD, ASCII, signed and
unsigned numbers.

• Interrupt Capability:
– Interrupts are used to handle unpredictable and
random events in the microcomputer.
– It is used to interrupt the microprocessor.
– Interrupt driven input/output improves the
throughput of a system.

15
 Features of Microprocessor
• Cost:
– The most important feature of a microcomputer is its low
cost.
– Because of the widespread use of microprocessors, the
volume of production is very high.
– That is why, microprocessor chips are available at fairly low
prices.

• Size:
– The second important feature of a microprocessor is its
small size.
– As a result of improvement in fabrication technology, VLSI,
electronic circuitry has become so dense that a minute
silicon chip can contain hundred and thousands of
transistors.

16
 Features of Microprocessor
• Power Consumption:
– Another important feature is its low power consumption.
– Microprocessors are normally manufactured by Metal-
Oxide semiconductor technology, which has the feature of
low power consumption.
• Versatility:
– The microprocessors are versatile.
– Keeping the same basic hardware, a microprocessor-based
system can be configured for a number of applications by
simply altering the software program.
• Reliability:
– Another important property of microprocessors is its
extreme reliability.
– It has been established that the failure rate of an IC is fairly
uniform at the package level, regardless of its complexity.

17
 Micron
• A unit of length equal to one millionth of a meter.
• It is denoted by µ (Mu).
• For Example:
– If we pluck a hair from the head, it is very thin.
– But a hair is more than 2000 times wider than a
transistor on a microprocessor.
– Wires between transistors are even thinner.
– They're more than 4000 times thinner than a hair.
– A hair is about 100 microns in diameter.
– That means, a transistor is just 0.045 microns wide.

18
SYSTEM BUS
 System Bus
The CPU sends various data values,
instructions and information to all the devices
and components inside the computer.
If you look at the bottom of a motherboard
you'll see a whole network of lines or
electronic pathways that join the different
components together.
This network of wires or electronic pathways
is called the 'Bus'.

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Bottom of Motherboard

Syste
m Bus

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 Types of System Buses

• Data Bus
• Address Bus
• Control Bus

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 Data Bus
A collection of wires through which data is
transmitted from one part of a computer to
another is called Data Bus.
Data Bus can be thought of as a highway
on which data travels within a computer.
This bus connects all the computer
components to the CPU and main memory.

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 Data Bus
The size (width) of bus determines how
much data can be transmitted at one time.
E.g.:
A 16-bit bus can transmit 16 bits of data at a
time.
32-bit bus can transmit 32 bits at a time.

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 Address Bus
A collection of wires used to identify
particular location in main memory is
called Address Bus.
Or in other words, the information used to
describe the memory locations travels
along the address bus.

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 Address Bus
The size of address bus determines how
many unique memory locations can be
addressed.
E.g.:
A system with 4-bit address bus can address 24
= 16 Bytes of memory.
A system with 16-bit address bus can address
216 = 64 KB of memory.
A system with 20-bit address bus can address
220 = 1 MB of memory.
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 Control Bus
The connections that carry control
information between the CPU and other
devices within the computer is called Control
Bus.
The control bus carries signals that report the
status of various devices.
E.g.:
This bus is used to indicate whether the CPU is
reading from memory or writing to memory.

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 Introduction to 8085
 It was introduced in 1977.
 It is 8-bit microprocessor.
 Its actual name is 8085 A.
 It is single NMOS device.
 It contains 6200
transistors approx.
 Its dimensions are
164 mm x 222 mm.
 It is having 40 pins Dual-
Inline-Package (DIP).
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 Introduction to 8085
• It has three advanced
versions:
◦ 8085 AH
◦ 8085 AH2
◦ 8085 AH1

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 Introduction to 8085
• The advanced versions
consume 20% less
power supply.

• The clock frequencies

of 8085 are:
◦ 8085 A 3 MHz
◦ 8085 AH 3 MHz
◦ 8085 AH25 MHz
◦ 8085 AH16 MHz

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 Block Diagram of 8085

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 Three Units of 8085

• Processing Unit

• Instruction Unit

• Storage and Interface Unit

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 Processing Unit

• Arithmetic and Logic Unit

• Accumulator
• Status Flags
• Temporary Register

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 Instruction Unit

• Instruction Register
• Instruction Decoder
• Timing and Control Unit

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 Storage and Interface Unit

• General Purpose Registers

• Stack Pointer
• Program Counter
• Increment/Decrement Register
• Address Latch
• Address/Data Latch

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 Three Other Units

• Interrupt Controller
• Serial I/O Controller
• Power Supply

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 Accumulator

• It the main register of microprocessor.

• It is also called register ‘A’.
• It is an 8-bit register.
• It is used in the arithmetic and logic operations.
• It always contains one of the operands on which
arithmetic/logic has to be performed.
• After the arithmetic/logic operation, the contents
of accumulator are replaced by the result.
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 Arithmetic & Logic Unit (ALU)
• It performs various arithmetic and logic
operations.
• The data is available in accumulator and
temporary/general purpose registers.
• Arithmetic Operations:
– Addition, Subtraction, Increment, Decrement etc.
• Logic Operations:
– AND, OR, X-OR, Complement etc.

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 Temporary Register

• It is an 8-bit register.
• It is used to store temporary 8-bit operand
from general purpose register.
• It is also used to store intermediate
results.

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 Status Flags

• Status Flags are set of flip-flops which are

used to check the status of Accumulator
after the operation is performed.

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 Status Flags

• S=Sign Flag
• Z=Zero Flag
• AC =Auxiliary Carry Flag
• P =Parity Flag
• CY =Carry Flag
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 Status Flags

• Sign Flag (S):

– It tells the sign of result stored in Accumulator
after the operation is performed.

– If result is –ve, sign flag is set (1).

– If result is +ve, sign flag is reset (0).

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 Status Flags

• Zero Flag (Z):

– It tells whether the result stored in
Accumulator is zero or not after the operation
is performed.

– If result is zero, zero flag is set (1).

– If result is not zero, zero flag is reset (0).

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 Status Flags

• Auxiliary Carry Flag (AC):

– It is used in BCD operations.
– When there is carry in BCD addition, we add
0110 (6) to the result.
– If there is carry in BCD addition, auxiliary carry
is set (1).
– If there is no carry, auxiliary carry is reset (0).

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 Status Flags

• Parity Flag (P):

– It tells the parity of data stored in Accumulator.

– If parity is even, parity flag is set (1).

– If parity is odd, parity flag is reset (0).

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 Program Status Word (PSW)
• The contents of Accumulator and Status
Flags clubbed together is known as
Program Status Word (PSW).
• It is a 16-bit word.

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 Instruction Register

• It is used to hold the current instruction

which the microprocessor is about to
execute.
• It is an 8-bit register.

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 Instruction Decoder

• It interprets the instruction stored in

instruction register.
• It generates various machine cycles
depending upon the instruction.
• The machine cycles are then given to the
Timing and Control Unit.
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 Timing and Control Unit

• It controls all the operations of

microprocessor and peripheral devices.
• Depending upon the machine cycles received
from Instruction Decoder, it generates 12
control signals:
– S0 and S1 (Status Signals).
– ALE (Address Latch Enable).

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 Timing and Control Unit
– RD (Read, active low).
– WR (Write, active low).
– IO/M (Input-Output/Memory).
– READY
– RESET IN
– RESET OUT
– CLK OUT
– HOLD and HLDA
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 General Purpose Registers

• There are 6 general purpose registers, namely B, C, D, E, H,

L.
• Each of the them is 8-bit register.
• They are used to hold data and results.
• To hold 16-bit data, combination of two 8-bit registers can
be used.
• This combination is known as Register Pair.
• The valid register pairs are:
– B – C, D – E, H – L.

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 Program Counter

• It is used to hold the address of next

instruction to be executed.
• It is a 16-bit register.
• The microprocessor increments the value
of Program Counter after the execution of
the current instruction, so that, it always
points to the next instruction.
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 Stack Pointer

• It holds the address of top most item in

the stack.
• It is also 16-bit register.
• Any portion of memory can be used as
stack.

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 Increment/Decrement Register

• This register is used to increment or

decrement the value of Stack Pointer.
• During PUSH operation, the value of Stack
Pointer is incremented.
• During POP operation, the value of Stack
Pointer is decremented.
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 Address Latch

• It is group of 8 buffers.
• The upper-byte of 16-bit address is stored
in this latch.
• And then it is made available to the
peripheral devices.

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 Address/Data Latch
• The lower-byte of address and 8-bit of data are
multiplexed.
• It holds either lower-byte of address or 8-bits of data.
• This is decided by ALE (Address Latch Enable)
signal.
• If ALE = 1 then
– Address/Data Latch contains lower-byte of address.
• If ALE = 0 then
– It contains 8-bit data.

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 Serial I/O Controller
• It is used to convert serial data into parallel
and parallel data into serial.
• Microprocessor works with 8-bit parallel
data.
• Serial I/O devices works with serial transfer
of data.
• Therefore, this unit is the interface between
microprocessor and serial I/O devices.

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 Interrupt Controller
• It is used to handle the interrupts.
• There are 5 interrupt signals in 8085:
– TRAP
– RST 7.5
– RST 6.5
– RST 5.5
– INTR

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 Interrupt Controller

• Interrupt controller receives these

interrupts according to their priority and
applies them to the microprocessor.
• There is one outgoing signal INTA which
is called Interrupt Acknowledge.

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 Power Supply

• This unit provides +5V power supply to the

microprocessor.
• The microprocessor needs +5V power
supply for its operation.

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PIN DIAGRAM OF 8085
 Pin Diagram of 8085

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 X1 & X2
Pin 1 and Pin 2 (Input)
These are also called
Crystal Input Pins.

8085 can generate

clock signals internally.

To generate clock

signals internally,
8085 requires external
inputs from X1 and X2.

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 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
RESET IN:

◦ It is used to reset the

microprocessor.

◦ It is active low signal.

◦ When the signal on this

pin is low for at least 3
clocking cycles, it
forces the
microprocessor to reset
itself.

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 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
Resetting the
microprocessor means:

◦ Clearing the PC and IR.

◦ Disabling all interrupts
(except TRAP).
◦ Disabling the SOD pin.
◦ All the buses (data,
address, control) are tri-
stated.
◦ Gives HIGH output to
RESET OUT pin.

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 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
RESET OUT:

◦ It is used to reset the

peripheral devices and other
ICs on the circuit.

◦ It is an output signal.

◦ It is an active high signal.

◦ The output on this pin goes

high whenever RESET IN is
given low signal.

◦ The output remains high as

long as RESET IN is kept low.

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 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
SID (Serial Input Data):

o It takes 1 bit input from

serial port of 8085.

o Stores the bit at the 8th

position (MSB) of the
Accumulator.

o RIM (Read Interrupt

Mask) instruction is
used to transfer the bit.

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 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
SOD (Serial Output Data)
:

o It takes 1 bit from

Accumulator to serial
port of 8085.

o Takes the bit from the 8th

position (MSB) of the
Accumulator.

o SIM (Set Interrupt Mask)

instruction is used to
transfer the bit.
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 Interrupt Pins
Interrupt:

• It means interrupting the normal execution of the

microprocessor.

• When microprocessor receives interrupt signal, it

discontinues whatever it was executing.

• It starts executing new program indicated by the

interrupt signal.

• Interrupt signals are generated by external peripheral

devices.

• After execution of the new program, microprocessor

goes back to the previous program.

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 Sequence of Steps Whenever There is
an Interrupt
Microprocessor completes execution of
current instruction of the program.

PC contents are stored in stack.

PC is loaded with address of the new program.

After executing the new program, the

microprocessor returns back to the previous
program.

It goes to the previous program by reading the

top value of stack.
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 Five Hardware Interrupts in 8085
TRAP

RST 7.5

RST 6.5

RST 5.5

INTR
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 Classification of Interrupts
• Maskable and Non-Maskable

• Vectored and Non-Vectored

• Edge Triggered and Level Triggered

• Priority Based Interrupts

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 Maskable Interrupts
• Maskable interrupts are those
interrupts which can be enabled or
disabled.

• Enabling and Disabling is done by

software instructions.

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 Maskable Interrupts
• List of Maskable Interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• INTR
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 Non-Maskable Interrupts
• The interrupts which are always in
enabled mode are called non-
maskable interrupts.

• These interrupts can never be

disabled by any software instruction.

• TRAP is a non-maskable interrupt.

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 Vectored Interrupts
• The interrupts which have fixed
memory location for transfer of
control from normal execution.

• Each vectored interrupt points to the

particular location in memory.

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 Vectored Interrupts
• List of vectored interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• TRAP
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 Vectored Interrupts
The addresses to which program
control goes:
Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
TRAP 0024 H (4.5 x 0008 H)

Absolute address is calculated by

multiplying the RST value with 0008 H.

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 Non-Vectored Interrupts
• The interrupts which don't have fixed
memory location for transfer of
control from normal execution.

• The address of the memory location

is sent along with the interrupt.

• INTR is a non-vectored interrupt.

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 Edge Triggered Interrupts
• The interrupts which are triggered at
leading or trailing edge are called
edge triggered interrupts.

• RST 7.5 is an edge triggered interrupt.

• It is triggered during the leading

(positive) edge.

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 Level Triggered Interrupts
The interrupts which are triggered at
high or low level are called level
triggered interrupts.

RST 6.5
RST 5.5
INTR

TRAP is edge and level triggered

interrupt.

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 Priority Based Interrupts
• Whenever there exists a
simultaneous request at two or more
pins then the pin with higher priority
is selected by the microprocessor.

• Priority is considered only when there

are simultaneous requests.

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 Priority Based Interrupts
• Priority of interrupts:

Interrupt Priority
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5

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 TRAP
Pin 6 (Input)
It is a non-maskable
interrupt.
It has the highest priority.
It cannot be disabled.
It is both edge and level
triggered.
It means TRAP signal
must go from low to high.
And must remain high for
a certain period of time.
TRAP is usually used for
power failure and
emergency shutoff.
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 RST 7.5
Pin 7 (Input)
It is a maskable interrupt.
It has the second highest
priority.
It is positive edge
triggered only.
The internal flip-flop is
triggered by the rising
edge.
The flip-flop remains high
until it is cleared by
RESET IN.

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 RST 6.5
Pin 8 (Input)
It is a maskable
interrupt.
It has the third highest
priority.
It is level triggered only.
The pin has to be held
high for a specific
period of time.
RST 6.5 can be enabled
by EI instruction.
It can be disabled by DI
instruction.
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 RST 5.5
Pin 9 (Input)
It is a maskable
interrupt.
It has the fourth
highest priority.
It is also level
triggered.
The pin has to be held
high for a specific
period of time.
This interrupt is very
similar to RST 6.5.
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 INTR
Pin 10 (Input)
It is a maskable
interrupt.
It has the lowest
priority.
It is also level triggered.
It is a general purpose
interrupt.
By general purpose we
mean that it can be used
to vector microprocessor
to any specific
subroutine having any
address.
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 INTA
Pin 11 (Output)
It stands for interrupt
acknowledge.
It is an out going
signal.
It is an active low
signal.
Low output on this
pin indicates that
microprocessor has
acknowledged the
INTR request.
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 Address and Data Pins
• Address Bus:

• The address bus is used to send

address to memory.
• It selects one of the many locations in
memory.
• Its size is 16-bit.

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 Address and Data Pins
• Data Bus:

• It is used to transfer data between

microprocessor and memory.
• Data bus is of 8-bit.

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 AD0 – AD7
Pin 19-12 (Bidirectional)
• These pins serve the dual
purpose of transmitting lower
order address and data byte.

• During 1 clock cycle, these

s t

pins act as lower half of

address.

• In remaining clock cycles,

these pins act as data bus.

• The separation of lower order

address and data is done by
address latch.

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 A8 – A15
Pin 21-28 (Unidirectional)
• These pins carry the
higher order of address
bus.

• The address is sent from

microprocessor to
memory.

• These 8 pins are switched

to high impedance state
during HOLD and RESET
mode.
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 ALE
Pin 30 (Output)
• It is used to enable
Address Latch.

• It indicates whether bus

functions as address bus
or data bus.

• If ALE = 1 then
– Bus functions as address
bus.

• If ALE = 0 then
– Bus functions as data bus.
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 S0 and S1
Pin 29 (Output) and Pin 33 (Output)
• S0 and S1 are called Status
Pins.

• They tell the current

operation which is in
progress in 8085.

S0 S1 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch
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 IO/M
Pin 34 (Output)
• This pin tells whether I/
O or memory operation
is being performed.

• If IO/M = 1 then
– I/O operation is being
performed.

• If IO/M = 0 then
– Memory operation is
being performed.

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 IO/M
Pin 34 (Output)
• The operation being performed is
indicated by S and S .
0 1

• If S = 0 and S = 1 then
0 1

– It indicates WRITE operation.

• If IO/M = 0 then
– It indicates Memory operation.

• Combining these two we get Memory Write

Operation.
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 Table Showing IO/M, S0, S1 and
Corresponding Operations

Operations IO/M S0 S1
Opcode Fetch 0 1 1
Memory Read 0 1 0
Memory Write 0 0 1
I/O Read 1 1 0
I/O Write 1 0 1
Interrupt Ack. 1 1 1
Halt High Impedance 0 0

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 RD
Pin 32 (Output)
• RD stands for Read.
• It is an active low signal.
• It is a control signal
used for Read operation
either from memory or
from Input device.
• A low signal indicates
that data on the data
bus must be placed
either from selected
memory location or from
input device.
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 WR
Pin 31 (Output)
• WR stands for Write.
• It is also active low signal.
• It is a control signal used
for Write operation either
into memory or into
output device.
• A low signal indicates that
data on the data bus must
be written into selected
memory location or into
output device.

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 READY
Pin 35 (Input)
• This pin is used to
synchronize slower
peripheral devices with
fast microprocessor.
• A low value causes the
microprocessor to
enter into wait state.
• The microprocessor
remains in wait state
until the input at this
pin goes high.

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 HOLD
Pin 38 (Input)
• HOLD pin is used to
request the
microprocessor for DMA
transfer.
• A high signal on this pin is
a request to
microprocessor to
relinquish the hold on
buses.
• This request is sent by
DMA controller.
• Intel 8257 and Intel 8237
are two DMA controllers.
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 HLDA
Pin 39 (Output)
• HLDA stands for Hold
Acknowledge.
• The microprocessor uses
this pin to acknowledge
the receipt of HOLD
signal.
• When HLDA signal goes
high, address bus, data
bus, RD, WR, IO/M pins
are tri-stated.
• This means they are cut-
off from external
environment.
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 HLDA
Pin 39 (Output)
• The control of these
buses goes to DMA
Controller.
• Control remains at
DMA Controller until
HOLD is held high.
• When HOLD goes low,
HLDA also goes low
and the
microprocessor takes
control of the buses.
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 VSS and VCC
Pin 20 (Input) and Pin 40 (Input)
• +5V power supply is
connected to VCC.

• Ground signal is
connected to VSS.

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ADDRESSING MODES OF
8085
 Addressing Modes of 8085
• To perform any operation, we have to give
the corresponding instructions to the
microprocessor.
• In each instruction, programmer has to
specify 3 things:
– Operation to be performed.
– Address of source of data.
– Address of destination of result.
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 Addressing Modes of 8085
The method by which the address of
source of data or the address of
destination of result is given in the
instruction is called Addressing Modes.
The term addressing mode refers to the
way in which the operand of the
instruction is specified.

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 Types of Addressing Modes
• Intel 8085 uses the following addressing
modes:
1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

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 Direct Addressing Mode
• In this mode, the address of the operand is
given in the instruction itself.

LDA 2500 H Load the contents of memory

location 2500 H in accumulator.

• LDA is the operation.

• 2500 H is the address of source.
• Accumulator is the destination.
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 Register Addressing Mode
• In this mode, the operand is in general
purpose register.
MOV A, B Move the contents of register B to A.

• MOV is the operation.

• B is the source of data.
• A is the destination.

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 Register Indirect Addressing Mode
• In this mode, the address of operand is
specified by a register pair.
MOV A, M Move data from memory location
specified by H-L pair to accumulator.

• MOV is the operation.

• M is the memory location specified by H-L
register pair.
• A is the destination.

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 Immediate Addressing Mode
• In this mode, the operand is specified
within the instruction itself.
MVI A, 05 H Move 05 H in accumulator.

• MVI is the operation.

• 05 H is the immediate data (source).
• A is the destination.

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 Implicit Addressing Mode
If address of source of data as well as
address of destination of result is fixed,
then there is no need to give any operand
along with the instruction.
CMA Complement accumulator.

CMA is the operation.

A is the source.
A is the destination.
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INSTRUCTION SET OF 8085
 Instruction Set of 8085
An instruction is a binary pattern designed inside
a microprocessor to perform a specific function.
The entire group of instructions that a
microprocessor supports is called Instruction Set.
8085 has 246 instructions.
Each instruction is represented by an 8-bit binary
value.
These 8-bits of binary value is called Op-Code or
Instruction Byte.
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 Classification of Instruction Set

• Data Transfer Instruction

• Arithmetic Instructions
• Logical Instructions
• Branching Instructions
• Control Instructions
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 Data Transfer Instructions
• These instructions move data between
registers, or between memory and
registers.
• These instructions copy data from source
to destination.
• While copying, the contents of source are
not modified.

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 Data Transfer Instructions
Opcode Operand Description
MOV Rd, Rs Copy from source to destination.
M, Rs
Rd, M

 This instruction copies the contents of the source

register into the destination register.
 The contents of the source register are not altered.

 If one of the operands is a memory location, its

location is specified by the contents of the HL registers.
 Example: MOV B, C or MOV B, M
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 Data Transfer Instructions
Opcode Operand Description
MVI Rd, Data Move immediate 8-bit
M, Data

 The 8-bit data is stored in the destination register or

memory.

 If the operand is a memory location, its location is

specified by the contents of the H-L registers.

 Example: MVI B, 57H or MVI M, 57H

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 Data Transfer Instructions
Opcode Operand Description
LDA 16-bit address Load Accumulator

 The contents of a memory location, specified by a

16-bit address in the operand, are copied to the
accumulator.

 The contents of the source are not altered.

 Example: LDA 2034H

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 Data Transfer Instructions
Opcode Operand Description
LDAX B/D Register Load accumulator indirect
Pair

 The contents of the designated register pair point to a

memory location.
 This instruction copies the contents of that memory
location into the accumulator.
 The contents of either the register pair or the memory
location are not altered.
 Example: LDAX B
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 Data Transfer Instructions
Opcode Operand Description
LXI Reg. pair, 16-bit Load register pair immediate
data

 This instruction loads 16-bit data in the register pair.

 Example: LXI H, 2034 H

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 Data Transfer Instructions
Opcode Operand Description
LHLD 16-bit address Load H-L registers direct

 This instruction copies the contents of memory

location pointed out by 16-bit address into register L.

 It copies the contents of next memory location into

register H.

 Example: LHLD 2040 H

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 Data Transfer Instructions
Opcode Operand Description
STA 16-bit address Store accumulator direct

 The contents of accumulator are copied into the

memory location specified by the operand.

 Example: STA 2500 H

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 Data Transfer Instructions
Opcode Operand Description
STAX Reg. pair Store accumulator indirect

 The contents of accumulator are copied into the

memory location specified by the contents of the
register pair.

 Example: STAX B

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 Data Transfer Instructions
Opcode Operand Description
SHLD 16-bit address Store H-L registers direct

 The contents of register L are stored into memory

location specified by the 16-bit address.

 The contents of register H are stored into the next

memory location.

 Example: SHLD 2550 H

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 Data Transfer Instructions
Opcode Operand Description
XCHG None Exchange H-L with D-E

 The contents of register H are exchanged with the

contents of register D.

 The contents of register L are exchanged with the

contents of register E.

 Example: XCHG

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 Data Transfer Instructions
Opcode Operand Description
SPHL None Copy H-L pair to the Stack Pointer (SP)

 This instruction loads the contents of H-L pair into SP.

 Example: SPHL

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 Data Transfer Instructions
Opcode Operand Description
XTHL None Exchange H–L with top of stack

 The contents of L register are exchanged with the

location pointed out by the contents of the SP.

 The contents of H register are exchanged with the

next location (SP + 1).

 Example: XTHL

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 Data Transfer Instructions
Opcode Operand Description
PCHL None Load program counter with H-L contents

 The contents of registers H and L are copied into the

program counter (PC).

 The contents of H are placed as the high-order byte

and the contents of L as the low-order byte.

 Example: PCHL

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 Data Transfer Instructions
Opcode Operand Description
PUSH Reg. pair Push register pair onto stack

 The contents of register pair are copied onto stack.

 SP is decremented and the contents of high-order

registers (B, D, H, A) are copied into stack.
 SP is again decremented and the contents of low-order
registers (C, E, L, Flags) are copied into stack.
 Example: PUSH B
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 Data Transfer Instructions
Opcode Operand Description
POP Reg. pair Pop stack to register pair

 The contents of top of stack are copied into register pair.

 The contents of location pointed out by SP are copied to

the low-order register (C, E, L, Flags).
 SP is incremented and the contents of location are
copied to the high-order register (B, D, H, A).
 Example: POP H
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 Data Transfer Instructions
Opcode Operand Description
OUT 8-bit port Copy data from accumulator to a port with 8-
address bit address

 The contents of accumulator are copied into the I/O

port.

 Example: OUT 78 H

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 Data Transfer Instructions
Opcode Operand Description
IN 8-bit port Copy data to accumulator from a port with 8-
address bit address

 The contents of I/O port are copied into accumulator.

 Example: IN 8C H

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 Data Transfer Instructions
• MOV, Rd, Rs
• MOV M, Rs
• MOV Rd, M
• MVI Rd, Data
• MVI M, Data
• LDA 16-bit address
• LDAX B/D Register Pair
• LXI Reg. pair, 16-bit data
• LHLD 16-bit address
• STA 16-bit address
• STAX Reg. pair
• SHLD 16-bit address
• XCHG
 Data Transfer Instructions
• SPHL
• XTHL
• PCHL
• PUSH Reg. Pair
• POP Reg. pair
• OUT 8 bit port addr.
• IN 8 bit port addr.
 Arithmetic Instructions
• These instructions perform the operations
like:
– Addition

– Subtract

– Increment

– Decrement

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 Addition
• Any 8-bit number, or the contents of register,
or the contents of memory location can be
added to the contents of accumulator.
• The result (sum) is stored in the accumulator.
• No two other 8-bit registers can be added
directly.
• Example: The contents of register B cannot
be added directly to the contents of register C.

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 Subtraction
• Any 8-bit number, or the contents of register, or the
contents of memory location can be subtracted
from the contents of accumulator.
• The result is stored in the accumulator.
• Subtraction is performed in 2’s complement form.
• If the result is negative, it is stored in 2’s
complement form.
• No two other 8-bit registers can be subtracted
directly.
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 Increment / Decrement
• The 8-bit contents of a register or a
memory location can be incremented or
decremented by 1.
• The 16-bit contents of a register pair can
be incremented or decremented by 1.
• Increment or decrement can be performed
on any register or a memory location.

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 Arithmetic Instructions
Opcode Operand Description
ADD R Add register or memory to accumulator
M

 The contents of register or memory are added to the

contents of accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified
by H-L pair.
 All flags are modified to reflect the result of the addition.
 Example: ADD B or ADD M
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 Arithmetic Instructions
Opcode Operand Description
ADC R Add register or memory to accumulator with
M carry

 The contents of register or memory and Carry Flag (CY)

are added to the contents of accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified
by H-L pair.
 All flags are modified to reflect the result of the addition.
 Example: ADC B or ADC M
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 Arithmetic Instructions
Opcode Operand Description
ADI 8-bit data Add immediate to accumulator

 The 8-bit data is added to the contents of

accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of the

addition.

 Example: ADI 45 H Gursharan Singh

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 Arithmetic Instructions
Opcode Operand Description
ACI 8-bit data Add immediate to accumulator with carry

 The 8-bit data and the Carry Flag (CY) are added to
the contents of accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of the

addition.

 Example: ACI 45 H Gursharan Singh

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 Arithmetic Instructions
Opcode Operand Description
DAD Reg. pair Add register pair to H-L pair

 The 16-bit contents of the register pair are added to the

contents of H-L pair.
 The result is stored in H-L pair.
 If the result is larger than 16 bits, then CY is set.
 No other flags are changed.
 Example: DAD B
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 Arithmetic Instructions
Opcode Operand Description
SUB R Subtract register or memory from
M accumulator

 The contents of the register or memory location are

subtracted from the contents of the accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified
by H-L pair.
 All flags are modified to reflect the result of subtraction.
 Example: SUB B or SUB M
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 Arithmetic Instructions
Opcode Operand Description
SBB R Subtract register or memory from
M accumulator with borrow

 The contents of the register or memory location and Borrow Flag

(i.e. CY) are subtracted from the contents of the accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified by H-L
pair.
 All flags are modified to reflect the result of subtraction.
 Example: SBB B or SBB M

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 Arithmetic Instructions
Opcode Operand Description
SUI 8-bit data Subtract immediate from accumulator

 The 8-bit data is subtracted from the contents of the

accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of

subtraction.

 Example: SUI 45 H Gursharan Singh

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 Arithmetic Instructions
Opcode Operand Description
SBI 8-bit data Subtract immediate from accumulator with
borrow

 The 8-bit data and the Borrow Flag (i.e. CY) is

subtracted from the contents of the accumulator.

 The result is stored in accumulator.

 All flags are modified to reflect the result of

subtraction.

 Example: SBI 45 H Gursharan Singh

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 Arithmetic Instructions
Opcode Operand Description
INR R Increment register or memory by 1
M

 The contents of register or memory location are

incremented by 1.
 The result is stored in the same place.

 If the operand is a memory location, its address is

specified by the contents of H-L pair.
 Example: INR B or INR M
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 Arithmetic Instructions
Opcode Operand Description
INX R Increment register pair by 1

 The contents of register pair are incremented by 1.

 The result is stored in the same place.

 Example: INX H

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 Arithmetic Instructions
Opcode Operand Description
DCR R Decrement register or memory by 1
M

 The contents of register or memory location are

decremented by 1.
 The result is stored in the same place.

 If the operand is a memory location, its address is

specified by the contents of H-L pair.
 Example: DCR B or DCR M
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 Arithmetic Instructions
Opcode Operand Description
DCX R Decrement register pair by 1

 The contents of register pair are decremented by 1.

 The result is stored in the same place.

 Example: DCX H

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 Logical Instructions
• These instructions perform logical operations on
data stored in registers, memory and status flags.

• The logical operations are:

– AND
– OR
– XOR
– Rotate
– Compare
– Complement

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 AND, OR, XOR
• Any 8-bit data, or the contents of register, or
memory location can logically have
– AND operation
– OR operation
– XOR operation

with the contents of accumulator.

• The result is stored in accumulator.
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 Rotate
• Each bit in the accumulator can be shifted
either left or right to the next position.

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 Compare
• Any 8-bit data, or the contents of register, or
memory location can be compares for:
– Equality
– Greater Than
– Less Than

with the contents of accumulator.

• The result is reflected in status flags.
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 Complement
• The contents of accumulator can be
complemented.
• Each 0 is replaced by 1 and each 1 is
replaced by 0.

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 Logical Instructions
Opcode Operand Description
CMP R Compare register or memory with
M accumulator

 The contents of the operand (register or memory)

are compared with the contents of the accumulator.

 Both contents are preserved .

 The result of the comparison is shown by setting the

flags of the PSW as follows:

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 Logical Instructions
Opcode Operand Description
CMP R Compare register or memory with
M accumulator

 if (A) < (reg/mem): carry flag is set

 if (A) = (reg/mem): zero flag is set

 if (A) > (reg/mem): carry and zero flags are reset.

 Example: CMP B or CMP M

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 Logical Instructions
Opcode Operand Description
CPI 8-bit data Compare immediate with accumulator

 The 8-bit data is compared with the contents of

accumulator.

 The values being compared remain unchanged.

 The result of the comparison is shown by setting the

flags of the PSW as follows:

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 Logical Instructions
Opcode Operand Description
CPI 8-bit data Compare immediate with accumulator

 if (A) < data: carry flag is set

 if (A) = data: zero flag is set

 if (A) > data: carry and zero flags are reset

 Example: CPI 89H

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 Logical Instructions
Opcode Operand Description
ANA R Logical AND register or memory with
M accumulator

 The contents of the accumulator are logically ANDed with the

contents of register or memory.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by
the contents of H-L pair.
 S, Z, P are modified to reflect the result of the operation.
 CY is reset and AC is set.
 Example: ANA B or ANA M.
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 Logical Instructions
Opcode Operand Description
ANI 8-bit data Logical AND immediate with accumulator

 The contents of the accumulator are logically ANDed

with the 8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY is reset, AC is set.
 Example: ANI 86H.
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 Logical Instructions
Opcode Operand Description
ORA R Logical OR register or memory with
M accumulator

The contents of the accumulator are logically ORed with the contents of the
register or memory.
The result is placed in the accumulator.
If the operand is a memory location, its address is specified by the contents
of H-L pair.
S, Z, P are modified to reflect the result.
CY and AC are reset.
Example: ORA B or ORA M.
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 Logical Instructions
Opcode Operand Description
ORI 8-bit data Logical OR immediate with accumulator

 The contents of the accumulator are logically ORed

with the 8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY and AC are reset.
 Example: ORI 86H.
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 Logical Instructions
Opcode Operand Description
XRA R Logical XOR register or memory with
M accumulator

 The contents of the accumulator are XORed with the

contents of the register or memory.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is
specified by the contents of H-L pair.
 S, Z, P are modified to reflect the result of the operation.
 CY and AC are reset.
 Example: XRA B or XRA M.
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 Logical Instructions
Opcode Operand Description
XRI 8-bit data XOR immediate with accumulator

 The contents of the accumulator are XORed with the

8-bit data.
 The result is placed in the accumulator.
 S, Z, P are modified to reflect the result.
 CY and AC are reset.
 Example: XRI 86H.
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 Logical Instructions
Opcode Operand Description
RLC None Rotate accumulator left(Without carry)

 Each binary bit of the accumulator is rotated left by one

position.
 Bit D7 is placed in the position of D0 as well as in the
Carry flag.
 CY is modified according to bit D7.
 S, Z, P, AC are not affected.
 Example: RLC.
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 Logical Instructions
Opcode Operand Description
RRC None Rotate accumulator right

 Each binary bit of the accumulator is rotated right by

one position.
 Bit D0 is placed in the position of D7 as well as in the
Carry flag.
 CY is modified according to bit D0.
 S, Z, P, AC are not affected.
 Example: RRC.
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 Logical Instructions
Opcode Operand Description
RAL None Rotate accumulator left through carry

 Each binary bit of the accumulator is rotated left by one

position through the Carry flag.
 Bit D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
 CY is modified according to bit D7.
 S, Z, P, AC are not affected.
 Example: RAL.
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 Logical Instructions
Opcode Operand Description
RAR None Rotate accumulator right through carry

 Each binary bit of the accumulator is rotated right by

one position through the Carry flag.
 Bit D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
 CY is modified according to bit D0.
 S, Z, P, AC are not affected.
 Example: RAR.
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 Logical Instructions
Opcode Operand Description
CMA None Complement accumulator

 The contents of the accumulator are complemented.

 No flags are affected.
 Example: CMA.

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 Logical Instructions
Opcode Operand Description
CMC None Complement carry

 The Carry flag is complemented.

 No other flags are affected.
 Example: CMC.

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 Logical Instructions
Opcode Operand Description
STC None Set carry

 The Carry flag is set to 1.

 No other flags are affected.
 Example: STC.

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 Branching Instructions
• The branching instruction alter the normal
sequential flow.

• These instructions alter either

unconditionally or conditionally.

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 Branching Instructions
Opcode Operand Description
JMP 16-bit address Jump unconditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
 Example: JMP 2034 H.

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 Branching Instructions
Opcode Operand Description
Jx 16-bit address Jump conditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand based on the specified flag of the PSW.
 Example: JZ 2034 H.

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 Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1

JNC Jump if No Carry CY = 0

JP Jump if Positive S=0

JM Jump if Minus S=1

JZ Jump if Zero Z=1

JNZ Jump if No Zero Z=0

JPE Jump if Parity Even P=1

JPO Jump if Parity Odd P=0

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 Branching Instructions
Opcode Operand Description
CALL 16-bit address Call unconditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
 Before the transfer, the address of the next instruction
after CALL (the contents of the program counter) is
pushed onto the stack.
 Example: CALL 2034 H.
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 Branching Instructions
Opcode Operand Description
Cx 16-bit address Call conditionally

 The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand based on the specified flag of the PSW.
 Before the transfer, the address of the next instruction
after the call (the contents of the program counter) is
pushed onto the stack.
 Example: CZ 2034 H.
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 Call Conditionally
Opcode Description Status Flags
CC Call if Carry CY = 1

CNC Call if No Carry CY = 0

CP Call if Positive S=0

CM Call if Minus S=1

CZ Call if Zero Z=1

CNZ Call if No Zero Z=0

CPE Call if Parity Even P=1

CPO Call if Parity Odd P=0

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 Branching Instructions
Opcode Operand Description
RET None Return unconditionally

 The program sequence is transferred from the

subroutine to the calling program.
 The two bytes from the top of the stack are copied
into the program counter, and program execution
begins at the new address.
 Example: RET.
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 Branching Instructions
Opcode Operand Description
Rx None Call conditionally

 The program sequence is transferred from the

subroutine to the calling program based on the
specified flag of the PSW.
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
 Example: RZ.
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 Return Conditionally
Opcode Description Status Flags
RC Return if Carry CY = 1

RNC Return if No Carry CY = 0

RP Return if Positive S=0

RM Return if Minus S=1

RZ Return if Zero Z=1

RNZ Return if No Zero Z=0

RPE Return if Parity Even P=1

RPO Return if Parity Odd P=0

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 Branching Instructions
Opcode Operand Description
RST 0–7 Restart (Software Interrupts)

 The RST instruction jumps the control to one of eight

memory locations depending upon the number.
 These are used as software instructions in a program
to transfer program execution to one of the eight
locations.
 Example: RST 3.
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 Restart Address Table

Instructions Restart Address

RST 0 0000 H

RST 1 0008 H

RST 2 0010 H

RST 3 0018 H

RST 4 0020 H

RST 5 0028 H

RST 6 0030 H

RST 7 0038 H

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 Control Instructions
• The control instructions control the
operation of microprocessor.

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 Control Instructions
Opcode Operand Description
NOP None No operation

 No operation is performed.
 The instruction is fetched and decoded but no
operation is executed.
 Example: NOP

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 Control Instructions
Opcode Operand Description
HLT None Halt

 The CPU finishes executing the current instruction

and halts any further execution.
 An interrupt or reset is necessary to exit from the halt
state.
 Example: HLT

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 Control Instructions
Opcode Operand Description
DI None Disable interrupt

 The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled.
 No flags are affected.
 Example: DI

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 Control Instructions
Opcode Operand Description
EI None Enable interrupt

 The interrupt enable flip-flop is set and all interrupts

are enabled.
 No flags are affected.
 This instruction is necessary to re-enable the
interrupts (except TRAP).
 Example: EI
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 Control Instructions
Opcode Operand Description
RIM None Read Interrupt Mask

 This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
 The instruction loads eight bits in the accumulator
with the following interpretations.
 Example: RIM
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 RIM Instruction

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 Control Instructions
Opcode Operand Description
SIM None Set Interrupt Mask

 This is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
 The instruction interprets the accumulator contents
as follows.
 Example: SIM
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 SIM Instruction

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 PROGRAMMABLE PERIPHERAL
INTERFACE -8255

Features:
• It is a programmable device.

• It has 24 I/O programmable pins like PA,PB,PC

(3-8 pins).

 T T L compatible.

 Improved dc driving capability

200
Pin Diagram

201
 Function of pins:
• Data bus(D0-D7):These are 8-bit bi-directional
buses, connected to 8085 data bus for
transferring data.

• CS: This is Active Low signal. When it is low,

then data is transfer from 8085.

• Read: This is Active Low signal, when it is Low

read operation will be start.

• Write: This is Active Low signal, when it is Low

Write operation will be start.
202
• Address (A0-A1):This is used to select the
ports. like this

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC

1 1 Control reg.

203
• RESET: This is used to reset the device. That
means clear control registers.

• PA0-PA7:It is the 8-bit bi-directional I/O pins used

to send the data to peripheral or
or to receive the data from peripheral.

• PB0-PB7:Similar to PA

• PC0-PC7:This is also 8-bit bidirectional I/O pins.

These lines are divided into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups working in separately using 4
data’s.
204
Block Diagram

205
Data Bus buffer:
• It is a 8-bit bidirectional Data bus.

• Used to interface between 8255 data bus

with system bus.

• The internal data bus and Outer pins D0-D7

pins are connected in internally.

• The direction of data buffer is decided by

Read/Control Logic.
206
Read/Write Control Logic:
• This is getting the input signals from
control bus and Address bus

• Control signal are RD and WR.

• Address signals are A0,A1,and CS.

• 8255 operation is enabled or disabled by

CS.
207
Group A and Group B control:
• Group A and B get the Control
Signal from CPU and send the command to the
individual control blocks.
• Group A send the control signal to port A and Port
C (Upper) PC7-PC4.
• Group B send the control signal to port B and Port
C (Lower) PC3-PC0.
• PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode
2.

208
PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode
1.
• PORT C:
• This is a 8-bit Unlatched buffer Input and an
Output latch.
• It is splitted into two parts.
• It can be programmed by bit set/reset
operation.

209
 Operation modes:
BIT SET/RESET MODE:
• The PORT C can be Set or Reset by sending OUT
instruction to the CONTROL registers.
I/O MODES:
• MODE 0(Simple input / Output):
• In this mode , port A, port B and port C is used as
individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability.
210
• MODE 1 :(Input/output with Hand shake)
• In this mode, input or output is transferred by
hand shaking Signals.

Computer DATA BUS Printer

STB
ACK

Busy

• Handshaking signals is used to transfer data

between those whose data transfer rate is
not same.
211
• Example:
• The computer send the data to the printer
large speed compared to the printer.
• When computer send the data according to
the printer speed at the time only, printer can
accept.
• If printer is not ready to accept the data then
after sending the data bus , computer uses
another handshaking signal to tell printer that
valid data is available on the data bus.
• Each port uses three lines from port C as
handshake signals
212
MODE 2:bi-directional I/O data transfer:
• This mode allows bidirectional data transfer
over a single 8-bit data bus using handshake
signals.
• This feature is possible only Group A
• Port A is working as 8-biy bidirectional.
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port ,
when the peripheral request it.
• CONTROL WORD FORMATS:
• In the INPUT mode , When RESET is High all
24 pins (3-ports) be a input mode. 213
• i.e all flip flops are cleared and the interrupts
are reset.
• This condition is maintained even after
RESET goes low.
• This can be avoid by writing single control
word to the control registers , when required.

214
FOR BIT SET/RESET MODE:
• This is bit set/reset control word format.
D7 D6 D5 D4 D3 D2 D1 D0

X X X BIT SET/
RESET
Don’t care 1=SET
0=RESET

Bit select
0 1 2 3 4 5 6 7
0 1 0 1B00 1 0 1
0 0 1 1B10 0 1 1
0 0 0 0B21 1 1 1

BIT SET/RESET FLAG

=0 Active
215
• PC0-PC7 is set or reset as per the status of D0.
• A BSR word is written for each bit
• Example:
• PC3 is Set then control register will be
0XXX0111.
• PC4 is Reset then control register will be
0XXX01000.
• X is a don’t care.

216
• FOR I/O MODE:
The mode format for I/O as shown in figure

D7 D6 D5 D4 D3 D2 D1 D0

Group A Group B
Port C Upper
1=Input Port C Lower
Mode set
0=Output 1=Input
flag=1=Active
Port B 0=Output
1=Input Port B
0=Output 1=Input
Mode selection 0=Output
00=mode 0 Mode selection
01=mode 1 0=mode 0
1x=mode 2 1=mode 1

217
• The control word for both mode is same.
• Bit D7 is used for specifying whether word
loaded in to Bit set/reset mode or Mode
definition word.
• D7=1=Mode definition mode.
• D7=0=Bit set/Reset mode.
Digital-to-Analog
Analog-to-Digital
 Data Handling Systems
• Both data about the physical world and control
signals sent to interact with the physical world
are typically "analog" or continuously varying
quantities.
• In order to use the power of digital electronics,
one must convert from analog to digital form on
the experimental measurement end and convert
from digital to analog form on the control or
output end of a laboratory system.
Data Collection and Control
Digital-to-Analog Conversion
[DAC]
 Digital-to-Analog Conversion
• When data is in binary form, the 0's and 1's
may be of several forms such as the TTL
form where the logic zero may be a value
up to 0.8 volts and the 1 may be a voltage
from 2 to 5 volts.
• The data can be converted to clean digital
form using gates which are designed to be
on or off depending on the value of the
incoming signal.
 Digital-to-Analog Conversion
• Data in clean binary digital form can be
converted to an analog form by using a
summing amplifier.
• For example, a simple 4-bit D/A converter
can be made with a four-input summing
amplifier.
 Digital-to-Analog Conversion

• 2 Basic Approaches

– Weighted Summing Amplifier

– R-2R Network Approach
 Weighted Sum DAC
• One way to achieve D/A conversion is to
use a summing amplifier.
• This approach is not satisfactory for a
large number of bits because it requires
too much precision in the summing
resistors.
• This problem is overcome in the R-2R
network DAC.
Weighted Sum DAC
R-2R Ladder DAC
R-2R Ladder DAC
 R-2R Ladder DAC

• The summing amplifier with the R-2R ladder of

resistances shown produces the output where
the D's take the value 0 or 1.
• The digital inputs could be TTL voltages which
close the switches on a logical 1 and leave it
grounded for a logical 0.
• This is illustrated for 4 bits, but can be
extended to any number with just the
resistance values R and 2R.
 DAC0830/DAC0832
8-Bit µP Compatible DAC
• An advanced CMOS/Si-Cr 8-bit multiplying DAC
designed to interface directly with the 8080, 8048, 8085,
Z80®, and other popular microprocessors.
• A deposited silicon-chromium R-2R resistor ladder
network divides the reference current and provides the
circuit with excellent temperature tracking
characteristics (0.05% of Full Scale Range maximum
linearity error over temperature).
Typical Application
Analog to Digital Conversion
[ADC]
 ADC Basic Principle
• The basic principle of operation is to use
the comparator principle to determine
whether or not to turn on a particular bit of
the binary number output.
• It is typical for an ADC to use a digital-to-
analog converter (DAC) to determine one
of the inputs to the comparator.
 ADC Various Approaches
• 3 Basic Types

• Digital-Ramp ADC
• Successive Approximation ADC
• Flash ADC
 Digital-Ramp ADC

• Conversion from analog to digital form

inherently involves comparator action
where the value of the analog voltage at
some point in time is compared with
some standard.
• A common way to do that is to apply the
analog voltage to one terminal of a
comparator and trigger a binary counter
which drives a DAC.
Digital-Ramp ADC
 Digital-Ramp ADC

• The output of the DAC is applied to the

other terminal of the comparator.
• Since the output of the DAC is increasing
with the counter, it will trigger the
comparator at some point when its
voltage exceeds the analog input.
• The transition of the comparator stops
the binary counter, which at that point
holds the digital value corresponding to
the analog voltage.
Successive approximation ADC

Illustration of 4-bit SAC with 1 volt step size

Successive approximation ADC
• Much faster than the
digital ramp ADC
because it uses
digital logic to
converge on the
value closest to the
input voltage.
• A comparator and a
DAC are used in the
process.
 Flash ADC
• It is the fastest type of ADC
available, but requires a comparator
for each value of output.
(63 for 6-bit, 255 for 8-bit, etc.)
• Such ADCs are available in IC form
up to 8-bit and 10-bit flash ADCs
(1023 comparators) are planned.
• The encoder logic executes a truth
table to convert the ladder of inputs
to the binary number output.

Illustrated is a 3-bit flash ADC with resolution 1 volt

 Flash ADC
• The resistor net and comparators provide
an input to the combinational logic circuit,
so the conversion time is just the
propagation delay through the network - it
is not limited by the clock rate or some
convergence sequence.
 ADC080x, 8-Bit µP Compatible A/D
Converters
• CMOS 8-bit successive approximation A/D converters that use
a differential potentiometer ladder—similar to the 256R
products.
• These converters are designed to allow operation with the
NSC800 and INS8080A derivative control bus with TRI-STATE
output latches directly driving the data bus.
• These A/Ds appear like memory locations or I/O ports to the
microprocessor and no interfacing logic is needed.
• Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog zero input
voltage value.
• In addition, the voltage reference input can be adjusted to
allow encoding any smaller analog voltage span to the full 8
bits of resolution.
 ADC080x Features
• Compatible with 8080 µP
derivatives—no interfacing logic
needed - access time - 135 ns
• Easy interface to all microprocessors,
or operates “stand alone”
• Differential analog voltage inputs
• Logic inputs and outputs meet both
MOS and TTL voltage level
specifications
• Works with 2.5V (LM336) voltage
reference
• On-chip clock generator
• 0V to 5V analog input voltage range
with single 5V supply
• No zero adjust required
ADC080x, interfacing
Functional
Functional Diagram
Diagram
Multiple A/D Intf. with Z80

PORT, DEV
00 74C374
01 A/D 1
02 A/D 2
03 A/D 3
04 A/D 4
05 A/D 5
06 A/D 6
07 A/D 7
 I/O interfacing
• Introduction:
– Peripheral devices provide interface between the CPU and slow
electromechanical devices
– Previously, all these devices were taken care of by the CPU using
interrupt mechanism or polling techniques, which results in reduced
overall efficiency and low processing speed
– To minimize the slow speed I/O communication overhead, a set of
dedicated programmable peripheral devices have been introduced
– Thus once initiated by the CPU, these devices take care of all the
interface activities , and thus makes the CPU free from the interface
activities and execute its main task more efficiently.

Advanced Microprocessor 248

 Programmable interval Timer 8253
Function and working principle of 8253:
• The 8253/54 solves one of most common problem in any microcomputer
system, the generation of accurate time delays under software control.
• Instead of setting up timing loops in system software, the programmer
configures the 8253/54 to match his requirements, initializes one of the
counters of the 8253/54 with the desired quantity, then upon command the
8253/54 will count out the delay and interrupt the CPU when it has
completed its tasks.
• It is easy to see that the software overhead is minimum and that multiple
delays can be easily be maintained by assignment of priority levels.
• The 8253/54 includes three identical 16 bit counters that can operate
independently.
• To operate a counter, a 16-bit count is loaded in its register and, on
command, it begins to decrement the count until it reaches 0.

Advanced Microprocessor 249

Programmable interval Timer 8253

• At the end of the count, it generates a pulse that can be used to

interrupt the CPU.
• The counter can count either in binary or BCD.
• In addition, a count can be read by the CPU while the counter is
decrementing.
FEATURES:
• Three independent 16-bit down counters.
• Each with maximum count rate of 2.6 MHz .
• Three counters are identical presettable, down counters and can be
programmed for either binary or BCD count.
• Counter can be programmed in six different modes.
• Compatible with all Intel and most other microprocessors.

250
 Programmable interval Timer 8253

FEATURES:
• 8253 has powerful command called READ BACK command which allows
the user to check the count value, programmed mode and current mode
and
current status of the counter.
Architecture and signal descriptions:
• Three independent 16-bit counters, all these counters may be
independently controlled by programming the 3 internal command word
registers, thus possible to generate 3 totally independent delays or
maintain 3 independent counters simultaneously.
• It has 8-bit, bidirectional data buffer interfaces internal circuit of 8253 to
microprocessor system bus.
• Data is transmitted or received by the buffer upon the execution of IN
(reads data) or OUT(writes data to a peripheral) instruction.
• Read/write logic controls the direction of the data buffer depending upon
whether it is read or write operation.
Advanced Microprocessor 251
 I/O Interface

8254 Functional Description

Advanced Microprocessor 252

 Programmable interval Timer 8253

• Fig. above shows the block diagram of 8253/54. It includes three counters,
a data
bus buffer, Read/Write control logic, and a control register.
• Each counter has two input signals CLOCK and GATE and one output signal
OUT.
– CLK: The clock input is the timing source for each of the internal counters. It is often
connected to the PCLK signal from the bus controller.
– GATE: The gate input controls the operation of the counter in some modes.
– OUT: A counter output where the wave-form generated by the timer is available.
Data Bus Buffer :
•This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.

Advanced Microprocessor 253

 Programmable interval Timer 8253

Read/Write Logic :
• The Read/Write logic has five signals : RD,WR,CS and the address lines A0
and
A1.
• In the peripheral I/O mode, the RD, and WR signals are connected to IOR
and
IOW, respectively.
• In memory-mapped I/O, these are connected to MEMR and MEMW.
• Address lines A0 and A1 of the CPU are usually connected to lines A0 and
A1 of
the 8253/54, and CS is tied to a decoded address.
• The control word register and counters are selected according to the
signals on
lines A0 and A1.

Advanced Microprocessor 254

 Programmable interval Timer 8253
Read/Write Logic :
• A low on CS line enables the 8253. No operation will be performed by 8253 till
it
is enabled. Table below shows the selected operations for various inputs of
8253:
CS RD WR A1 A0 selected operation
0 1 0 0 0 write counter 0
0 1 0 0 1 write counter 1
0 1 0 1 0 write counter 2
0 1 0 1 1 write control word
0 0 1 0 0 read counter 0
0 0 1 0 1 read counter 1
0 0 1 1 0 read counter 2
0 0 1 1 1 no operation
0 1 1 x x no operation
1 X x x x disabled

Advanced Microprocessor 255

 Programmable interval Timer 8253

Control Word Register :

• This register is accessed when lines A0 and A1 are at logic 1
• It is used to write a command word which specifies the counter to be used
(binary or BCD), its mode, and either a read or write operation.
Counters :
• These three functional blocks are identical in operation. Each counter
consists of a single, 16 bit, pre-settable, down counter. The counter can
operate in either binary or BCD and its input, gate and output are
configured by the selection of modes stored in the control word register.
• The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the actual count in
process.

Advanced Microprocessor 256

 Programmable interval Timer 8253
Operational Description:
• The complete functional definition of the 8253/54 is programmed by the
system
• software. Once programmed, the 8253/54 is ready to perform whatever timing
tasks it is assigned to accomplish.
Programming the 8253/54 :
• Each counter of the 8253/54 is individually programmed by writing a control
word into the control word register (A0 -A1 = 11).
• The Fig. shows the control word format.
• Bits SC1 and SC0 select the counter, bits RW1 and RW0 select the read, write
or latch command, bits M2,M1 and M0 select the mode of operation and bit
BCD decides whether it is a BCD counter or binary counter.
• The complete functional definition of the 8253/54 is programmed by the
system
• software.
• Once programmed, the 8253/54 is ready to perform whatever timing tasks it
is assigned to accomplish.

Advanced Microprocessor 257

 Programmable interval Timer 8253

Each counter is individually programmed by writing a control word, followed

by the initial count.

The control word allows the programmer to select the counter, mode of
operation, binary or BCD count and type of operation (read/write).

Advanced Microprocessor 258

 Programmable interval Timer 8253
Programming the 8254

Each counter may be programmed with a count of 1 to FFFFH.

Each counter has a program control word used to select the way the
counter operates.
If two bytes are programmed, then the first byte (LSB) stops the count,
and the second byte (MSB) starts the counter with the new count.

There are 6 modes of operation for each counter:

Mode0, Mode1, Mode2, MOde3, Mode4, Mode5

Advanced Microprocessor 259

 Programmable interval Timer 8253
Programming the 8254
Modes of operation
 Mode 0: interrupt on terminal count.
The output becomes a logic 0 when the control word is written and remains
there until N plus the number of programmed counts.

 Mode 1: One-shot mode.

The G input triggers the counter to output a 0 pulse for count clocks.Counter
reloaded if G is pulsed again.

Advanced Microprocessor 260

 Programmable interval Timer 8253
Programming the 8254
Modes of operation
Mode 2: rate generator or divide by N counter
N is loaded as the count value, then after N pulses, the output becomes low only
for one clock cycle.
The cycle is repeated until reprogrammed or G pin set to 0.

 Mode 3: Generates a continuous square-wave with G set to 1.

If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

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 Programmable interval Timer 8253
Programming the 8254
Modes of operation
Mode 4: Software triggered one-shot (G must be 1).

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

Trigger with count of 5

Advanced Microprocessor 262

Programmable interval Timer 8253I/O Interface

Advanced Microprocessor 263

 Programmable interval Timer 8253I/O Interface
Read Operations

There are three possible methods for reading the counters:

• a simple read operation
• the Counter Latch Command
• the Read-Back Command

Simple read operation :

• The Counter which is selected with the A1, A0 inputs, the CLK input of the
selected Counter must be inhibited by using either the GATE input or external
logic.
• Otherwise, the count may be in the process of changing when it is read, giving
an undefined result.

Advanced Microprocessor 264

 Programmable interval Timer 8253I/O Interface

Counter Latch Command:

• SC0, SC1 bits select one of the three

Counters
• two other bits, D5 and D4, distinguish
this command from a Control Word

• If a Counter is latched and then, some

time later, latched again before the
count is read, the second Counter Latch
Command is ignored. The count read
will be the count at the time the first
Counter Latch Command was issued.

Advanced Microprocessor 265

 Programming
CONTROL WORD FORMAT

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

0 0 1 1 0 1 0 0

= 34H(Mode 2)

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

0 0 1 1 0 1 1 0

= 36H(Mode 3)
 Control word
• SELECT COUNTER SC0 SC1 OPE RATION
BIT DEFINITION
0 0 Select channel
0 1 0
1 0 Select channel
1 1 1
Select channel
• READ\LOAD BIT RL0 RL1 2 RATION
OPE
DEFINITION Illegeal
0 0 Latch Counter
0 1 Read\Load(LSB)
1 0 Read\Load(MSB)
1 1 Read\Load LSB
first then
MSB
 MODE

M2 M1 M0 SELECTED
MODE

0 0 0 MODE 0 MODE SELECT BIT DEFINITION

0 0 1 MODE 1
X 1 0 MODE 2
X 1 1 MODE 3
1 0 0 MODE 4
1 0 1 MODE 5

BCD OPERATION
0 Hex Count
1 BCD Count HEX\BCD BIT DEFINITION
 Rate Generator

MOV AL,34H
Move the command word to A register
OUT 16,AL Output it to control register
MOV AL,04H Move 04 to A register
OUT 10,AL Output the value to counter 0
MOV AL,00H Move 00 to A register

OUT 10,AL Output the value to content 0

HLT Halt the program execution
 SQUARE WAVE

MOV AL,36H Move the command word to A

register
OUT 16,AL Output it to control register
MOV AL,04H Move 04 to A register
OUT 10,AL Output the value to counter 0

MOV AL,00H Move 00 to A register

OUT 10,AL Output the value to content 0

HLT Halt the program execution

 I/O Interface
16550 Programmable Communications Interface:
• 16550 , A universal asynchronous receiver/transmitter (UART).
• it capable of operating speed: 0 to 1.5M Baud (Baud is # of bits transmitted/
sec, including start, stop, data and parity).
•It includes:
- A programmable Baud rate generator.
- Separate FIFO buffers for input and and output data (16 bytes each).

Asynchronous serial data:

Asynchronous serial data are transmitted and received without a clock or
timing signal.

Two 10-bit frames of asynchronous serial data, start bit, 7 data bit, parity &
stop bit.
Advanced Microprocessor 271
 I/O Interface

16550 functional description:

• this device is available as 40-pin DIP( dual in-line package) or as a 44-pin PLCC (
plastic lead less chip)

• two separate sections are responsible for data communications

- Receiver & Transmitter

• can function :
- simplex: transmit only,
eg:FM radio station
-half-duplex: transmit and receive but not
simultaneously
eg: CB( citizen band) station
- full-duplex: transmit and receive
simultaneously
eg : telephone

Advanced Microprocessor 272

 I/O Interface

•main feature, has internal receiver & transmitter FIFO memories,

each 16 Bytes deep.

• the UART, requires attention only from the microprocessor after

receiving 16 bytes of data

• it holds 16 bytes before the microprocessor must wait for the ‘

transmitter.

• the FIFO makes UART ideal when interfacing to high speed systems

Advanced Microprocessor 273

 I/O Interface

The 16550 can control a modem through

and .

the modem is called the data set

the 16550 is called the data terminal.

16550 Pin function:

A0, A1 and A2: Select an internal register for

programming and data transfer.

Advanced Microprocessor 274

 I/O Interface

 : Address strobe used to latch address and chip select. Not needed on
Intel systems - connected to ground.
 : Clock signal from Baud rate generator in transmitter.
 CS0, CS1, : Chip selects must all be active enable the 16550 UART
 : Clear to send -- indicates that the modem or data set is ready to
exchange information. (Used in half-duplex to turn the line around).
 D7-D0: The data bus pins are connected to the microprocessor data bus.
 : The data carrier detect -- used by the modem to signal the 16550
that a carrier is present.
 DDIS: Disable driver output -- set to 0 to indicate that the microprocessor is
reading data from the UART. Used to change direction of data flow through a
buffer.

Advanced Microprocessor 275

 I/O Interface

 : Data set ready is an input to 16550, indicates that the modem (data
set) is ready to operate.

 : Data terminal ready is an output, indicates that the data terminal (16550)
is ready to function.

 INTR: Interrupt request is an output to the microprocessor, used to request an

interrupt.
Receiver error, Data received, Transmit buffer empty

 MR: Master reset , connect to system RESET

 : User defined output pins for modem or other device.

 RCLK: Receiver clock, clock input to the receiver section of the UART.
Always 16X the desired receiver Baud rate.

Advanced Microprocessor 276

 I/O Interface
 : Ring indicator input , set to 0 by modem to indicate telephone is ringing.

 RD, : Read inputs (either can be used), cause data to be read from the register
given by the address inputs

 :Request-to-send, signal to modem, indicating UART

wishes to send data.

SIN, SOUT: Serial data pins, in and out.

 : Receiver ready, used to transfer received data
via DMA techniques.

 :Transmitter ready, used to transfer transmitter data

via DMA
 WR, :Write (either can be used) , connects to microprocessor
write signal to transfer commands and data to 16550.

XIN, XOUT: Main clock connections -- a crystal oscillator can be used.

Advanced Microprocessor 277

 I/O Interface

Programming 16550:
• the programming is a two part process
- initialization dialog
- operational dialog

Initializing 16550:
•Initialization dialog, occurs after a hardware or software reset,
Consists of two parts
- line control register
- baud rate generator
must be programmed

•Line control register selects: number of stop & parity bit( even or odd)

•Baud rate generator: programmed with a divisor that determine the

baud rate of the transmission section

Advanced Microprocessor 278

 I/O Interface

Line control register:

• programmed by outputting information to I/O ports 011
• Right most 2 bits, selects the number of transmitted data bits
(5,6,7or 8)

• Stop bits: S = 1, 1.5 stop bits used for 5 data bits, 2 used for 6, 7 or 8.
• next 3 bits: ST(stick), P and PE used to send even or odd parity, to send no
parity or to send a 1 or a 0 in the parity bit position for all data.

Advanced Microprocessor 279

 I/O Interface

•SB = 1 , used to send a break to be transmitted on SOUT.

A break is at least two frame of logic 0 data.
software is responsible for timing the transmission,
to end the break SB return to logic 0

•DL = 1, enables programming of the baud rate divisor.

Advanced Microprocessor 280

 I/O Interface

Programming the baud rate:

Baud rate generator is programmed with a divisor that sets
baud rate of transmitter.

• Baud rate generator is programmed at 000 and 001 ( A2,A!,A0).

Port 000 used to hold least significant part, 001 most
significant part

Value used depends on external clock/crystal frequency.

For 18.432MHz crystal :
- 10,473 divisor value 110 band rate,
- 30 divisor value gives 38,400 baud

Note : the actual number programmed into baud rate generator causes, to
produce a clock that is 16 times the desired baud rate
eg : if 240 is programmed into baud rate divisor,
Baud rate = 18.432 MHz/(16X240) = 4800 baud.

Advanced Microprocessor 281

 I/O Interface

FIFO control register for 16550:

• register enable the transmitter & receiver and clears the transmitter
& receiver FIFO.
• provides control for 16550 interrupts

Sending serial data :

line status register, contains the information about
- error conditions
- state of the transmitter & receiver

• the register is tested before a byte is transmitted or can be received

Advanced Microprocessor 282

 I/O Interface

Suppose a program wants to send data out SOUT.

•It needs to pool the TH bit to determine if transmitter is ready to
receive data.

Receiving serial data:

•To receive information, the DR bit is tested.

Advanced Microprocessor 283

 I/O Interface

UART error:
Operation:
It is also a good idea to check for errors.

•Parity error: Received data has wrong error, transmission bit flip due to noise.

•Framing error: Start and stop bits not in their proper places.
This usually results if the receiver is receiving data at the incorrect baud rate.

•Overrun error: Data has overrun the internal receiver FIFO buffer.
Software is failing to read the data from UART before the FIFO is full.

•( BI )Break indicator bit: Software should check for this as well, i.e. two
consecutive frames of 0s.

Advanced Microprocessor 284

 I/O Interface

Examples, 16550 interfaced to the 8088 at ports 00F0H – 00F7H

Advanced Microprocessor 285

 I/O Interface

•Here port F3H accesses the line control register

•F0H & F1H access the baud rate divisor register

• after the line control register & baud rate divisor are programmed , still it is
not ready to function

• program the FIFO control register, at port F2H

Advanced Microprocessor 286

8259 PIC
 Introduction
• An interrupt is an event which informs
the CPU that its service (action) is
needed.
• Sources of interrupts:
– internal fault (e.g.. divide by zero, overflow)
– software
– external hardware :
• maskable
• nonmaskable
– reset
 Programmable Interrupt Controller (PIC)
• 8259 is Programmable Interrupt Controller (PIC)
• It is a tool for managing the interrupt requests.
• 8259 is a very flexible peripheral controller
chip:
– PIC can deal with up to 64 interrupt inputs
– interrupts can be masked
– various priority schemes can also programmed.
• originally (in PC XT) it is available as a
separate IC
• Later the functionality of (two PICs) is in the
motherboards chipset.
 Pin description
CS (CHIP SELECT) :
• A LOW on this input enables the 8259A. No reading or writing of the chip
will occur unless the device is selected.
WR (WRITE):
• A LOW on this input enables the CPU to write control words (ICWs and
OCWs) to the 8259A.
RD (READ) :
• A LOW on this input enables the 8259A to send the status of the Interrupt
Request Register (IRR), In Service Register (ISR), the Interrupt Mask
Register (IMR), or the Interrupt level onto the Data Bus.
A0:
• This input signal is used in conjunction with WR and RD signals to write
commands into the various command registers, as well as reading the
various status registers of the chip. This line can be tied directly to one of
the address lines.
 Pin description
D7 - D0: BIDIRECTIONAL DATA BUS- Control, status and interrupt-vector
information is transferred via this bus.
CAS0 - CAS2: CASCADE LINES: The CAS lines form a private 8259A bus to
control a multiple 8259A structure. These pins are outputs for a
master
8259A and inputs for a slave 8259A.
SP/EN: SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.
When in the Buffered Mode it can be used as an output to control
buffer
transceivers (EN). When not in the buffered mode it is used as an
input to
designate a master (SP e 1) or slave (SP e 0).
INT : INTERRUPT: This pin goes high whenever a valid interrupt request is
asserted. It is used to interrupt the CPU, thus it is connected to the CPU's
interrupt pin.
INTA: INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A
interrupt-vector data onto the data bus by a sequence of interrupt
acknowledge
pulses issued by the CPU.
 Architecture of PIC-8257
Features:
• It is programmed to work with either 8085 or 8086 processor.
• It manage 8-interrupts according to the instructions written into its control registers.
• In 8086 processor, it supplies the type number of the interrupt and the type number
is programmable. In 8085 processor, the interrupt vector address is programmable.
The priorities of the interrupts are programmable.
• The interrupts can be masked or unmasked individually.
• The 8259s can be cascaded to accept a maximum of 64 interrupts.
FUNCTIONAL BLOCK DIAGRAM OF 8259:
It has eight functional blocks. They are:
• Control logic
• Read Write logic
• Data bus buffer
• Interrupt Request Register (IRR)
• In-Service Register (ISR)
• Interrupt Mask Register (IMR)
• Priority Resolver (PR)
• Cascade buffer.
 Architecture of PIC-8259
Data Bus Buffer:
Data bus and its buffer are used for the following activities:
• It is a tristate bidirectional buffer interfaces internal 8259A to the
microprocessor system data bus
• The processor sends control word to data bus buffer through D0-D7.
• The processor read status word from data bus buffer through D0-D7
• From the data bus buffer the 8259 send type number through D0-D7 to
the processor.
Read/Write control logic
• The function of this block is to accept OUTput commands from the CPU. It
contains the Initialization Command Word (ICW) registers and Operation
• Command Word (OCW) registers which store the various control formats
for device operation. This function block also allows the status of the
8259A to be transferred onto the Data Bus.
 Architecture of PIC-8259
Interrupt request register:
• The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go
high, the request is stored in IRR in order to serve them one by one on the
priority basis. It registers a request only if the interrupt is unmasked.
• Normally IR0 has highest priority and IR7 has the lowest priority. The
priorities of the interrupt request input are also programmable.
• First the 8259 should be programmed by sending Initialization Command
Word (ICW) and Operational Command Word (OCW). These command
words will inform 8259 about the following:

• Type of interrupt signal (Level triggered / Edge triggered).

• Type of processor (8085/8086).
• Call address and its interval (4 or 8)
• Masking of interrupts.
• Priority of interrupts.
• Type of end of interrupts.
 Architecture of PIC-8259
Interrupt mask register (IMR):
• The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be
masked. The relevant information is send by the processor through OCW.
In-service register(ISR):
• The in-service register keeps track of which interrupt is currently being serviced.
Priority resolver:
• The priority resolver examines the interrupt request, mask and in-service registers
and determines whether INT signal should be sent to the processor or not. The IR0
has the hiest priority while the IR7 has the lowest priority, normally in fixed priority
mode. The priorities however may be altered by the programming the 8259A in
rotating mode.
Cascade buffer/comparator:
• The cascade buffer/comparator is used to expand the interrupts of 8259.
• In cascade connection one 8259 will be directly interrupting 8086 and it is called
master 8259.
• To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be
connected. The 8259s interrupting the master 8259 are called slave 8259s.
• Each 8259 has its own addresses so that each 8259 can be programmed
independently by sending command words and independently the status bytes can
be read from it.
FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel
Corporation.)
 INTERRUPT SEQUENCE

The events occur as follows in an 8086 system:

1. One or more of the INTERRUPT REQUEST lines (IR7 – IR0) are raised high,
setting the corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is
set, and the corresponding IRR bit is reset. The 8259A will also release a
CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 -
D0 pins.
5. This CALL instruction will initiate second INTA pulses to be sent to the
8259A from the CPU group.
6. This INTA pulse allow the 8259A to release an 8-bit preprogrammed
subroutine address onto the Data Bus.
7. ISR bit is reset at the end of the 2nd INTA pulse if automatic EOI mode is
programmed
 Priority Modes

• Fully Nested mode

• Automatic Rotating Mode
• Specific Rotating Mode
 END of Interrupt

1.Nonspecific EOI

2.Specific EOI

3Automatic EOI
 Command words of 8259A

PROGRAMMING THE 8259A

The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs): Before normal operation can
begin, each 8259A in the system must be initialized by writing 2 to 4
command words in the resp. command word reg.

2. Operation Command Words (OCWs): These are the command words

which command the 8259A to operate in various interrupt modes.
These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.
Programmable Keyboard/Display
Interface - 8279
 8279 contains the following features:
• Simultaneous and independent scanning of a
keyboard and refresh of a display,
• significantly offloading these functions from the
microprocessor.
Keyboard section:
– 8-character Keyboard FIFO
– 2-Key Lockout or N-key Rollover with Contact Debounce
– Interrupt Output on Key Entry
– Programmable Keyboard Scan & Debounce rates
Display Section:
– Dual 8- or 16-Numeric Display
– Single 16-Character Display
– Right or Left Entry 16-Byte Display RAM with address auto increment
– Programmable display refresh rate
PIN DIAGRAM
 Pinout Definition 8279
• P A0: Selects data (0) or control/status (1) for reads and
writes between micro and 8279.
• P BD: Output that blanks the displays.
• P CLK: Used internally for timing. Max is 3 MHz.
• P CN/ST: Control/strobe, connected to the control key on
the keyboard.
• P CS: Chip select that enables programming, reading the keyboard, etc.
• P DB7-DB0: Consists of bidirectional pins that connect to data bus on
micro.
• P IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
• P OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least
significant nibble of display.
• P RD(WR): Connects to micro's IORC or RD signal, reads data/status
registers.
• P RESET: Connects to system RESET.
• P RL7-RL0: Return lines are inputs used to sense key depression in the
keyboard matrix.
• P Shift: Shift connects to Shift key on keyboard.
• P SL3-SL0: Scan line outputs scan both the keyboard and displays
 KEYBOARD SECTION
• Has eight lines: RL0 to RL7 + two additional lines:
CNTL/STB; connected to 8 columns of the keyboard
• 2 modes:
• 2 key lockout: if two keys are pressed simultaneously only 1st
key is recognized
• N-key rollover: simultaneous keys are recognized and their
codes are stored in internal buffer.
• Keyboard section also includes 8X8 FIFO which
further consists of eight registers that can store 8
keyboard entries.
 SCAN SECTION
• Has scan counter and four scan lines: SL0
to SL3
• These are decoded using 4X16 decoder
• Further these 16 lines are connected to
rows of matrix keyboard and digital drivers
of multiplexed display
 DISPLAY SECTION
• Has 8 output lines divided into 2 groups
A0 to A3 and B0 to B3
• These lines can be used as a group of 8
lines or 2 groups of 4 lines each in
conjunction to scan lines for display
• Display can be blanked by BD line
• Includes 16X8 display RAM
• MPU can read or write into these registers
 MPU INTERFACE SECTION
• Includes 8 bidir. Data lines (DB0-DB7), one
Interrupt Request (IRQ) and six lines for
interfacing, including buffer add line A0
• When A0 is high – control word
• When A0 is low – signals are interrupted
and they act as data lines
• IRQ goes high whenever data entries are
stored in FIFO
 8279 KEYBOARD AND DISPLAY
INTERFACING
Features:
 It is designed by Intel
 It is support 64 contact key matrix with
two more keys “CONTROL” and “SHIFT”
 It provides 3 operating modes
1.Scanned keyboard mode 2.Scanned
sensor matrix mode 3.Strobed Input mode.
 It has inbuilt debounce key .
 It provides 16 byte display RAM to display
16 digits and interfacing 16 digits.
 It provides two output modes:
1.Left entry (Typewriter type).
2.Right entry (Calculator type).
 Simultaneous keyboard and display
operation facility allows to interleave
keyboard and display software.
 The interrupt output of 8279 can be used to
tell CPU that the key press is detected, this
eliminates the need of software polling.
PIN DIAGRAM OF 8279
LOGIC SYMBOL
Cpu interface pins:
DB0-DB7 : These are bidirectional data bus
lines. The data and command words to and
from the CPU are transferred on these lines.

 RD, WR ( Input / Output ) READ/WRITE

These input pins enable the data buffers to
receive or send data over the data bus.
A0(Address lines) : A high on this line
indicates the transfer of a command or status
information. A low on this line indicates the
transfer of data. This is used to select one of
the internal registers of 8279.
 CS : Chip Select – A low on this line enables
8279 for normal read or write operations. Other
wise, this pin should remain high.
 RESET : This pin is used to reset 8279. A high on
this line reset 8279. After resetting 8279, its in
sixteen 8-bit display, left entry encoded scan, 2-
key lock out mode. The clock prescaler is set to
31.
 CLK : This is a clock input used to generate
internal timing required by 8279.
IRQ : This interrupt output lines goes high
when there is a data in the FIFO sensor RAM.
The interrupt lines goes low with each FIFO
RAM read operation but if the FIFO RAM
further contains any key-code entry to be
read by the CPU, this pin again goes high to
generate an interrupt to the CPU.
 Vss, Vcc : These are the ground and power
supply lines for the circuit.
 SL0-SL3-Scan Lines : These lines are used
to scan the key board matrix and display
digits. These lines can be programmed as
encoded or decoded, using the mode control
register.
Key board Data:
RL0 - RL7 - Return Lines : These are the input lines
which are connected to one terminal of keys, while
the other terminal of the keys are connected to the
decoded scan lines. These are normally high, but
pulled low when a key is pressed.
 SHIFT : The status of the shift input lines is stored
along with each key code in FIFO, in scanned
keyboard mode. It is pulled up internally to keep it
high, till it is pulled low with a key closure.
 CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard
mode, this lines is used as a control input and stored in
FIFO on a key closure. The line is a strobed lines that
enters the data into FIFO RAM, in strobed input mode. It
has an interrupt pull up. The lines is pulled down with a
key closer.
Display data:
OUT A0 – OUT A3 and OUT B0 – OUT B3 :
These are the output ports for two 16*4 or
16*8 internal display refresh registers. The
data from these lines is synchronized with
the scan lines to scan the display and
keyboard. The two 4-bit ports may also as
one 8-bit port.
 BD – Blank Display : This output pin is used
to blank the display during digit switching or
by a blanking closure.
Block Diagram
 It consists 4 main section.
1. CPU interface and control section.
2. Scan section
3. Keyboard Section
4. Display section.

CPU INTERFACE AND CONTROL SECTION:

It consists of
1. Data buffers
2. I/O control
3. Control and timing registers.
4. Timing and control logic.
Data Buffers:
 8-bit bidirectional buffer.
 Used to connect the internal data bus and
external data bus.

I/O control:
 I/O control section uses the A0,CS,RD and
WR signals to controls the data flow.
 The data flow is enabled by CS=0otherwise it
is the high impedance state.
 A0=0 means the data is transferred.
 A0=1 means status or command word is
transferred.
I/O control signals listed below

A0 RD WR Interpretation

0 1 0 Data from CPU to 8279

0 0 1 Data from 8279 to CPU
1 1 0 Command word from CPU to 8279
1 0 1 Status word from 8279 to CPU
TIMING AND CONTROL REGISTERS:
Store the keyboard and display modes and
others operating condition programmed by the
CPU.
The modes are programmed by sending proper
command A0=1.

TIMING AND CONTROL:

It consist timing counter chain.
First counter is divided by N prescalar that can
be programmed to give an internal frequency of
100 KHz.
The other counter is divide by basic
internal frequency .Listed below

Parameter Timings
Keyboard and time 5.1 msec
Keyboard and debounce time 10.3 msec
Key scan time 80 µ sec
Display scan time 10.3 msec
Digit ON time 480 µ sec
Blanking time 160 µ sec
Internal clock time 10 µ sec
 Scan Section
 It has two modes,
1. Encoded mode
2. Decoded mode.

ENCODED MODE:
 It provide binary count from 0000 to 1111 by
four scan lines(SC3-SC0)by active high inputs.
 It is externally decoded to provide 16 scan
lines
 Display use all 16 lines to interface 16 digit 7
segment display.
 But keyboard use only 8 scan lines out of 16
lines.

 DECODED MODE:
 In this mode ,the internal decoder decodes the
least 2 significant bits.
 It is provide four possible combination from
(SC0-SC3) such as 1110 ,1101 ,1011 and 0111.
 This four active low outputs line is used to
directly to interface 4 –digit 7-segment display ,
8*4 matrix keyboard
 Keyboard section
 This is consist of,
 Return buffers.
 Keyboard debounce control.
 FIFO / sensor RAM.
 FIFO / sensor RAM status.

RETURN BUFFERS:
 8 return lines(RL7-RL0) are buffered and
latched by when each row scan in scanned
keyboard or sensor matrix mode.
 In strobed mode ,the contents of return lines
are transferred to FIFO Ram.
KEYBOARD DEBOUNCE AND CONTROL:
 It is enabled only when keyboard mode is
selected.
 In this mode , return lines are scanned whether
any keys are closed in the row.
 If debounce circuit is detect any closed switch
it wait about 10 msec.
 It is continued , the status of SHIFT and
CONTROL keys are transferred into RAM.

 FIFO/SENSOR RAM:
 This is a dual function of 8*8 RAM.

 In scanned key board mode and Strobed input mode , It
is FIFO.
 Each new entry is written into successive RAM position
and read in the order of entry.
 In sensor matrix mode it is a sensor RAM.
 Each sensor RAM is loaded with corresponding sensor
RAM status.

 FIFO/SENSOR RAM status:

 This is used to tell the status of FIFO/SENSOR RAM.
 The status of logic also makes IRQ signal is High , When
FIFO is not empty.
 Display section:
It consists of,
1. Display RAM.
2. Display Address registers.
3. Display registers.
DISPLAY RAM:
 It is a 16*8 RAM.
 Which stores 16 digits display codes.
 It can be accessed by CPU directly.
 In Decoded mode,8279 uses only first four location of
Display RAM.
 In Encoded mode,8279 uses only first eight location of
Display RAM.
 And all 16 location for 16 digits display.
DISPLAY ADDRESS REGISTERS:
 Used to hold address of the byte currently
write or read by the CPU and scan count
value.
 In auto increment mode, address in the
register is automatically incremented for
each write or read.
DISPLAY REGISTERS:
 It is a Two 4-bit registers such as , A and B.
 They hold the bit patterns of character to be
displayed.
 The content of display registers A and B can
B blanked and inhibited individually.
 Operating modes
• It is two types,
1. Input modes.
2. Display modes.
INPUT MODES:
 It is basically 3 types,
1. Scanned keyboard.
2. Scanned sensor matrix.
3. Strobed mode.
SCANNED KEYBOARD:
Key board can be scanned in two ways.
1.Encoded Scan 2.Decoded Scan.
ENCODED SCAN:
 In this scan, scan lines (SL2-SL0) are
encoded externally to provide 8 scan lines.
 Additionally it provides 8 return lines.
 So the size of matrix keyboard is 8*8 (i.e
Scan * Return)=64.
 When the key is pressed , it is stored the
status of return lines , Scan lines ,SHIFT and
CNTL/STB keys into FIFO RAM.
B
7 B
6 5B B4 B
3 B
2 B
1 B
0

 The Scanned
CNTL SHIFTkeyboard
SCAN structure
RETURN is,
Example:
 Find the key code for given condition below:
CNTL/STB SHIFT keys are open.
The pressed keys are to scan lines 2 and
return lines 4.
SOLUTION:
B7 B6 B5 B4 B3 B2 B1 B0
1 1 0 1 0 1 0 0
 CNTL=1
 SHIFT=1
 Scan mode=010 (Scan line 2)
 Return mode=100 (Return line 4)
 Key code =D4 H
DECODED SCAN:
 In this mode ,internal decoder decodes the least
significant bits of scan lines (SC3-SC0).
 That is provide the four combination such as 1110,
1101,1011 and 0111.
 So the maximum size of keyboard is 8*4=32.
 The key code is similar to encoded code , only bit 5
(B5) is always zero.
2-KEY LOCKOUT:
 In this mode, the two key depression is not
allowed.
 When any key is depressed, the debounce logic
is set and 8279 checks for any key depress
next two scans.
 Three possible condition to avoid debouncing:
 Condition 1:
 If other key depression is not found during next
two scan, it is a single key is depressed .Then
the status of key code is entered into FIFO RAM
along with the status of CNTL and SHIFT lines
 If FIFO RAM is empty , The CPU is entry the
data.
 If FIFO RAM is full , The CPU does not entry
the data.
Condition 2:
 If any other key depress is encountered , no
entry to the FIFO can occur.
 When the key is released after that only Entry
will be allowed.
Condition3:
 If the two key is pressed in simultaneously in
a debounce cycle, both depression is not
considered.
• N-KEY ROLLOVER:
 Each key is depression is treated as
independently from all others.
SCANNED SENSOR MATRIX:
 In this mode , image of the sensor matrix is
kept in the sensor RAM.
 The status of sensor switches are input directly
to the sensor RAM.
 8279 scans row one by one and store the
status of each row in the corresponding
memory location.
 STROBED INPUT MODE:
 The data is entered from Returned lines.
 Display modes:
• It is basically two types,
1. Left entry (Type writer mode).
2. Right entry (Calculator mode).
LEFT ENTRY:
 In this mode , 8279 display characters from
left to right.
 Like a typewriter.
AUTOINCREMENT IN LEFT ENTRY:
 In left entry mode , Autoincrement flag is set
after each operation display RAM address is
incremented.
RIGHT ENTRY:
 In this mode , 8279 display characters
from Right to left.
 Like a Calculator.
AUTOINCREMENT IN RIGHT ENTRY:
 In right entry mode , Auto increment flag
is set after each operation display RAM
address is incremented.
Interfacing stepper motor with
8085
 Stepper motor
• A stepper motor is an electromechanical device which converts
electrical pulses into discrete mechanical movements. The shaft or
spindle of a stepper motor rotates in discrete step increments when
electrical command pulses are applied to it in the proper sequence.

• The sequence of the applied pulses is directly related to the

direction of motor rotation. The speed of the motor’s shaft is
directly related to the frequency of the input pulses; and the length
of rotation is directly related to the number of input pulses applied.

• One of the most significant advantages of a stepper motor is its

ability to be accurately controlled in an open loop system. This type
of control eliminates the need for expensive sensing and feedback
devices such as optical encoders. Its position is known simply by
keeping track of the input step pulses.
 Application

Because of the inherent advantages,

stepper motors have found their place in
many different applications.
Some of these include:
printers, plotters, high end office
equipment, hard disk drives, medical
equipment, fax machines, machine tools,
automotive devices and many more
HARDWARE FOR STEPPER MOTOR
CONTROL
• A stepper motor is a digital motor. It can be driven by
digital signal. Fig. shows the typical 2 phase motor
rated 12V /0.67 A/ph interfaced with the 8085
microprocessor system using 8255. Motor shown in
the circuit has two phases, with center-tap winding.
The center taps of these windings are connected to the
12V supply. Due to this, motor can be excited by
grounding four terminals of the two windings. Motor
can be rotated in steps by giving proper excitation
sequence to these windings. The lower nibble of port A
of the 8255 is used to generate excitation signals in
the proper sequence. These excitation signals are
buffered using driver transistors. The transistors are
selected such that they can source rated current for
the windings. Motor is rotated by 1.80 per excitation.
SOFTWARE FOR STEPPER MOTOR
CONTROL
As port A is used as an output port, control word for 8255
is 80H.

Stepper Motor Control Program:

6000H Excite code 03H, 06H,

09H, OCH : This is the code
sequence for clockwise rotation

Subroutine to rotate a stepper motor clockwise by 360° -

Set the counts:
MVI C, 32H : Set repetition count to 50ıο
START: MVI B, 04H : Counts excitation sequence
LXI H, 6000H : Initialize pointer
BACK1: MOV A, M : Get the Excite code
OUT PORTA : Send Excite code
CALL DELAY : Wait
INX H : Increment pointer
DCR B : Repeat 4 times
JNZ BACK l
DCR C
JNZ START : Repeat 50 times
RET Memory Address Excite Code
INTERFACING SCHEME 6000H 03H
Delay subroutine:
6001H 06H
Delay: LXI D, Count
6002H 09H
Back: DCX D
MOV A, D 6003H 0CH
ORA E
JNZ Back
RET
Main program
Motor subroutine
Delay subroutine
Traffic light contol with 8085
Layout
LED PORTS
 Description
• 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to
control lights on W-E road.
• The electric bulbs are controlled by relays.
The 8255 pins are used to control relay on-
off action with the help of relay driver
circuits. The driver circuit includes 12
transistors to drive 12 relays.
Interfacing
Initialize PPI
PORT ADDRESS
Port output addresses
 Program
Source Program 1:
MVI A, 80H : Initialize 8255, port A and port B
OUT 83H ;(CR) : in output mode
START: MVI A, 09H
OUT 80H; (PA) : Send data on PA to glow R1 and R2
MVI A, 24H
OUT 81H; (PB) : Send data on PB to glow G3 and G4
MVI C, 28H : Load multiplier count (40ıο) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT 80H; PA : Send data on Port A to glow Y1 and
Y2
OUT 81H ;PB : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
CALL: DELAY : Call delay subroutine
MVI A, 24H
OUT 80H ;PA : Send data on port A to glow G1 and G2
MVI A, 09H
OUT 81H; PB : Send data on port B to glow R3 and R4
MVI C, 28H : Load multiplier count (40ıο) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT 80H : Send data on port A to glow Y1 and Y2
OUT 81H : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
CALL DELAY : Call delay subroutine
JMP START
Delay Subroutine:
DELAY: LXI D, Count : Load count to give 0.5 sec delay
BACK: DCX D : Decrement counter
MOV A, D
ORA E : Check whether count is 0
JNZ BACK : If not zero, repeat
DCR C : Check if multiplier zero, otherwise repeat
JNZ DELAY
RET : Return to main program
THANK YOU