NETAJI SUBHAS ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ANALOG & DIGITAL ELECTRONICS LABORATORY ESC- 391
EXPERIMENT NO- 01
TITLE: Realization of different logic gates using NAND Gate
OBJECT: Realization of truth table of different logic gates using NAND Gate
EQUIPMENT & COMPONENT REQUIED
SL NO NAME SPECIFICATION
1. IC 7400 Quad 2 i/p NAND Gate
2. Bread Board -
3. Power Supply 5v/1A, DC Regulated, fixed
4. Connecting Wires Single strand wire
5. LED 2v, 10 mA
6. Resistance 1kΩ, ¼ w
THEORY: Various Boolean operations of binary data are performed by logic gates. The
important logic operation frequently performed in the design of digital systems are AND, OR,
NOT, NAND, NOR, EX-OR, EX-NOR. The NAND & NOR are called universal gates as all the
primary functions can be realized with them.
NAND GATE: A NAND gate has two or more inputs and only one output .The NAND
operation is given Y=A.B and NAND operation is called “Universal Operation”
SYMBOL:
I/P State I/P State O/P State
Truth Table
0 0 1
Circuit Diagram:
0 1 1
1 0 1
1 1 0
NOT GATE: It has only one input and one output. Its output is the compliment of the input i.e. Y= Ā
So NOT gate is called an INVERTER
SYMBOL:
Truth Table I/P State O/P State
0 1
1 0
Circuit Diagram:
OR GATE: An OR gate has two or more inputs but only one output. The output of an OR gate
will be high if at least one of the inputs is high and is low when all the inputs are low. Boolean
expression of OR is Y= A+B
SYMBOL:
Truth Table I/P State I/P State O/P State
Circuit Diagram: 0 0 0
0 1 1
1 0 1
1 1 1
AND GATE: AND gate output will be zero if any one of the inputs is zero. Output will be high
if all the input is high. Boolean expression of AND is given by, Y=A.B
SYMBOL:
Truth Table
Circuit Diagram: I/P State I/P State O/P State
0 0 0
0 1 0
1 0 0
1 1 1
EX-OR GATE: The output of XOR gate is high only when its input is different. Its output is
low when both inputs A& B are same .It’s output is given by Y= A B
SYMBOL:
I/P State I/P State O/P State
Truth Table 0 0 0
Circuit Diagram: 0 1 1
1 0 1
1 1 0
EX-NOR GATE: Ex-NOR function is equivalent to complement of Ex-OR function. The
output of XNOR is high only when its input is same. Its output is low when both inputs A& B
are same i.e. Y= A B
SYMBOL:
I/P State I/P State O/P State
Truth Table
0 0 1
Circuit Diagram: 0 1 0
1 0 0
1 1 1
NETAJI SUBHAS ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ANALOG & DIGITAL ELECTRONICS LABORATORY ESC-391
EXPERIMENT NO- 02
TITLE: Construction of simple Decoder circuit using Logic Gates
OBJECT: To realize the simple Decoder circuit using Logic Gates
EQUIPMENT & COMPONENT REQUIED
SL NO NAME SPECIFICATION
1. IC 7404 Hex inverter Gate
2. IC 7408 Quad 2i/p AND Gate
3. Bread Board -
4. Power Supply 5v/1A, DC Regulated, fixed
5. Connecting Wires Single strand wire
6. LED 2v, 10 mA
7. Resistance 1k, 1/4w
THEORY: Decoder is a combinational circuit that converts binary information from n i/p lines
to a maximum of 2n unique o/p lines. For a n to m line Decoder we can write m=2n , provided the
n bit decoded information has no don’t care condition.
Circuit Diagram:
Truth Table
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
NETAJI SUBHAS ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ANALOG & DIGITAL ELECTRONICS LABORATORY ESC-391
EXPERIMENT NO- 03
TITLE: Design of 4×1 Multiplexer circuit using logic gates
OBJECT: To realize the 4 ×1 Multiplexer circuit using logic gates
EQUIPMENT & COMPONENT REQUIED
SL NO NAME SPECIFICATION
1 IC 7404 Hex inverter Gate
2. IC 7408 Quad 2i/p AND Gate
3. IC 7432 Quad 2i/p OR Gate
4. Bread Board -
5. Power Supply 5v/1A, DC Regulated, fixed
6. Connecting Wires Single strand wire
7. LED 2v, 10 m/a
8. Resistance 1k, 1/4w
THEORY: Multiplexer means transmitting a large no of information units over a smaller no of
channels or lines. Digital multiplexer is a combinational circuit that selects one binary
information from many i/p lines and directs to a single o/p line.
Circuit Diagram:
Truth Table
A B O/P
0 0 D0
0 1 D1
1 0 D2
1 1 D3
NETAJI SUBHAS ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ANALOG & DIGITAL ELECTRONICS LABORATORY ESC-391
EXPERIMENT NO- 04
TITLE: Design and implementation of Full Adder using logic gates.
OBJECT: To study the Circuit of Full Adder using logic gates.
EQUIPMENT & COMPONENT REQUIED
SL NO NAME SPECIFICATION
1. IC 7408 Quad 2i/p AND Gate
2. IC 7432 Quad 2i/p OR Gate
3. IC 7486 Quad 2i/p X OR Gate
4. Bread Board -
5. Power Supply 5v/1A, DC Regulated, fixed
6. Connecting Wires Single strand wire
7. LED 2v, 10 m/a
8. Resistance 1k, 1/4w
THEORY: A Full Adder is a combinational circuit that performs the arithmetic sum of three
input bits. It consists of three i/p s and two o/ps.
Truth Table
X Y Z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The Boolean Expression for the Sum and Carry are as follows:
S=XY׳Z׳+X׳YZ׳+X׳Y׳Z+XYZ
=(XY׳+X׳Y)Z׳+(X׳Y׳+XY)Z
=(XY)Z׳+( XY)׳Z
= XYZ
C=XY ׳Z+X׳YZ+XYZ+XYZ׳
=(XY׳+X׳Y)Z+XY(Z+Z)׳
==(XY)Z+XY
Circuit Diagram Of Full Adder:
NETAJI SUBHAS ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ANALOG & DIGITAL ELECTRONICS LABORATORY ESC-391
EXPERIMENT NO- 05
TITLE: Realization of RS-JK & D Flip Flops using universal logic gates
OBJECT: To Realize the RS-JK & D Flip Flops using universal logic gates
EQUIPMENT & COMPONENTS REQUIED
SL NO NAME SPECIFICATION
1. IC 7400 Quad 2 i/p NAND Gate
2. IC 7408 Quad 2 i/p AND Gate
3. IC 7404 Hex Inverter
4. Connecting Wires Single strand wire
5. Resistor 1k
6. LED 2V,10mA
7. Power Supply 5V/1A DC Regulated
8. Pulse Generator 20 MHz
Theory:
Flip-Flop:-The Flip-Flop is a basic memory element. A Flip-Flop is basically a bistable
multivibrator. It has two stable states. One of the States is known as SET or 1, where as the other
stable state is called RESET or 0. Normally there are two input terminals and two output
terminals. The outputs Q and Q are complementary, i.e. at any of time if Q=0, then Q=1 and
vice versa.
RS Flip-Flop:-The RS Flip-Flop is the Basic flip-flop. The block diagram and truth table of the
RS flip flop is given in the figure. This is a memory cell. The output Q is 1, if S=1 and R-0. Now
if S is removed the output Q still remains1. That means it memorizes a 1. Similarly it can
memorize a 0.
Block Diagram of RS Flip-Flop
Circuit Diagram of RS Flip-Flop Truth Table
Inputs Output
S R Q
0 0 0 or 1
0 1 0
1 0 1
1 1 Not used
D Flip Flop:- The RS Flip-Flop has two inputs , R & S . To store a high bit we need a highs to
store a low bit we need a high R. Further the forbidden condition of both R & S may occur
inadvertently. This has led to the D flip flop, a circuit that needs only one data input.
The following figure shows a simple way to build a delay D flip flop. This configuration
prevents the value of D from reaching the Q output until a clock pulse occurs.
When the clock is low, low both AND gates are disabled. So D can change values without
affecting the value of Q On the other hand when the clock is high both AND gates are enabled.
In this case Q is forced to equal the value of D. When the clock again low Q retains the last value
of D
Block Diagram of D Flip Flop
Circuit Diagram of D Flip flop Truth Table
Clk D Q
0 X Last state
0 0
1 1
JK Flip Flop:-The following figure shows how to build a JK flip flop. The variables J&K are
called controls inputs because they determine what the flip flop does when a positive clock edge
occurs. Because of AND gates the circuit is +ve edge triggered .When J & K are both low both
AND gates are disabled. So the clock pulses have no effect. Here Q retains the last value.
When J is low K is high the upper AND gate is disabled. So there is no way to set the F/F. The
only alternate is to reset the F/F. If Q is high the lower AND gate passes a reset trigger as soon as
the next positive clock arrives. That makes Q to become low.
When J is high, K is low the lower AND gate is disabled. So it is disabled. So it is impossible to
reset the F/F. At this time if Q is low i.e. Q is high then the upper AND gate passes a trigger
state. This makes Q=1 on the arrival of next clock pulses
When J & K are both high, it is possible to set or reset the F/F . If Q is high the lower gate passes
a reset trigger on the +ve clock edge. So Q become 0.On the other hand if Q is low the upper
gate passes a state trigger on the +ve clock edge. So Q becomes 1. Either way Q changes to the
complement of the last state. Therefore J-1 and K=1means the F/F will toggle on the next +ve
clock edge “Toggle” means to switch to the opposite state.
Circuit Diagram of JK Flip flop Truth Table
Inputs Output
J K Last State
0 0 0
0 1 0
1 0 1
1 1 Toggle
NETAJI SUBHASH ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ECE 2ND YEAR 3RD SEM 2021-2022
ANALOG & DIGITAL ELECTRONICS LABORATORY (ESC-391)
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