25 SystemVerilog Snippet-Based Problems
1. Logic vs Reg Behavior
module test;
logic a;
reg b;
initial begin
a = 1'b1;
b = 1'b1;
a = a + 1;
b = b + 1;
$display("a=%b b=%b", a, b);
end
endmodule
Q: What will be printed, and why does `logic` behave differently from `reg` here?
2. Blocking vs Non-Blocking
module test;
reg x = 0, y = 0;
initial begin
x = 1;
y <= x;
$display("%0d %0d", x, y);
end
endmodule
Q: What will be displayed, and why?
3. Static Variable Persistence
module test;
task counter;
static int count = 0;
count++;
$display("Count=%0d", count);
endtask
initial begin
counter();
counter();
end
endmodule
Q: What will `count` display in each call and why?
4. Packed vs Unpacked Arrays
module test;
bit [3:0] packed;
bit unpacked[3:0];
initial begin
packed = 4'b1010;
unpacked = '{1,0,1,0};
$display("%b %p", packed, unpacked);
end
endmodule
Q: How will packed and unpacked arrays print differently?
5. Default Random Values
module test;
bit [3:0] x;
initial $display("%b", x);
endmodule
Q: What value will `x` have at simulation start?
6. Randomize with Constraint
class RandEx;
rand int a;
constraint c1 { a inside {[1:5]}; }
endclass
module test;
initial begin
RandEx r = new();
r.randomize();
$display("%0d", r.a);
end
endmodule
Q: What are the possible values for `a`?
7. Associative Array Iteration
module test;
int arr[string];
initial begin
arr["apple"] = 1;
arr["banana"] = 2;
foreach(arr[k])
$display("%s=%0d", k, arr[k]);
end
endmodule
Q: In what order will keys print?
8. Queue Methods
module test;
int q[$] = {1, 2, 3};
initial begin
q.pop_front();
q.push_back(4);
$display("%p", q);
end
endmodule
Q: What will the queue contain at the end?
9. String Concatenation
module test;
string s = "Hello";
initial begin
s = {s, " SV"};
$display("%s", s);
end
endmodule
Q: What will be displayed?
10. Inside Operator
module test;
initial $display("%0d", (3 inside {[1:5]}));
endmodule
Q: What does this return, and why?
11. Priority if
module test;
int x = 3;
initial begin
priority if (x == 3) $display("Three");
else if (x > 0) $display("Positive");
end
endmodule
Q: What gets printed?
12. Unique Case
module test;
int x = 2;
initial begin
unique case (x)
1: $display("One");
2: $display("Two");
3: $display("Three");
endcase
end
endmodule
Q: Why use `unique` here, and what happens if multiple cases match?
13. Default Clocking Block
module test;
logic clk = 0;
default clocking cb @(posedge clk);
endclocking
endmodule
Q: What is the purpose of `default clocking` in testbenches?
14. Immediate Assertion
module test;
initial assert (2+2 == 4) else $fatal("Math error");
endmodule
Q: What will happen during simulation?
15. Concurrent Assertion
property p1;
@(posedge clk) a |=> b;
endproperty
assert property(p1);
Q: What does this property check?
16. Enum Auto Increment
module test;
typedef enum {RED, GREEN=5, BLUE} colors;
initial $display("%0d %0d %0d", RED, GREEN, BLUE);
endmodule
Q: What values will be printed?
17. Casting
module test;
int a = 65;
initial $display("%s", string'(a));
endmodule
Q: What will this print?
18. Covergroup Sampling
module test;
int x;
covergroup cg;
coverpoint x;
endgroup
initial begin
cg c = new();
x = 5; c.sample();
end
endmodule
Q: When does the covergroup sample the variable?
19. Class Handle Copy
class A;
int data;
endclass
module test;
initial begin
A obj1 = new();
obj1.data = 10;
A obj2 = obj1;
obj2.data = 20;
$display("%0d %0d", obj1.data, obj2.data);
end
endmodule
Q: Why do both objects print the same value?
20. Constant Variable
module test;
const int x = 10;
initial begin
// x = 20; // Uncommenting this causes?
end
endmodule
Q: What error happens if you uncomment the line?
21. Random Stability
module test;
initial begin
$urandom_range(0,5);
$display("%0d", $urandom_range(0,5));
end
endmodule
Q: Why might results differ each simulation?
22. Mailbox Communication
module test;
mailbox m = new();
initial begin
fork
m.put(5);
m.get(val);
join
end
endmodule
Q: What is the purpose of a mailbox in SV?
23. Parameter Override
module test #(parameter WIDTH=8);
logic [WIDTH-1:0] data;
endmodule
module top;
test #(.WIDTH(16)) t1();
endmodule
Q: What is the size of `data` in `t1`?
24. Generate For Loop
module test;
genvar i;
generate
for (i=0; i<4; i++) begin : blk
initial $display("Instance %0d", i);
end
endgenerate
endmodule
Q: How many instances will be created?
25. Cross Coverage
covergroup cg;
coverpoint a;
coverpoint b;
cross a, b;
endgroup
Q: What is the purpose of cross coverage?
