(20A04602P) VLSI DESIGN LAB
Course Outcomes:
Design any logic circuit using CMOS transistor.
Use different software tools for analysis of circuits.
Design layouts to the CMOS circuits.
Use different software tools for analog layout
List of Experiments:
1. Design and analysis of CMOS Inverter
a) Implement CMOS inverter schematic using 180 nm technology and design its symbol.
b) Implement test bench for CMOS Inverter and check its output response.
c) Perform DC and AC analysis for CMOS inverter.
d) Check the performance of CMOS inverter using parametric sweep.
2. Design and analysis of NAND and NOR Logic gates
a) Implement NAND/NOR schematic using 180 nm technology and design its symbol.
b) Implement test bench for NAND/NOR and check its output response.
c) Perform DC and AC analysis for NAND/NOR.
d) Check the performance of NAND/NOR using parametric sweep.
3. Design and analysis of XOR and XNOR Logic gates
a) Implement XOR/XNOR schematic using 180 nm technology and design its symbol.
b) Implement test bench for XOR/XNOR and check its output response.
c) Perform DC and AC analysis for XOR/XNOR.
d) Check the performance of XOR/XNOR using parametric sweep.
4. Design of AOI logic
a) Design Schematic for AB+C‘D and check its output response.
b) Design Schematic for AB‘+C‘D and check its output response.
c) Design Schematic for (A+B‘)(C+D) and check its output response.
d) Design Schematic for (A+B‘)(C‘+D) and check its output response.
5. Design and analysis of Full adder
a) Design full adder using Full custom IC design.
b) Design full adder using Semi custom IC design.
6. Analysis of NMOS and PMOS characteristics
a) Implement test bench for NMOS/PMOS transistor.
b) Perform DC and AC analysis for NMOS/PMOS transistor
c) Check the performance of NMOS/PMOS transistor using parametric sweep.
7. Design and analysis of Common source amplifier
a) Implement CS amplifier schematic using 180 nm technology and design its symbol.
b) Implement test bench for CS amplifier and check its output response.
c) Perform DC and AC analysis for CS amplifier.
d) Check the performance of CS amplifier using parametric sweep.
8. Design and analysis of Common drain amplifier
a) Implement CD amplifier schematic using 180 nm technology and design its symbol.
b) Implement test bench for CD amplifier and check its output response.
c) Perform DC and AC analysis for CD amplifier.
d) Check the performance of CD amplifier using parametric sweep.
9. Design of MOS differential amplifier
a) Design differential amplifier schematic using 180 nm technology and its symbol.
b) Implement test bench for differential amplifier and check its output response.
c) Perform DC and AC analysis for differential amplifier.
d) Check the performance of differential amplifier using parametric sweep.
10. Design of two stage differential amplifier
a) Design two stage differential amplifier schematic using 180 nm technology and its symbol. b)
Implement test bench for two stage differential amplifier and check its output response.
c) Perform DC and AC analysis for two stage differential amplifier.
d) Check the performance of two stage differential amplifier using parametric sweep.
11. Design of Inverter Layout
a) Design and implement inverter schematic.
b) Design the layout for inverter using 180 nm tech file.
c) Perform LVS for schematic and layout
d) Check and remove all DRC violations.
e) Extract parasitic R and C in layout.
12. Design of NAND/NOR Layout
a) Design and implement NAND/NOR schematic.
b) Design the layout for inverter using 180 nm tech file.
c) Perform LVS for schematic and layout
d) Check and remove all DRC violations.
e) Extract parasitic R and C in layout
Note: Any TEN of the experiments are to be conducted
The students are required to design the schematic diagrams using CMOS logic and to draw the layout
diagrams to perform the experiments with the Industry standard EDA Tools.
Software Required: i. Mentor Graphics Software / Equivalent Industry Standard Software. ii. Personal
computer system with necessary software to run the programs and to implement.
Parametric Analysis We can also plot Id Vgs characteristics for more than one value of Vds on the
same graph at the same time. Such plots can be achieved by parametric analysis. Let us consider
that we wish to plot the below given graph. We have Vgs on the X Axis and Id on the Y Axis. Each
curve on the plot is for different values of Vds. Therefore we select vgs as the sweep variable in dc
analysis and vds as the variable of parametric analysis. Just like earlier, from analog environment,
we select vgs voltage source in component parameter sweep in DC Analysis. Sweep it from 0 to
1.8V. Select the drain terminal of the transistor as the current plot. 13 Then from Analog
Environment window, we select Tools > Parametric. This will open up a new window as shown
below. .. we fill up the above window as shown. Note that the variable name “vds” is same as the
variable name given to the dc voltage value of the voltage source which applies the vds of the
transistor. To eliminate variable name errors, in this window, choose Setup > Variable name >
sweep 1. Then select vds as the parametric sweep variable. Give in the range and the number of
steps as shown above. Then click Analysis > Start. Simulation will run, and the above shown graph
for Id Vs. Vgs for various vds will be plotted.
