Physical Design Training Syllabus (Beginner Level)
1. Linux Commands
Hands-on training with Linux commands essential for EDA tool usage and
automation.
2. TCL Scripting
Introduction to TCL (Tool Command Language).
Writing basic scripts for automation in physical design tools.
Practical exercises for commonly used commands.
3. CMOS Basics
Overview of CMOS design principles.
Basic concepts of transistors, gates, and logic design.
4. Synthesis
Introduction to synthesis and its purpose in physical design.
Synthesis flow overview.
Constraining designs for timing, area, and power.
Understanding timing library (.lib) format.
Hands-on synthesis of a basic design.
Analyzing and debugging synthesis reports.
Basic optimization techniques.
5. Timing Constraints
Introduction to timing constraints.
Go through the important timing constraints.
Setting and analyzing constraints for setup and hold timing.
Basic hands-on timing analysis exercises.
6. Floorplanning
Goals of floorplanning.
Basic concepts of area estimation (square/rectangle/rectilinear floorplans).
IO and macro placement.
Introduction to congestion estimation.
Simple floorplanning exercises with predefined constraints.
7. Power Planning
Basics of power structure design.
Logical power/ground connections.
Creating and analyzing simple power networks.
Introduction to IR drop analysis.
Hands-on exercise to create power rails and run basic checks.
8. Placement
Goals and types of placement.
Pre-placement: End-cap, tap, and IO buffer cells.
Introduction to standard cell placement.
Basic congestion analysis and reduction techniques.
Hands-on exercises for placement strategies.
9. Routing
Introduction to routing and its types (global, detailed).
Inputs and outputs of routing.
Basic signal routing tasks.
Congestion checks and RC extraction for net parasitics.
Hands-on exercises for simple routing tasks.
10. Power Analysis
Introduction to static and dynamic power dissipation.
Basics of leakage power analysis.
VT cell swapping for power and timing trade-offs.
Hands-on dynamic power calculation using sample data.
11. Clock Tree Synthesis (CTS)
What is CTS and its goals?
Basics of clock tree structures and specifications.
Setting simple clock constraints such as skew and insertion delay.
Hands-on exercise: Building and analyzing a basic clock tree.
12. Engineering Change Order (ECO) Flow
Introduction to ECO and its importance.
Basic types of ECO: Functional and timing.
Flattened ECO flow overview.
Hands-on debugging of simple ECO flows.
13. Physical Design Verification
Introduction to design rule checks (DRC) and their importance.
Basics of layout vs. schematic (LVS).
Electrical rule checks and their role.
Static IR drop analysis.
14. Industry Standard Projects
Guided projects covering the complete flow from input files to GDSII, including:
o Synthesis.
o Floorplanning.
o Power planning.
o Placement.
o Routing.
o Static timing analysis (STA).
o Physical verification (DRC and LVS).
Additional Enhancements for Beginner-Level Students:
1. EDA Tool Familiarization
o Overview of tools such as Synopsys Design Compiler and Cadence Innovus.
o Basic navigation and usage.
2. Low-Power Design Basics
o Introduction to concepts like multi-Vt and power gating.
o Simple exercises to understand trade-offs.
3. Soft Skills for Collaboration
o Guidelines for teamwork in physical design projects.
o Best practices for documentation and reporting.
o Simple examples integrated into the physical design flow.
4. Real-World Case Studies
o Beginner-friendly case studies highlighting hierarchical vs. flat design trade-
offs.
o Examples of clock domain crossing issues and resolutions.
