IEEE - 61001

DESIGN OF 32 BIT RISC V PROCESSOR

2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT) | 979-8-3503-7024-9/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICCCNT61001.2024.10726132

Meeradevi T Mohanraj K Mourissh B M

Department of ECE, Department of ECE, Department of ECE,
Kongu Engineering College, Kongu Engineering College, Kongu Engineering College,
Perundurai, Erode, India Perundurai, Erode, India Perundurai, Erode, India
meeradevi@kongu.ac.in mohanrajk.20ece@kongu.edu mourisshbm.20ece@kongu.edu

Santhosh Sivaa V Ravi Samikannu S.Sasikala

Department of ECE, Department of Electrical Computer Department of ECE
Kongu Engineering College, and Telecommunications Engineering Kongu Engineering College
Perundurai, Erode, India International University of Science and Perundurai, Erode, India
santhoshsivaav.20ece@kongu.edu Technology, Palapye sasikalas@kongu.ac.in

Abstract—This paper presents the design and the foundational framework, encompassing the
implementation of a RISC-V processor core with initial 37 instructions from the base instruction set.
a single-stage architecture, focusing on the This endeavor stands as a testament to the intricate
execution of the base 32I instruction set. The interplay between hardware design, assembly
processor core features a 32-bit address and data language, and simulation technologies. The
architecture, with 32 general-purpose registers processor core design is executed in Verilog, a
for data manipulation. The design adheres hardware description language, with the
strictly to the RISC-V ISA specifications, customasm assembler providing flexibility and
ensuring compatibility with existing software and customizability. Simulation is facilitated through
toolchains. Key components of the processor core EDA playground and Verilog, while the Digital
include a fetch unit, decode unit, ALU unit, open-source logic designer and simulator serve as
register file, memory control unit, and instruction the principal platform for comprehensive testing.
memory unit. Through rigorous design and
simulation, the processor core achieves single- The core architecture shuns the complexities of
clock-cycle execution, enabling efficient a pipelined structure, opting for a straight forward
processing of instructions at an operating approach of executing a single instruction per
frequency of 2.2 KHz.The instruction memory cycle. Memory management is bifurcated into
unit facilitates the retrieval of instructions from a separate 32-bit addressable spaces for program and
4.5 KB memory array, while simultaneous read data, each serviced by dedicated buses to optimize
and write capabilities are supported for both data transfer efficiency. Decoding instructions is a
registers and data memory. Additionally, 13 pivotal task handled by a dedicated decoder, which
pseudo-instructions have been incorporated to identifies instruction types based on the opcode.
enhance programming ease and readability. The subsequent routing of instructions to specific
Performance evaluation of the processor core decoders ensures precise control signal generation
demonstrates its effectiveness in executing a and data retrieval from registers and memory.
variety of computational tasks, showcasing its Execution units, in turn, manipulate the acquired
reliability and efficiency within the specified data to compute results, which are then written
operational parameters. The design serves as a back to registers or memory, as dictated by the
foundation for future enhancements, including instruction.
the integration of pipeline architecture, branch
prediction mechanisms, and frequency II. LITERATURE REVIEW
optimization.
Andrew Waterman [10] discussed about the
Keywords—PUF, Modeling attacks, Vulnerability, RISC-V Instruction Set Manual is a foundational
Enhanced Security, Unpredictable responses document that outlines the principles and design
goals of the RISC-V instruction set architecture
I.INTRODUCTION (ISA). Published by a team from the University of
California at Berkeley, serves as a comprehensive
This In the realm of processor architecture, this guide for computer architecture research and
project delves into the meticulous design and education. The RISC-V ISA is characterized by its
realization of a 32-bit processor core adhering to open nature, simplicity, and efficiency, aiming to
the RISC-V 32I ISA. The RISC-V architecture, provide a realistic yet open ISA suitable for various
known for its simplicity and versatility, serves as microarchitecture styles and implementation

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technologies. It supports both 32-bit and 64-bit Architecture" that delves into the evolution of the
address spaces, highly-parallel multicore ARM reduced-instruction-set computing (RISC)
implementations, and an efficient instruction processor, which has advanced to encompass a
encoding scheme with variable-length instructions. range of chips, including multiprocessors. The
Additionally, the manual highlights the support for ARM architecture has adapted to meet the
the revised IEEE 754 floating-point standard and escalating demands for performance in embedded
emphasizes the importance of being fully applications, incorporating new technologies to
virtualizable. enhance efficiency. Throughout its development,
Diefendorff [1] proposed the AltiVec ARM has employed various techniques to exploit
extension to the PowerPC architecture, known as parallelism effectively, such as variable execution
the Velocity Engine by Apple is used to enhance time, subword parallelism, digital signal processor-
multimedia processing performance in future PCs. like operations, thread-level parallelism, exception
This extension is a SIMD (single-instruction, handling, and multiprocessing. By leveraging
multiple-data) addition to general-purpose parallelism at multiple levels, ARM's innovative
processors, specifically designed to cater to chip designs have the potential to revolutionize
multimedia-rich applications like audio and video technology accessibility. With over 1.5 billion
compression, image processing, 3D graphics, ARM processors sold annually and a rapidly
speech recognition, and more. Unlike other expanding market, software developers now have
extensions that overload floating-point registers for extensive opportunities to deploy ARM code across
multimedia data, AltiVec introduces a dedicated diverse sectors.
large register file exclusively for multimedia data, Zhang [13] conducted an in-depth examination of
treating it as first-class data in the form of vectors. the RISC-V Instruction Set Architecture (ISA),
The design of AltiVec prioritizes high functionality emphasizing its adaptability and scalability. They
over backward compatibility, aiming to stressed the crucial role of comprehending ISA
significantly boost processing speed in critical specifications in the context of optimizing
loops that handle large input data sets commonly microarchitecture design. By elucidating the
found in signal and image processing applications. flexibility and extensibility of the RISC-V ISA, the
The AltiVec extension's capabilities include a full- study underscored how designers can tailor
range data-type support, a four-operand instruction sets to suit diverse application needs.
nondestructive instruction format, powerful SIMD Additionally, the authors emphasized the necessity
instruction set, and efficient data reorganization of aligning microarchitectural features with the
capabilities like permute operations. Overall, intricacies of the RISC-V ISA, illustrating how a
AltiVec's advancements enable media-rich deep understanding of ISA specifications informs
applications to run efficiently on general-purpose decisions regarding pipeline structure, instruction
PowerPC microprocessors without the need for scheduling, and memory management. In summary,
specialized media processors or dedicated hardware the study highlights the symbiotic relationship
accelerators. between ISA specifications and microarchitecture
John M. Frankovich [11] developed the design, showcasing the significance of a
Lincoln TX-2 computer, built at the Massachusetts comprehensive approach to processor optimization.
Institute of Technology Lincoln Laboratory, is a A novel pipeline architecture tailored for 32-bit
large-scale digital computer that incorporates new RISC-V microprocessors, with a specific emphasis
memory and circuit components along with on enhancing performance through optimized
innovative logical design concepts. This computer instruction scheduling. Their proposal underscored
is intended for use as a research tool in scientific the critical role of microarchitectural optimizations
computations, data-handling, and real-time in achieving efficient processor designs. By
applications, reflecting both the available prioritizing instruction scheduling within their
components and the intended application. The TX-2 pipeline architecture, the authors aimed to minimize
is part of a series of experimental computers pipeline stalls and maximize instruction throughput,
developed at the Lincoln Laboratory, emphasizing thereby improving overall processor performance.
large-scale digital systems suitable for real-time The study highlights the importance of fine-tuning
control. It builds upon its predecessors, Whirlwind I microarchitectural features to harness the full
and the Memory Test Computer, by introducing potential of RISC-V microprocessors, ultimately
new developments in components, circuits, contributing to the development of more efficient
memories, and logical organization. The input- computing systems[2].
output system of the Lincoln TX-2 computer is Key challenges in the design of RISC-V
designed with various devices suitable for research microprocessors, including concerns related to
and control applications, allowing multiple input- power efficiency, security, and the accommodation
output devices to operate simultaneously. of emerging workloads are addressed in [3][7]. To
J. Goodacre and A.N. Sloss [12] developed address these challenges, they proposed several
"Parallelism and the ARM Instruction Set solutions. Firstly, they suggested implementing

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dynamic voltage and frequency scaling techniques implementations of a family of broadband

to optimize power consumption while maintaining mediaprocessors and provides an example to
performance levels. Secondly, they advocated for demonstrate the software development process
the integration of hardware-based security features within its development environment.
to enhance the robustness of RISC-V
microprocessors against potential threats. Lastly, GAP ANALYSIS
Liang and Wu recommended the incorporation of
The literature presented spans several
specialized accelerators tailored for handling
decades and covers diverse aspects of computer
artificial intelligence and machine learning
architecture, from foundational principles and design
workloads efficiently. Overall, their proposals aim
goals to specific implementations and extensions.
to overcome existing obstacles and pave the way
However, there exists a noticeable gap in the
for the development of more efficient, secure, and
temporal continuity and the focus on specific
versatile RISC-V microprocessors capable of
architectures. While the RISC-V Instruction Set
meeting the demands of evolving computing
Manual outlines the principles of an open and
environments.
efficient ISA, and the IBM System / 360 paper
MMX technology [6] was developed to enhance the
delves into the innovative features of a historical
performance of multimedia and communications
mainframe architecture, there is a temporal and
software by adding new data types and instructions
contextual divide between these two. The AltiVec
to the Intel architecture (IA) that take advantage of
extension introduces a SIMD approach for
parallel processing capabilities. By incorporating a
multimedia processing, offering a more
SIMD (single-instruction, multiple-data) approach,
contemporary perspective, but the transition from
MMX technology improves the efficiency of
historical mainframe architectures to modern SIMD
applications that involve multimedia,
extensions remains somewhat unexplored.
communication, and other numerically intensive
Furthermore, the literature on the Lincoln TX-2
tasks by leveraging inherent parallelism in these
computer introduces an experimental large-scale
applications.
digital system, but its connection to subsequent
Speculative Lock Elision (SLE), an innovative
developments in computer architecture, especially in
micro-architectural method [3] aimed at eliminating
terms of mainstream adoption or influence on future
unnecessary lock-induced serialization during
designs, is not explicitly addressed. Finally, the
runtime, thereby supporting more concurrent
paper on the ARM Instruction Set Architecture
multithreaded execution. The fundamental idea is
highlights the evolution of ARM processors and
that acquiring locks is not always required for
their adaptation for embedded applications,
correct program execution. By predicting which
presenting a more recent perspective. However, the
synchronization instructions are redundant and
gap lies in the absence of a clear bridge connecting
omitting them, SLE allows multiple threads to
the historical mainframes, experimental designs, and
execute critical sections concurrently, even when
the contemporary emphasis on parallelism in ARM
these sections are governed by the same lock.
processors. A comprehensive analysis that
To achieve programmability while maintaining
seamlessly traces the evolution of computer
high performance, the Imagine stream processor
architecture from historical foundations to current
was developed at Stanford University[4][5].
trends and innovations is needed to provide a
Imagine integrates a programming model, software
holistic understanding of this dynamic field.
tools, and a specialized architecture, all tailored to
efficiently handle streams. The stream
III. METHODOLOGY
programming model reveals the inherent locality
and concurrency in media applications, enabling The RISC-V highlights the importance of the
the stream architecture to fully utilize these RISC-V ISA Manual Version 2.2 as a crucial
properties. The architecture features a unique reference for understanding the details of the RISC-
register file design that supports 48 floating-point V 32I ISA. This manual serves as the guiding
arithmetic units. framework for the design and implementation of the
A broadband mediaprocessor introduced to project's 32-bit processor core, providing detailed
efficiently handle digital video, audio, data, and RF specifications of instruction sets, opcode encodings,
signals at broadband speeds, relying on compiled, and architectural conventions. The figure 3.1
downloadable software instead of specialized represents the block diagram of RISC-V
hardware[8][9]. This approach introduces the architecture.
instruction set, system capabilities, and initial

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Fig 3.1: Block Diagram of Configurable PUF

In the realm of RISC-V processor design, the
Five notable existing designs are scrutinized to choice of Electronic Design Automation (EDA)
provide a nuanced understanding of the diverse tools plays a crucial role in facilitating the
landscape of RISC-V processors. Each design, development, simulation, and verification
ranging from Rocket Chip's configurability to processes. EDA Playground, an online platform for
PicoRV32's lightweight FPGA focus, presents EDA tool access, proves to be a valuable resource
unique strengths and challenges. BOOM's out-of- for the project's 32-bit processor core
order execution and Sodor's educational emphasis implementation. This cloud-based platform offers
further contribute to the rich ecosystem. VexRiscv's a convenient and collaborative environment,
FPGA-centric design underscores the adaptability of enabling users to design and simulate circuits
RISC-V architectures for different use cases. These using various tools without the need for local
existing designs collectively showcase the installations.
versatility, scalability, and educational potential of IV.RESULT
RISC-V.
The RISC-V presents a comprehensive
RISC-V is a family of open and extensible
analysis of the performance and functionality of
instruction set architectures (ISA) that are based on
the designed processor core. This section outlines
the reduced instruction set computer (RISC) design
the outcomes of executing various instructions,
principles. RISC-V has a base integer ISA, which
assesses the effectiveness of the implemented
can be extended with optional standard extensions
design choices, and discusses potential areas for
for different purposes. The base integer ISA has four
improvement. Through rigorous evaluation and
variants: RV32I, RV64I, RV128I, and RV32E,
comparison with design objectives, this section
which differ in the size of the registers and the
provides insights into the overall performance,
address space. RV32I is the most common variant,
efficiency, and feasibility of the processor core
which has 32-bit registers and a 32-bit address
within its intended applications.
space. RV32E is a reduced variant, which has only
16 registers for embedded applications. The base
integer ISA defines six types of instructions: R, I, S,
B, U, and J, which have different formats and
operands.
In the landscape of RISC-V processor
design, the tooling chosen for simulation and testing
is paramount. Digital, a versatile open-source logic
designer and simulator developed by Heneman,
emerges as a powerful asset in the implementation of
the project's 32-bit processor core. The tool boasts
an array of features tailored for effective circuit
Fig 4.1: Output of Fetch Unit
analysis, synthesis, and visualization. Its
adaptability, performance, and debugging
The fetch unit of the RISC-V processor core serves
capabilities make it a valuable addition to the
as a fundamental component responsible for
project's toolchain.
retrieving instructions from memory for execution.
Through rigorous testing and analysis, the

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performance and functionality of the fetch unit ensuring reliable computation across a wide range
have been thoroughly evaluated. of applications. The inclusion of operations such as
The waveform analysis of the fetch unit "set less than" and "set less than unsigned" enables
indicates its ability to effectively increment the efficient comparison of input data, facilitating
program counter (PC) with each clock cycle when conditional branching and decision-making
enabled. This functionality aligns with the basic processes within program execution. The figure
requirement of fetching sequential instructions for 4.3 represents the output of ALU unit.
execution. Additionally, the fetch unit
demonstrates robust behaviour in response to reset
signals, promptly resetting the program counter to
its initial state. The figure 4.1 represents the output
of fetch unit.
The decoder unit of the designed RISC-V
processor core plays a pivotal role in interpreting
the incoming instruction stream and preparing the
necessary control signals for subsequent stages of
execution. Through rigorous analysis and Fig 4.3: Output of ALU Unit
evaluation, the effectiveness and efficiency of the
decoder unit can be assessed. The Register File unit, a critical component of
The decoder unit successfully identifies the the RISC-V processor core, serves as a storage
type of instruction being processed, categorizing mechanism for the 32 general-purpose registers,
them into distinct categories such as register-type, facilitating efficient data access and manipulation
immediate-type, load-type, store-type, branch- during program execution. Through rigorous testing
type, call-type, load-immediate-type, and jump- and analysis, the Register File unit demonstrated
type. This categorization ensures proper handling robust functionality and performance in meeting the
of diverse instruction formats, facilitating seamless core's design objectives.
execution within the processor core. The figure 4.2
represents the output of decoder unit. Upon examination of the waveform generated
during simulation, it is evident that the Register File
unit effectively handles simultaneous read and write
operations, ensuring seamless data flow within the
processor core. The waveform illustrates the timely
propagation of data from the designated source
registers to the destination registers, validating the
correctness of the read and write logic implemented
within the unit. The figure 4.4 represents the output
of register file unit.

Fig 4.2: Output of Decoder Unit

The ALU unit serves as a fundamental

component within the designed RISC-V processor
core, responsible for executing arithmetic and
logical operations on input data. Through rigorous
testing and analysis, the ALU unit demonstrates
robust functionality and performance, effectively
fulfilling its designated tasks.

Upon examination of the ALU unit's Fig 4.4: Output of Register File Unit
waveform, it is evident that the implemented
operations, including addition, subtraction, logical The instruction memory unit serves as a
left shift, logical right shift, arithmetic right shift, fundamental component of the RISC-V processor
bitwise XOR, bitwise OR, and bitwise AND, are core, facilitating the retrieval of instructions stored
executed seamlessly within the desired clock in memory for execution. Upon evaluating the
cycle. The waveform illustrates the timely functionality of the instruction memory unit, it was
generation of output data based on the specified observed that the implemented design successfully
ALU operation and input operands. fetched instructions based on the provided address
inputs.
Furthermore, the ALU unit exhibits accurate
handling of both signed and unsigned data,

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The waveform analysis revealed a consistent brings about refinements and enhancements aimed at
and accurate retrieval of instructions from the achieving greater performance, efficiency, and
memory array during each clock cycle. This versatility. As computing demands continue to
indicates the proper functioning of the instruction evolve, the RISC-V processor core stands poised to
memory unit in accessing the designated memory adapt to the RISC-V architecture.
locations and delivering the corresponding
instructions to downstream processing units. The
figure 4.5 represents the output of instruction FUTURE SCOPE
memory unit.
While the current iteration of the processor
core has demonstrated functionality within its design
constraints, there exists a promising avenue for
future enhancements and refinements to bolster its
performance and capabilities.One significant aspect
of future development involves transitioning the
processor core from a single-stage architecture to a
five-stage pipeline architecture. This transition will
Fig 4.5: Output of Instruction Memory Unit
involve the introduction of distinct pipeline stages
for fetch, decode, execute, memory operation, and
write back to register. By breaking down the
V. CONCLUSION
instruction execution process into discrete stages, the
In culmination, the development and evaluation processor can exploit parallelism and achieve higher
of the RISC-V processor core represent a significant throughput, thereby enhancing overall performance.
endeavour in the realm of computer architecture
design. Through meticulous design choices and In addition to pipeline implementation,
implementation efforts, a functional processor core incorporating a branch prediction module represents
has been realized, capable of executing a subset of a critical advancement. Branch prediction techniques
RISC-V instructions with single-clock-cycle can mitigate the performance penalties associated
efficiency.The project's success hinges on the with conditional branches by speculatively executing
effective integration and coordination of various instructions based on predicted branch outcomes.
processing units, including the fetch unit, decode This optimization can significantly enhance the
unit, ALU unit, register file, memory control unit, efficiency of the processor core, especially in
and instruction memory unit. Together, these scenarios with frequent branch
components form a cohesive architecture that instructions.Furthermore, to address potential
enables the execution of instructions within the hazards arising from instruction dependencies within
specified operational parameters.Development of a the pipeline, the inclusion of instruction stalls can
functional RISC-V processor core that efficiently ensure proper data dependencies and maintain
executes a subset of the RISC-V instructions in a program correctness. By intelligently managing
single clock cycle. instruction flow and resource utilization, instruction
stalls can mitigate hazards such as data hazards and
Throughout the project, a thorough control hazards, thus optimizing pipeline efficiency.
understanding of RISC-V architecture principles
guided the design decisions, ensuring compliance Another area of focus for future enhancements
with the base 32I instruction set while also involves increasing the operating frequency of the
incorporating pseudo-instructions to enhance processor core. By leveraging advancements in
programmability and readability. The inclusion of semiconductor technology and optimizing the design
simultaneous read and write capabilities for registers for higher clock speeds, the processor can achieve
and data memory further enriches the processor greater computational throughput and
core's functionality and versatility.The evaluation of responsiveness, making it better suited for
the processor core's performance, as evidenced by demanding computing tasks.
waveform analysis and functional testing,
demonstrates its reliability and efficiency in REFERENCES
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