27-10-2024

ANALOG ELECTRONIC
CIRCUITS
ICE 2121 [3 1 0 4] [4-Credit]

MUKUND KUMAR MENON

Assistant Professor (Sr. Scale),
Dept. of I&CE,
MIT-MAHE, Manipal

COURSE LEARNING OUTCOMES:

At the end of the course, the students will be able to

CO1 Understand the operation of field effect transistors (FET)

CO2 Analyze various biasing and amplifier topologies of FET

CO3 Realize differential amplifiers using FET

CO4 Analyze frequency response of FET amplifiers

CO5 Design of various feedback amplifiers and power amplifiers

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Chapter 2 MOS Amplifiers [ 14 Lecture Hours]

• Biasing
• Amplifier topologies
• Analysis and Design of Common-Source Amplifier
• Common-Gate Amplifier
• Source Follower
• Cascode stage- current mirror, amplifier
• MOS current mirror, Two stage CS Amplifiers
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MOSFET based amplification: Intro

• The basis for using MOSFET as an
amplifier is that when operated in
saturation, the MOSFET functions
as voltage-controlled current
source: VGS controlling ID.
• A simple way to use MOSFET as
voltage amplifier is to pass the
output current through a resistor
and take the voltage across the
resistor as the output.
• RD acts as load resistance, converts
ID into a voltage IDRD with supply
voltage as VDD
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MOSFET amplifier: Voltage transfer characteristics (VTC)

• In saturation region, we see the maximum slope (A-B) where

• Thus, MOSFET is made to operate as an amplifier in saturation

region.
• This equation  obviously a nonlinear relationship.
• We use Biasing to achieve linear amplification.

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MOSFET Biasing for linear amplification

• A dc voltage VGS is selected to obtain operation at a point Q on the

segment AB of the VTC.
• Point Q is known as the bias point or the dc operating point. Also,
since at Q no signal component is present, it is also known as the
quiescent point.
• Next, the signal to be amplified, vgs, a function of time , is superimposed
on the bias voltage. Thus, the total instantaneous value of vGS becomes

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MOSFET Biasing for

linear amplification

I/P

O/P

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MOSFET Biasing for linear amplification

• Consider case of vgs being a triangular wave of “small” amplitude.

Specifically, the amplitude of vgs is small enough to restrict the
excursion of the instantaneous operating point to a short, almost-
linear segment of the VTC around the bias point Q.
• The shorter the segment, the greater the linearity achieved, and
the closer to an ideal triangular wave the signal component at
the output, vds, will be.
• This is the essence of obtaining linear amplification from the
nonlinear MOSFET.
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Different strategies of MOSFET Biasing

An appropriate dc operating point or bias point is characterized by a stable and

predictable dc drain current ID and by a dc drain-to-source voltage VDS that
ensures operation in the saturation region for all expected input-signal levels.

Technique 1: Biasing by Fixing VGS.

Technique 2: Biasing by Fixing VG and Connecting a Resistance in the Source

Technique 3: Biasing Using a Drain-to-Gate Feedback Resistor

Technique 4: Biasing Using a Constant-Current Source

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Different strategies of MOSFET Biasing

• Technique 1: Biasing by Fixing VGS.

The most straightforward approach to
biasing a MOSFET is to fix its gate-
to-source voltage VGS to the value
required to provide the desired ID.
Not a good approach as we observe
that for the fixed value of VGS, the
resultant spread in the values of the
drain current can be substantial.

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Different strategies of MOSFET Biasing

𝑽𝑮 𝑽𝑮𝑺
• Technique 2: Biasing by Fixing 𝑰𝑫 =
𝑹𝑺
VG and Connecting a Resistance 𝑰𝑫 ∝ 𝑽𝑮 − 𝑽𝑮𝑺
in the Source, Rs
 For this circuit we can write:
= VS

 RS provides negative feedback,

which acts to stabilize the value of
the bias current ID.

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Different strategies of MOSFET Biasing

Practical implementations

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Different strategies of MOSFET Biasing

• Technique 3: Biasing Using a Drain-to-Gate
Feedback Resistor

Here the large feedback resistance RG (usually in

the Megohm range) forces the dc voltage at the gate
(VGS) to be equal to that at the drain, VDS (because
IG = 0). For this circuit it can be written as:

 The negative feedback provided by RG works to

keep the value of ID as constant as possible.
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Different strategies of MOSFET Biasing

• Technique 4: Biasing Using a Constant-
Current Source
 Most effective scheme for biasing a MOSFET amplifier.
Here RG (usually in the megohm range) establishes a dc
ground at the gate and presents a large resistance to an input
signal source that can be capacitively coupled to the gate.
Resistor RD establishes an appropriate dc voltage at the drain
to allow for the required output signal swing while ensuring
that the transistor always remains in the saturation region.
This circuit for implementing the constant-current source ‘I’
is called the current mirror circuit.

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MOSFET as Small Signal amplifier: Analysis

• Step 1: Fixing the DC bias point: (putting vgs =0)

• To ensure saturation-region operation, we must have

• Since the total voltage at the drain (vDS) will have a

signal component vDS superimposed on VDS, VDS has
to be sufficiently greater than VOV to allow for the
required signal swing.

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Since the total voltage at the drain

will have a signal component vDS
superimposed on VDS,

VDS has to be sufficiently greater

than VOV to allow for the required
signal swing.

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MOSFET as Small Signal amplifier: Analysis

• Next, we consider the situation with the input signal vgs applied. The total instantaneous gate-to source
voltage will be

The drain current iD can be written as:

Can be neglected
Drain Current IDC Bias Small signal Drain Current id

If vgs is small,

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MOSFET as Small Signal amplifier: Analysis

• If this small-signal condition is satisfied, we may neglect the last term in prev. eqn. and express
iD as:

where

Transconductance, gm , can be introduced here as:

Or,
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O/P Voltage

Graphical interpretation of small signal amplification

O/P Current

I/P Voltage I/P Voltage

Note that gm is equal to the slope of the iD vs. vGS

characteristic at the bias point (Q), i.e.

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Voltage Gain
• From the circuit, vDS = VDD – RDiD
• Under the small-signal condition, we have
vDS = VDD – RD(ID + id)
or, vDS = VDS – idRD
Thus the signal component of the drain voltage is,
vds = – idRD = – gmvgsRD

which indicates that the voltage gain is given by

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Realization of Voltage Dependent Current Sources

• MOS transistors operating in saturation can act as
current sources.
• As illustrated in Fig. (a), an NMOS device serves as a
current source with one terminal tied to ground, i.e.,
it draws current from node X to ground.
• On the other hand, a PMOS transistor [Fig. (b)]
draws current from VDD to node Y. If λ = 0, these
currents remain independent of VX or VY (so long as
the transistors are in saturation).

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Realization of Current Sources: Review Question

• Consider the circuits shown in Fig. (c) and Fig. (d) (.. w/o external resistances!!).
Do they qualify for being called current sources?
Solution:
 NMOS or PMOS devices configured as
shown in Figs. (c) and (d) do not operate as
current sources because variations of VX or
VY directly change the gate-source voltage of
each transistor, thus changing the drain
current considerably.
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MOS Amplifier topologies

MOS Amplifiers

Common Drain
Common Source Common Gate (CD) OR
(CS) (CG)
Source Follower

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Recall: MOS Transconductance (gm)

• As a voltage-controlled current source, a MOS transistor can be characterized by
its transconductance,

• This quantity serves as a measure of the “strength” of the device: a higher value
corresponds to a greater change in the drain current for a given change in VGS.

• For saturation region,

(1)

• Replacing (VGS - VTH) in terms of ID we get: [Using ID eq. for saturation]

(2)
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Recall: MOS Transconductance (gm)

Another equation holds true if we divide eq. (1) by ID equation in saturation

(3)

Various dependencies of gm : Summary Table

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1. Common Source
Stage (CS)

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Common Source Stage (CS)

• As shown in Fig. (a) the basic CS stage is

similar to the common-emitter topology, with

the input applied to the gate and the output

sensed at the drain.

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Common Source Stage (CS)

• Fig. (b) yields vin = v1 and

vout = − gmv1RD. That is,

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Common Source Stage (CS)

• Using we can write:

• It might appear gain can be increased by increasing IDRD , but for the MOS to
be in saturation,

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Common Source Stage (CS): Example Problem

Fig. below assumes that ID = 1 mA, μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0.
a) Calculate the small-signal voltage gain of the given CS stage.
b) Verify that M1 operates in saturation.

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Solution:
(a)
Find gm :

Find gain:
(b)

The drain voltage, VD = VDD − RDID = 0.8 V.

Since VOV = VGS − VTH

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= 0.6 V, the device  in saturation (i.e. w/ a margin of 0.2 V w.r.t. the triode region.) 33

Common Source Stage (CS): Input and Output Impedance

• Since the gate current is zero (at low • Similarly, the output impedance Rout
frequencies), input impedance Rin = ∞ = Vx/Ix = RD (going around the outer
• The high input impedance of the CS loop)
topology plays a critical role in many
analog circuits.

Small signal Model for Rout

Small signal Model for Rin

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Common Source Stage (CS): Input and Output Impedance

• If channel length modulation is included, especially if RD is large, the small signal model
gets modified as shown in Fig below.

• Thus,

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1A. CS Stage With Current-Source Load

• Recall that the PMOS also can act as a

current source and hence can be put as a
load on the NMOS CS amplifier.

• So, CS stage NMOS amplifier with Current

source load (PMOS) looks like the circuit
shown 

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1A. CS Stage With Current-Source Load

• Consider the small signal model of the circuit
• M2 (PMOS) acts as a resistor (..why??) with both Vb and
VDD grounded for ac analysis.
• Here, v1 = 0 and hence gm2v1 = 0, so M2 only represents
ro2
• Thus, the drain node of M1 i.e. Vout sees both ro1 and ro2
to ac ground.
• It follows that:

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CS Stage With Current-Source Load: Review Problem

Figure below shows a PMOS CS stage using an NMOS current source

load. Compute the voltage gain of the circuit.

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CS Stage With Current-Source Load: Review Problem

Figure below shows a PMOS CS stage using an NMOS current source load. Compute the voltage gain of the circuit.

Solution:

Transistor M2 generates a small-signal current equal to

gm2vin, which then flows through
rO1||rO2, producing vout = −gm2vin(rO1||rO2).

Thus,
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1B. CS Stage With Diode connected load

• In some applications, we may use a diode-connected
MOSFET as the drain load.
• Illustrated in Fig. (a), such a topology exhibits only a
moderate gain due to the relatively low impedance of
the diode-connected device.
• M2 acts as a small signal resistance equal to 1/gm2, thus
neglecting channel length modulation using basic CS
gain eqn., i.e. Av = -gmRD we have

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1B. CS Stage With Diode connected load

Fig. (b): Simplified circuit of (a)

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1B. CS Stage With Diode connected load

Fig. (b): Simplified circuit of (a)

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1B. CS Stage With Diode connected load

• A more accurate expression for the gain of the stage in Fig.(a) must take
channel length modulation into account.
• As depicted in Fig.(b), the resistance seen at the drain is now equal to
(1/gm2)||rO2||rO1, and hence

• Similarly, the output resistance of the stage is given by

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Fig. (b): Simplified circuit of (a) 43

1C. CS Stage With Degeneration

• Let us attach a Source resistance Rs to the source

terminal of the MOSFET as shown.

• Corresponding small signal equivalent model can be

drawn as:

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1C. CS Stage With Degeneration

• From small signal model,

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1C. CS Stage With Degeneration

• Since gmv1 flows through RD, vout = − gmv1RD , putting expression of v1,
we get,

• The gain decreases by a

factor 1 + gmRs due to the
source resistance Rs.
• Because of the negative-
feedback action of Rs , it
is known as a source-
degeneration resistance.
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1C. CS Stage With Degeneration: Output Impedance calculation

• For output impedance, the small

signal model appears as shown
27-10-2024 here. 47

1C. CS Stage With Degeneration: Output Impedance calculation

• Since RS carries a current equal to iX,

we have v1 = −iXRS. Also, the current
through rO is equal to:

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1C. CS Stage With Degeneration: Output Impedance calculation

• [Voltage drop across r0 ] + [Voltage drop across Rs ] = vx

Hence,

So,
• For CS stage with degeneration (with Rs), MOS exhibits a
“boosted” output impedance.
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1D. CS core with Biasing

• Let’s consider voltage divider biasing scheme with Gate Resistance RG and bypass
capacitor

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1D. CS core with Biasing

• We can visualize for case (a):

(a)

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1D. CS core with Biasing

• For case (b), assuming λ=0,

voltage gain falls to:

(b)

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CS core with Biasing

• For case (c) with bypass capacitor C2 ,

and voltage gain rises as:

(c)

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2. Common Gate (CG) stage

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2. Common Gate (CG) stage

VGS
Input rises ID reduces Vout rises by
decreases by
by ∆𝒗 by gm ∆𝒗 gm ∆𝒗 RD
∆𝒗

So, the voltage gain is positive and is equal to:

• To achieve a high gain, a high ID or RD is necessary,

but the drain voltage, VDD − IDRD , must remain
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2A. CG stage: Impedance calculation without RS

SSA
v 1 = − vX

𝒗𝒙 𝟏
𝑹𝒊𝒏 = =
27-10-2024 Relatively low value
𝒊𝒙 𝒈𝒎 56

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2A. CG stage: Impedance calculation without RS

SSA

v1 = 0
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2B. CG stage: Gain and impedance calculation with RS

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2B. CG stage: Gain and impedance calculation with RS

Thus, • The gain is therefore
equal to that of the
degenerated CS stage
except for a negative
sign.
• Following the same
pattern as in
degenerated CS
topology, output
impedance can be
found as:

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2C. CG stage: Input impedance calculation with RG

• A resistance appearing in series

with the gate terminal as shown in
Fig. does not alter the gain or I/O
impedances (at low frequencies)
because it sustains a zero potential
drop—as if its value were zero.

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2C. CG stage with voltage divider biasing

• Providing a path for the bias

current to ground, resistor R3
lowers the input impedance—
and hence the voltage gain—
if the signal source exhibits a
finite output impedance, RS.

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2C. CG stage with voltage divider biasing

• Since the impedance seen to the right of
node X is equal to R3||(1/gm), we have

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3. Common Drain (CD) or Source Follower configuration

• The amplifier senses the input at the gate and

produces the output at the source, with the drain
tied to VDD / GND. (practical / small-signal resp.)

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Common Drain (CD) or Source Follower configuration

vG = vin = vGS + vout
vS = vout
VDD = vDS + vin - vGS

Input at
VGS
Gate rises Is increases Vout rises
increases
by ∆𝒗
• Thus, Vout “follows” Vin.
• Since the dc level of Vout is lower than that of Vin by VGS, we say the follower can serve
as a “level shift” circuit.
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3A. Source Follower configuration: Voltage gain calculation

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3A. Source Follower configuration: Voltage gain calculation

• Recognizing that rO appears in

parallel with RL, we have

• Also, we can write,

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3A. Source Follower configuration: Voltage gain calculation

• Similarly, Voltage gain (AV) is

found as,

• The voltage gain is therefore

positive and less than unity. It is
desirable to maximize RL (and rO).

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3A. Source Follower configuration: Impedance calculation

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3A. Source Follower configuration: Impedance calculation

• The input impedance is infinite at low
frequencies. (Why ??)
• As illustrated in figure here, Rout consists of the
resistance seen looking up into the source in
parallel with that seen looking down into RL.
• Thus, we can write
• In summary, the source follower exhibits a very
high input impedance and a relatively low
output impedance, thereby providing buffering
capability. It can act as a buffer.
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3B. Need for a voltage buffer

• Consider the situation depicted in
Fig. here
• A signal source delivering a signal
of reasonable strength (1 V) with an
internal resistance of 1 MΩ is to be
connected to a 1-k Ω load
resistance.

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• Connecting the source to the load

directly (as in the figure) would result
in severe attenuation of the signal.
• The signal appearing across the load
𝟏
will be only of the input i ≈ 999nA
𝟏𝟎𝟎𝟎 𝟏

signal or about 1 mV.

• This doesn’t appear as a good
technique at all !!!!

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• An alternative course of action is

suggested here.
• Here an amplifier  interposed
between the source and the load. This
amplifier, however, has/should have a
voltage gain of only unity.
• This is because the input signal is
already of sufficient strength and we
do not need to increase its amplitude.
• Note, however, that this amplifier has
a very large input resistance, thus
almost all of (i.e., 1 V) will appear at
the input of the amplifier proper. 27-10-2024 72

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• Since the amplifier has a low

output resistance (100 Ω), 90%
(say) of this signal (i.e. 0.9 V)
will appear at the output,
obviously a very significant
improvement over the situation
without the amplifier.
• In such situations, Source
follower configuration is the
only option for signal transfer.
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3C. Source Follower with Biasing

• Figure (here) depicts an example where RG
establishes a dc voltage equal to VDD (how??)
at the gate of M1 and RS sets the drain bias
current.
• With a zero voltage drop across RG, we have

• Note that M1 operates in saturation because

the gate and drain voltages are equal. Also,
the input impedance of the circuit has
dropped from infinity to RG.
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3C. Source Follower with Biasing

• Neglecting channel-length modulation,

• This resulting quadratic equation can be

solved to obtain ID.

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Practice Problem 1

• Derive the expressions for voltage gain and output impedance of the circuit
shown here

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Practice Problem 1
Solution:
Analysis from observation:

• M1  in common-source device (WHY ??) .

• Transistors M2 and M3  as the load
• M2  as a current source
• M3  as a diode-connected device.

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Practice Problem 1
Solution:
• Thus, M2  replaced with a small-signal resistance
equal to rO2 , and M3 with another equal to (1/gm3)||rO3.
• The circuit now reduces to that depicted here, based
on which :

• Also,

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Practice Problem 2

• Compute the voltage gain of the

circuit shown here.

• Neglect channel-length modulation

in M1.

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Practice Problem 2
Solution:
Analysis from observation:
• M1  as a CS stage and degenerated
• M3  diode-connected device degenerates M1,
• M2  the current-source load,
• Simplifying the amplifier to that in figure (here):

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Problem 1: Determine the bias

current of M1 in Fig. assuming VTH
= 0.5V, μnCox = 100 μA/V2, W/L =
5/0.18, and λ = 0. What is the
maximum allowable value of RD for
M1 to remain in saturation?

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Solution:

Let’s find the Gate terminal voltage VX

Applying KVL from VX to ground through RS, we

get

which means, 1.286 = VGS + ID (1 KΩ)

………….. (1)

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Solution:

Using ID equation for saturation, we have:

Putting values we get, ID = (½) (100x10-6)(5/0.18)(VGS – 0.5)2 …………… (2)

Substituting the value of VGS from eq. (1), we can find ID

Check : ID = 312 μA
Maintaining this ID and saturation condition we must have:
Drain voltage, VY = VDD – ID RD = VX – VTH = 1.286 – 0.5 = 0.786 V

Maximum allowable RD therefore is,

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RECALL: CS Stage With PMOS Current-Source Load

• Practically, due to channel length
modulation, current source load has a
finite resistance ro2. (assuming λ = 0,
then output resistance  ∞)
• Output resistance, Rout will become

∞ • The finite resistance ro2 causes a

reduction in voltage gain from - gm1 ro1
to the following gain (AV)
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• How can one improve/increase the voltage gain obtained from the
CS MOS Amplifiers with Current-Source** Load(s)
(**i.e. the basic gain cell in an IC amplifier)?
•  Find a way to raise the level of the output resistance of both the LOAD
amplifying transistor and the load transistor.
•  i.e. Seek for a circuit that :
 Passes a current gmvi (provided by the amplifying transistor) right
through, and,
 Meanwhile, it increases the resistance from ro to a much larger
value.
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For the purpose of small-signal calculations only

• Figure (a) shows the CS

amplifying transistor Q1 together
with its output equivalent circuit.
>> Passes a current gmvi (provided
by the amplifying transistor) right
through

• In Fig. (b), a shaded/ ‘black’ box

Black Box is inserted between the drain of
Q1 and a new output terminal
labelled as d2.
>> Increases the resistance from
ro to a much larger value
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• This “black box” should take in the output current

of Q1 and pass it to the output.
• Thus, at its output the equivalent circuit shown,
 will consist of the same controlled source gm1 vi ,
but, with the output resistance increased by a factor
of K.
• The black box passes the current but raises the
resistance level, making it a current buffer.
• The only candidate for implementing this current-
buffering action is the common-gate amplifier.

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The Cascode Amplifier : Idea and Implementation in MOS

Cascoding:
• Cascoding, in MOSFET  the use of a transistor
connected in CG configuration to provide as a
current buffer for the output of a CS amplifying
transistor.
• In the figure (here), the CS transistor Q1 is the
amplifying transistor and Q2 connected in the CG
configuration with a dc bias voltage VG2 (signal signal ground
signal ground
ground) at its gate, is the cascode transistor.
• The cascode transistor passes the current (gm1 vi) to the output node,
27-10-2024 while raising the resistance level by a factor K. 88

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Computation of Transconductance of Circuit

An alternative approach without using the Small Signal Model
• Here, we defined the transconductance of a MOS transistor as
the ratio of the change in the drain current to the change in
the gate-source voltage. This concept can be generalized to
circuits as well.
• As illustrated here, the output voltage is set to zero by shorting
the output node to ground, and the “short-circuit
transconductance” of the circuit is defined as

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Analysis of MOS Cascode Amplifier

Part A: Determination of Gm
For the purpose of small-signal calculations only
• Observe that if node d2 (i.e. the load terminal) of the
equivalent circuit is short-circuited to (signal) ground, the
instantaneous current io flowing through the short circuit
will be equal to Gmvi

• It follows (from a signal point of view) that one can

determine the transconductance Gm by short-circuiting the
output of the cascode amplifier to ground, as shown here,
therefore,

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Q2

• Now, replace both transistors Q1 and Q2 in

the circuit with their respective small-signal
Q1
models results in the circuit shown here,
• We shall analyze this model to determine i0
in terms of vi

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At the node d2 ,

Since,

Thus,

>> Passes a current gmvi (provided by the amplifying transistor) right through
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Analysis of MOS Cascode Amplifier

Part B: Determination of R0

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• To determine R0, we set vi to

zero  Q1  reduced to its
output resistance r01 
appears in the source circuit
of Q2.

• Now, by replacing with its

small signal model and
applying a test voltage vx to
the output node, it results in
the equivalent circuit shown
in Fig. (b). The output
resistance R0 can be
obtained as

(VA = Early Voltage)

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• Applying KVL in input loop from g1 to ground through ro1 we get:

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• Since, we can write:

= Ao2 ro1

Interpretation & Conclusion

• The CG transistor Q2 raises the output resistance of the amplifier by the factor (gm2ro2), which is its intrinsic gain.
• At the same time, the CG transistor simply passes the current (gm1 vi) to the output node.
• Thus the CG or cascode transistor very effectively realizes the objectives we set for the current buffer with:
K = Ao2 = gm2 ro2
27-10-2024 >> Increases the resistance from ro to a much larger value 97

Review Problem on MOS Cascode Amplifier

• Calculate the transconductance of the CS stage shown in Fig.

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Review Problem on MOS Cascode Amplifier

Calculate the transconductance of the CS stage shown in the figure.

Solution: An alternative approach without using the Small Signal Model

The output node is shorted to ac ground, and noting that RD carries no current, we write:

Thus, for this (given) circuit,

>> The transconductance of the circuit is equal to that of the transistor.

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VOLTAGE GAIN OF MOS CASCODE AMPLIFIER

• If the cascode amplifier is loaded with an ideal constant-current source as shown in Fig.
(a), the voltage gain realized can be found from the equivalent circuit in Fig. (b) as

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Thus, putting R0 value,

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Replacing current source load with PMOS transistor in

Cascode network

• Cascoding can also be

employed to raise the output
resistance of the current-
source load as shown here.
• Here Q4 is the current-
source transistor, and Q3 is
the CG cascode transistor.
• Voltages VG3 and VG4 are
dc bias voltages.

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• The cascode transistor Q3 ‘multiplies’

the output resistance of Q4
• That is, ro4 × (gm3 ro3)
• This provides an equivalent output
resistance Ro for the cascode current
source i.e. :

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• The complete circuit, therefore, appears as

shown here:

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Current • The complete circuit is shown in Fig. (a) and

Source
Load • The equivalent circuit at the output side is shown in Fig. (b).

Current Buffer

Using the small signal

CS Amp equivalent circuit in
Fig. (b),

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Cascode amplifier with cascode current source: Voltage gain calculation

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Cascode amplifier with cascode current source: Review Problem

Determine the overall voltage gain of the Cascode amplifier. Given that:

• (W/L)1,2 = 30
• (W/L)3,4 = 40
• ID,i = 0.5mA (i = 1,..,4)
• μnCOX = 100 μA/V2
• μpCOX = 50 μA/V2
• λn = 0.1 V-1
• λp = 0.15 V-1
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Problem 1:

Assuming M1 operates in
saturation,

• Determine the voltage gain of

the circuit (depicted here) and
• Plot the result as a function of
the transistor channel length
while other parameters remain
constant.
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Solution:
This is a case of CS stage with ideal current source as a load.

Ideal current source presents infinite output impedance.

If r0 is the output impedance for M1 then voltage gain

Putting gm expression as :

we get,

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Solution:

we get,

• Now, how is λ related to channel

length L ? Is it independent,
directly proportional or
inversely proportional?

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Problem 2: Here, assume M1 is in

saturation and RD = 2.5 KΩ and compute
(a) The maximum allowable value of
W/L and
(b) The minimum allowable value of RS
(with W/L = 5/0.18).

Assume λ = 0, VTH = 0.5V, μnCox =

100 μA/V2

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Solution:

Let’s find the Gate terminal voltage VX

Maximum allowable ID is given by: [Note: Drain voltage VY

remains same as in Prob 1]

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Solution:

(a) Applying KVL from VX to ground through RS, we get

Since, VX, ID and RS are known, VGS can be calculated as:

VGS = 0.88 V

Using saturation equation for ID

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Solution:

(b) With W/L = 5/0.18,

the minimum allowable value of RS gives a drain current of 406
μA.

Using ID equation for saturation, we have:

Now, RS(min) can be calculated as:

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Problem 3: Calculate the drain current

of M1 in Fig. if μnCox = 100 μA/V2,
VTH = 0.5 V, and λ = 0. What value of
RD is necessary to reduce ID by a
factor of two?

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Solution:

Let’s first consider a general self biased MOS amplifier circuit

Considering that M1 is in saturation and the voltage drop across RG is zero.,

Thus, by KVL

From above equation, VGS = VDD – ID (RD + RS)

Using ID equation for saturation and putting above VGS expression we get

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Solution:

Using ID equation for saturation and putting above VGS expression we get

Expanding the above equation, we get a quadratic equation in ID

----- (1)

Using eq. (1) we can find ID

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Solution:

Based on the analysis done, putting appropriate values in eq. (1) we get

In order to reduce ID to half i.e. 278 𝜇𝐴 , solving eq. (1) again by putting ID = 278 𝜇𝐴

we get,

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Practice Problem 4
• Determine the voltage
gain(s) of the amplifiers
illustrated in Figs. (a)
and (b).
• For simplicity, assume
rO1 = ∞ in Fig. (b).

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Solution:
For Fig. (a):
• Transistor M1  in CS config. &
Degenerated by RS  M1 presents an
impedance of (1 + gm1rO1)RS + rO1 to the
drain of M2.
• Thus, the total impedance seen at the drain is
equal to [(1 + gm1rO1)RS + rO1] || rO2, giving a
voltage gain of
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Solution:
For Fig. (b):
• M1  as a CG stage and M2 as the load,
obtaining voltage gain Eq. already derived for
CG stage with signal source resistance:

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Practice Problem 5

Calculate the voltage gain of the

circuit shown in Fig. if channel
length modulation is neglected.

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Solution:

• In this circuit, M1 operates as a source follower

and M2 as a CG stage.
• A simple method of analyzing the circuit is to
replace Vin and M1 with a Thevenin equivalent.
• From the simplified circuit of Small-signal
equivalent of source follower, discussed before,
we derive the model depicted in Fig.(b). Thus,
voltage gain:

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NECESSITY OF CURRENT MIRROR CIRCUIT IN

IC CHIP DESIGN

@ −20 deg.C @ +50 deg.C

Mobile phone mainboard

https://commons.wikimedia.org/wiki/File:IPhone_3G_teardown_-_main_board-3298.jpg

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Necessity of Current Mirror Circuit in IC chip design

• A critical issue in biasing relates to ambient temperature variations
• Consider a scenario with MOS circuit being used as a current source (shown
here), an NMOS current source  biased using a resistive divider
• This circuit  suffers from dependency on VDD and also the ambient
temperature.
• For the circuit shown (at saturation), we can write:

• Since mobility as well as the threshold voltage vary with temperature,

 I1 is not constant, even if VGS is.
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“ A bandgap reference voltage is a voltage source that outputs a voltage

proportional to the bandgap of a semiconductor. SI bandgap voltage (Silicon)
references are most common, which output at ~1.2 V. ”
https://resources.system-analysis.cadence.com/blog/msa2020-bandgap-voltage-reference-
circuit-design-and-usage

 Makes/ensure that the transistor is less sensitive to temperature and supply voltage

https://www.irjet.net/archives/V3/i5/IRJET-V3I5167.pdf
https://mixsignal.wordpress.com/wp-content/uploads/2013/03/l390-bandgaprefs.pdf

27-10-2024 127

A bandgap reference (BGR) circuit using subthreshold MOSFETs can generate a reference voltage for a supply voltage, and is less sensitive to
temperature and supply voltage. BGR circuits are used in many analog and digital circuits, such as: Memory systems, High precise comparators,
Phase-locked loop, Ring oscillator, and Implantable biomedical products.
Here are some examples of BGR circuits that use MOSFETs:
•Low voltage bandgap reference (LVBGR) circuit
 This circuit uses subthreshold MOSFETs to generate an output reference voltage for a supply voltage of 1.2V.
•Subthreshold MOSFET bandgap reference
 This BGR uses subthreshold MOSFETs to provide temperature compensation. It can provide an output voltage of 429 mV with a supply
voltage as low as 0.6 V.
•0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference
 This low-power, low-voltage BGR circuit can operate with a supply voltage as low as 0.9 V. It has several advantages over previous
methods, including lower power consumption, smaller area of silicon, and no BJT circuitry.
•Low power, offset compensated, CMOS only bandgap reference
 This BGR circuit has a temperature coefficient of 35 ppm/°C and operates at a minimum supply voltage of 600 mV. It consumes a total
power of 9.5 μW.

•A low power, offset compensated, CMOS only bandgap reference in ...

•Abstract: In this paper a very low supply voltage Bandgap Voltage Reference Circuit (BGR) has been presented. A temperature
coeffi...
•IEEE Xplore
Generative AI is experimental.

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Necessity of Current Mirror Circuit in IC chip design

• To avoid these dependencies, a bandgap reference can provide a “golden current” while requiring a few
tens of devices. One must therefore seek a method of “copying” the golden current without duplicating
the entire bandgap circuitry.
• Current mirrors serve this purpose.
• Figure (here) conceptually illustrates the goal.

• The golden current generated by a bandgap reference is “read” by the current mirror and a copy
having the same characteristics as those of IREF is produced. For example, Icopy = IREF or κ.IREF

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MOS Current Mirror: Idea and Intro

• Consider the arrangement shown below:

• Now, if channel-length modulation is neglected, the black box must generate VX (here, VX = VGS) such that
Icopy,1 equals:

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MOS Current Mirror: Idea and Intro

• Thus, the black box must satisfy the following input (current)/output (voltage) characteristic:

• That is, it must operate as a “square-root” circuit.

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MOS Current Mirror: Idea and Intro

• Which configuration of MOSFET circuit is capable of providing a square root operation ?

• Recall all the Common Source MOS Amplifier variants.

1. Core CS configuration with RD

2. CS with PMOS current source as the load

3. CS with Diode connected load

4. CS with degeneration resistance (RS)

• Which one would you pick ????

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RECALL: CS Stage With Diode connected load

• In some applications, we may use a diode-connected MOSFET as the drain load.
• Illustrated in Fig. (a), such a topology exhibits only a moderate gain due to the relatively low
impedance of the diode-connected device.
• M2 acts as a small signal resistance (say RD) equal to 1/gm2, thus neglecting channel length modulation
using basic CS gain eqn., i.e. Av = -gm1 RD , we have:

27-10-2024
Fig. (b): Simplified circuit of (a) 133

MOS Current Mirror: Idea and Intro

• Therefore, a diode-connected MOSFET can provide such a “square root” characteristic for current-
mirroring.
• Figure (here) depicts such a scenario.

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MOS Current Mirror: Full circuit implementation

• Thus, we now arrive at an NMOS current mirror depicted in Fig. below.

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MOS Current Mirror: Circuit Analysis

• Consider MREF NMOS transistor,

Gate to source voltage (VGS)REF = Vx
which is the voltage at X node.

• Similarly, for M1 NMOS transistor,

Gate to source voltage (VGS) = Vx
which is voltage at X node.

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MOS Current Mirror: Circuit Analysis

• Thus, drain currents for the two transistors can be expressed as:

where the threshold voltages are assumed equal.

• From the two equations above, it follows that:

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MOS Current Mirror: Circuit Analysis

• If both the transistors are identical i.e. they maintain the same aspect ratio, then:

𝐼 ≅ 𝐼

Thus, Icopy is the mirrored current of IREF

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Review Question
Answer:
• Can the circuit below serve as a
current mirror?
This circuit is not a current mirror because

only a diode-connected device can establish

square root operation based on aspect ratio and
hence a copy current independent of device
parameters and temperature. Since the gates of
MREF and M1 are floating, they can assume any
voltage, e.g., an initial condition created at node X
when the power supply is turned on.
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Design problem using MOS Current mirror

An integrated circuit employs the source follower and the common-source stage shown below.
Design a current mirror that produces I1 and I2 from a 0.3 mA reference.

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Design problem solution

• Carefully choosing the correct aspect ratios, we design the overall circuit shown below

𝑊 𝑊
2 5
𝐼 = 0.2𝑚𝐴 ≅ 𝐿 𝐼 𝐼 = 0.5𝑚𝐴 ≅ 𝐿 𝐼
𝑊 𝑊
3 3
𝐿 .
𝐿 .

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Review problem on MOS Current mirror

Calculate Icopy in each of the circuits

shown here.

Assume all of the transistors operate

in saturation.

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= Bandgap Reference Voltage (BRV)

Solution:

As per the concept of Current mirror(s),

I1 = (2/3) IREF
I1

Then,
Icopy = (3/5) I1
= (3/5) x (2/3) IREF
= 2/5 IREF

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Thank You
End of Unit II

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