Micro Processor Architecture

&
Assembly Language (CS-323)
BS – CS, SE, Telecom, Electronics & CET
(4th semester)

Credit Hours: 3-1

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT
Sarhad University of Science and Information Technology, Peshawar 1
Course Details
Week: 07

Lecture: 13

Topic: Basic Logic Instructions (Chap-05) cont…

Program: BS – CS, SE, Telecom, Electronics & CET

Semester: 4th (Section A, B & C)

Contact: shahid.csit@suit.edu.pk
Department of Computer Science & IT
Sarhad University of Science and Information Technology, Peshawar 2
Previously (Lecture: 1-12)
• Introduction to the Course (MP&AL) (Lect-01)
• Course description, Course outlines, Grading Policy, Recommended
books, Pre-requisite details, Introduction to Microprocessor and
Microcomputer
• Chapter-1: Intro. to Microprocessor & Computer (Lect-02,03 &
04)
• A Historical Background: The Mechanical Age, The Electrical Age,
• First General-Purpose Electronic Computer: ENIAC, Transistor and ICs
• Programming Advancements: Machine/Assembly Language, FORTAN,
ALGOL, COBOL, PASCAL, C, C++, C#, JAVA, ADA etc.
• The Microprocessor Age: 4-bit, 8-bit and 8085 Microprocessor
• The Modern Microprocessors: 16-bit Microprocessors: 8086/8088,
80286, 32-bit Microprocessors: 80386SX/SL/SLC/EX , 80486, Pentium,
Pentium-pro/II/III/4 and core2 etc. 3
Previously (Lecture: 1-12)
• The Microprocessor based PC (Lect-05)
• Memory System: The TPA, The System area, Extended Memory
• I/O System and I/O Space, The Microprocessor, Buses: Address Bus,
Data Bus, Control Bus
• The Number Systems (Lect-06)
• Digits, Positional Notation, Binary, Octal, Decimal, Hexa-decimal
• Conversion from Decimal, Conversion to Decimal
• BCH and Complements, Computer Data Formats: BCD, ASCII, Signed,
Unsigned, Byte-sized Data, Word-sized Data, Real Numbers
• Chapter-2: Microprocessor and its Architecture (Lect-07)
• Internal Microprocessor Architecture, The programming Model,
Multipurpose Registers, Special Purpose Registers, Flag-bit Function,
Segment Register
4
Previously (Lecture: 1-12)
• Real & Protected Mode Memory Addressing (Lect-08)
• Segment and Offset, Default Segment and Offset Registers, TPA,
Segment and Offset Addressing Scheme Allows Relocation
• Protected Mode Memory Addressing: Selector and Descriptor, Program
Invisible Registers
• Data Addressing Modes (Lect-09)
• Register Addressing Mode, Immediate Addressing Mode, Direct Data
Addressing, Register Indirect Addressing, Base-Plus-Index Addressing,
Register Relative Addressing, Base Relative-Plus-Index Addressing
• Chapter-04: Data Movement Instructions (Lect-10)
• Machine Language: The Opcode, MOD field, Register Assignment,
R/M Assignment, Special Addressing Mode, 32-bit Addressing Mode
• Data Movement Instructions: An immediate instruction, MOV, MOVSX,
MOVZX, PUSH and POP instructions 5
Previously (Lecture: 1-12)
• Chapter-04: Data Movement Instructions (Lect-11)
• LEA, LDS, LES, LFS, LGS, LSS,
• String instructions: MOVS, LODS, STOS, INS, and OUTS.
• Miscelenious: XCHG, XLAT, IN, OUT, LAHF, SAHF
• Assembler Details: Directives, Storing Data in Memory Segment,
ASSUME, EQU, ORG, PROC and ENDP
• Chapter-05: Arithmetic and Logic Instructions (Lect-12)
• Addition: 8-bit, 16-bit, 32-bit, ADC, INC, Register Add.,
Immediate Add., Mem-Reg Add., Array Add.
• Subtraction: 8-bit, 16-bit, 32-bit, SBB, DCR
• 8-bit, 16-bit, 32-bit Multiplication
• 8-bit, 16-bit, 32-bit Division, Remainder
• BCD and ASCII Arithmetic
6
Recommended Books
1. Text Book
• Intel Microprocessors: Architecture, Programming and
Interfacing, 8th Edition
by Barry B Brey, Prentice Hall
2. Reference Book
• Assembly Language for IBM-PC, 2nd Edition,
by Kip R. Irvine, Maxwell Macmillan Publishing Company

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Lecture outline
• Basic Logic Instructions
• Introduction
• Basic Logic operations
• AND Instructions
• OR Instructions
• Exclusive-OR Instructions
• NOT Instructions
• NEG (similar to the NOT instruction)
• Shift (Left, Right) Instructions
• Rotate (Left, Right) Instructions
• String comparison
• SCAS (Scan String), CMPS (Compare String)

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Basic Logic Instruction
• Include AND, OR, Exclusive-OR, and NOT
• also TEST, a special form of the AND instruction
• NEG, similar to the NOT instruction

• Logic operations provide binary bit control in low-level

software
• Allow bits to be set, cleared, or complemented
• Low-level software appears in machine language or assembly
language form and often controls the I/O devices in a system

• All logic instructions affect the flag bits

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Basic Logic Instruction
• Logic operations always clear the carry and overflow flags
• other flags change to reflect the result

• When binary data are manipulated in a register or a memory

location, the rightmost bit position is always numbered bit 0
• position numbers increase from bit 0 to the left, to bit 7 for a byte, and
to bit 15 for a word
• a doubleword (32 bits) uses bit position 31 as its leftmost bit and a
quadword (64-bits) position 63

10
 AND
• Performs logical multiplication, illustrated by a truth table

• In 8086, the AND instruction often executes in about a

microsecond
• with newer versions, the execution speed is greatly increased

Figure 5–3 (a) The truth table for the AND operation and (b) the logic symbol of an AND gate. 11
AND
• AND clears bits of a binary number
• called masking
• AND uses any mode except memory-to-memory and segment register
addressing

• An ASCII number can be converted to BCD by using AND to mask off the
leftmost four binary bit positions

Figure 5–4 The operation of the AND function showing how bits of a number are cleared
to zero.
12
OR
• Performs logical addition
• often called the Inclusive-OR function

• The OR function generates a logic 1 output if any inputs are 1

• a 0 appears at output only when all inputs are 0
• Figure 5–6 shows how the OR gate sets (1) any bit of a binary number

• The OR instruction uses any addressing mode except segment

register addressing

13
Figure 5–5 (a) The truth table for the OR operation and (b) the logic symbol of an OR gate.

Figure 5–6 The operation of the OR function showing how bits of a number are set
to one. 14
Exclusive-OR
• Differs from Inclusive-OR (OR) in that the 1,1 condition of
Exclusive-OR produces a 0
• a 1,1 condition of the OR function produces a 1

• The Exclusive-OR operation excludes this condition; the

Inclusive-OR includes it

• If inputs of the Exclusive-OR function are both 0 or both 1,

the output is 0; if the inputs are different, the output is 1.

• Exclusive-OR is sometimes called a comparator

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 Exclusive-OR

Figure 5–7 (a) The truth table for the Exclusive-OR operation and (b) the logic symbol of an
Exclusive-OR gate.
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Exclusive-OR
• XOR uses any addressing mode except segment register
addressing
• Exclusive-OR is useful if some bits of a register or memory
location must be inverted.

• Figure 5–8 shows how just part of an unknown quantity can

be inverted by XOR.
• when a 1 Exclusive-ORs with X, the result is X
• if a 0 Exclusive-ORs with X, the result is X

• A common use for the Exclusive-OR instruction is to clear a

register to zero

17
Figure 5–8 The operation of the Exclusive-OR function showing how bits of a number are
inverted.

18
NOT and NEG
• NOT and NEG can use any addressing mode except segment
register addressing

• The NOT instruction inverts all bits of a byte, word, or

doubleword

• NEG two’s complements a number

• the arithmetic sign of a signed number changes from positive to
negative or negative to positive

• The NOT function is considered logical, NEG function is

considered an arithmetic operation.

19
Shift and Rotate
• Shift and rotate instructions manipulate binary numbers at the
binary bit level
• as did AND, OR, Exclusive-OR, and NOT

• Common applications in low-level software used to control

I/O devices

• The microprocessor contains a complete complement of shift

and rotate instructions that are used to shift or rotate any
memory data or register

20
Shift
• Position or move numbers to the left or right within a register
or memory location
• also perform simple arithmetic as multiplication by powers of 2+n (left
shift) and division by powers of 2-n (right shift)

• The microprocessor’s instruction set contains four different

shift instructions:
• two are logical; two are arithmetic shifts
• All four shift operations appear in Figure 5–9

21
 – logical shifts move 0 in the
rightmost bit for a logical left shift;
– 0 to the leftmost bit position for a
logical right shift
– arithmetic right shift copies the
sign-bit through the number
– logical right shift copies a 0
through the number.

Figure 5–9 The shift instructions showing the operation and direction of the shift.
22
Shift
• Logical shifts multiply or divide unsigned data; arithmetic
shifts multiply or divide signed data
• a shift left always multiplies by 2 for each bit position shifted
• a shift right always divides by 2 for each position
• shifting a two places, multiplies or divides by 4

23
Rotate
• Positions binary data by rotating information in a register or
memory location, either from one end to another or through
the carry flag
• used to shift/position numbers wider than 16 bits
• With either type of instruction, the programmer can select
either a left or a right rotate.
• Addressing modes used with rotate are the same as those used
with shifts.
• Rotate instructions appear in Figure 5–10.
• A rotate count can be immediate or located in register CL.
• if CL is used for a rotate count, it does not change

• Rotate instructions are often used to shift wide numbers to the

left or right. 24
Figure 5–10 The rotate instructions showing the direction and operation of each rotate.
25
String Comparison
• String instructions are powerful because they allow the
programmer to manipulate large blocks of data with relative
ease

• Block data manipulation occurs with MOVS, LODS, STOS,

INS, and OUTS.

• Additional string instructions allow a section of memory to be

tested against a constant or against another section of memory.
• SCAS (string scan); CMPS (string compare)

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SCAS
• Compares the AL register with a byte block of memory, AX
with a word block, or EAX with a doubleword block of
memory

• Opcode used for byte comparison is SCASB; for word

comparison SCASW; doubleword comparison is SCASD

• SCAS uses direction flag (D) to select auto-increment or auto-

decrement operation for DI.
• also repeat if prefixed by conditional repeat prefix

27
CMPS
• Always compares two sections of memory data as bytes
(CMPSB), words (CMPSW), or doublewords (CMPSD)
• contents of the data segment memory location addressed by SI are
compared with contents of extra segment memory addressed by DI
• CMPS instruction increments/decrements SI & DI

• Normally used with REPE or REPNE prefix

• alternates are REPZ (repeat while zero) and REPNZ
(repeat while not zero)

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 Thank you
Dr. Shahid Latif
Associate Professor, CS-IT, SUIT, Peshawar

shahid.csit@suit.edu.pk

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar

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