Synthesis Constraints

Logic Cell Selection

 Synthesis tool perform timing analysis to drive a logic

cell selection.

 It considers the worst possible delay through each logic

element(but not the logical operation) propagates delays
through each timing paths.

 Calculated delay amount must not be more then clock

period.
Constraint Driven Synthesis

 Constraints define limits for circuit

parameters
 This is done by specifying
 Maximum area
 Maximum power
 Timing details and desired delays of paths
 Constraints are used by synthesis for
decision making and prioritizing
Timing

 Timing parameters are considered as having highest

priority as design must meet the timing constraints in
order to operate at the intended clock rate.
 synchronous circuits It means that correct data must
present at the data input of each synchronous device
when the clock edge arrives, under all possible
conditions. Otherwise timing issues will exists and
effective data will be lost.
Timing Paths

 For proper constraining, designs optionally divided into

separate groups:
 Input-to-register timing paths
 Register-to-register timing paths
 Register-to-output timing path

dashed arrows represent a timing paths.

Input-to-register Register-to-register
Register-to-output

D Q Combo D Q Combo Combo

IN Combinational D Q logic D Q OUT
logic

CLK CLK
CLK
Timing Paths (Startpoint-Endpoint)

 Each timing path has a startpoint and an endpoint.

 The startpoint is a place where data is launched by a
clock edge:
 A sequential element’s clock pin
 An input port of the design
 Data is propagated through the path and then captured
at the endpoint by another clock edge:
 A sequential element’s data input pin
 An output port of the design
Constraining Paths on Boundaries

 Clock set constraints on all reg-to-reg paths

 For boundaries paths additional data is required:
 For the input paths the arrival time of the data is unknown.
 For an output path of the design the external logic delays
are unknown.
 In order to analyze the input-to-register and register-to-output
timing, external timing conditions must be specified
 input delay is defined as external delay before input

 output delay is defined as delay of circuitry between output

and next register

Input Delay

 The input delay is the CLK-to-IN external

delay.
Input delay

IN D Q
CLK

CLK
Input Delay
Design

IN
tc

tDFF

CLKA

First clock edge

launches data

set_input_delay -clock CLKA -max [expr TDFF + Tc]

[get_ports IN]
Output Delay

 The output delay includes the delay of the

external buffer and the timing requirements
for the external flip-flop.
output delay

D Q OUT D Q
Output Delay

Design tc
tsetup

out

CLK

set_output_delay -clock CLK -max [exp tc + tsetup] [get_ports

OUT]
Timing Budgeting

 Usually the delays on inputs or outputs are not known

 In this cases time budget is used which is estimation of
delays, with enough margin for connection to real
circuitry.

Block A ?
Input My Design Ouput
? Block A
pin pin

CLK
Recommended Timing Budgeting

 It is recommended to set input delay and output delay equal to 40% of

clock period.
 If this kept in all digital circuits then after connection to each other there will
be 20% period margin, which will compensate possible variations

40% of clock period

My Design

… D Q
Output
logic
Input
logic D Q …

CLK

40% of clock period

Constraining Combinational Paths
by Virtual Clock
 In some cases it is necessary to create a clock
that exists in the system but not within the
design.
 When a source object is not specified a virtual
clock is used, which does not physically exist in
the design.
 The source object represents the place of the
clock in the design. A source object can be an
input port of a design or a pin inside a design.
Constraining Combinational Paths
by Virtual Clock (2)
 The virtual clock has no sources.
 It exists in memory but is not part of a design.
 The virtual clock specifies input and output
delays relative to a clock
 Virtual clock is not connected to any port or
pin within the current design.
Combinational Designs

 Combinational circuit is put in the same clocked environment as the clocked

one
 An abstract clock called “Virtual clock” is defined for this environment
 By setting correct clock period, input/output delays of the combinational
logic can be controlled

Combinational D Q
D Q Logic DFF
DFF
CLK
CLK

Clock
Delaymax= Tclk– Delayin – Delayout=7ns Delayout=3ns
Delayin=1ns
Input Path with Virtual Clock
0.1
t=3
Design
IN
D Q D Q

VSLK CLK
CK CK

Tsetup=0.5

VCLK

0 5 10
3.1 9.5
Setup check

CLKM

Data required
Data arrives

create_clock -name VCLK -period 10 -waveform {0 5}

set_input_delay -clock VCLK -max 3 [get_ports INA]
Constraining Combinational Paths
by Virtual Clock (3)

Assumed external Assumed external

Current Design
launching circuitry capturing circuitry

D Q Combinational D Q
logic
CLK

 This design constrains by using a virtual clock.

Defining Clocks

 Main attributes of clocks

Period

Ideal clock
Latency

Rise Fall
Uncertainty
 To determine exact times for clock edges the following clock characteristics
must be specified:
 Period
 Transition time
 Waveform
 Latency
 Uncertainty
Modeling Parameters

 At the logic synthesis step tool assumes ideal

clock (zero uncertainty, latency, transition),
because it doesn’t know actual interconnect
sizes, and parasitic parameters affecting
signals.
 That’s why this parameters must be modeled
at the logic synthesis step.
Basic Clock Details

 Clock Definition Components:

 Source
 Port of a design
 Period
 Time period of the clock (frequency)
 Duty cycle
 Positive and negative phase
 Edge times
 Rising edge and falling edge
 Variability
 Changes in frequency
Clock Definition

Design
CLK
CLK
5 10 15
0
CLKB

T=10

create_clock -name CLK -period 10 [get_port CLKB]

Clock Waveform
High duration

Design Low duration

CLK
CLK
5 10 15
0
CLKB

T=10

CLKB

0 3 5 7 9 10 13 15

T=10

create_clock -period 10 \
-waveform {3 5 7 9 } [get_port CLKB]
Divided Clock (Generated)

SRC DIV
CLK1
CLK1 CLK2
Clock CLK
Frequency CLK
source divider
CLK CLK2

create_clock -name CLK1 10 [get_pins SRC/CLK]

create_generated_clock -name CLK2 -source SRC/CLK -divide_by
2 [get_pins DIV/CLK]
Multiplied Clock (Generated)

CLK1
0 10 20

CLK2

0 5 10 15

create_clock -period 10 -waveform {0 5} [get_ports CLK1]

create_generated_clock -name CLK2 -source [get_ports CLK1] -multiply_by 2
[get_pins MULT/CLK]
Gated Clock (Generated)

D Q

CLK G1
CLKG
CLK1 Z

create_clock 10 [get_ports CLK1]

create_generated_clock -name CLKG -divide_by 1 -source CLK1
[get_pins G1/Z]
Generated by Edges

1 2 3 4 5 6 7 8 9 10

CLK

CLK2

CLK1

create_clock 2 [get_ports CLK]

create_generated_clock -name CLK1 -edges {3 4 7} -source DCLK [get_pins
G1/Z]
create_generated_clock -name CLK2 -edges {2 4 6} -source DCLK [get_pins
G2/Z]
Modeling Clock: Clock Latency

 The time that takes for the clock to be

propagated from the clock source to the
sequential elements in the design is called
latency that consists of following two
components:
 Source latency
 Network latency.
Modeling Clock: Clock Latency (2)

 Source latency is the delay from the clock source to the clock
definition pin in the design.
 Network latency is the delay from the clock definition point to the
register clock pin.
Current
design
D Q

Source Network
latency latency

Origin of Clock definition

clock point in design
Clock Latency

set_clock_latency 0.9 [get_clocks / CLK

set_clock_latency 0.8 –source / [get_clocks CLK]

set_clock_latency 0.7 -source -min /

[get_clocks CLK]

set_clock_latency 0.3 -source -max /

[get_clocks CLK]
Latency of Generated Clock

 Generated clock total latency is the sum of:

 Master clock source latency
 Generated clock source latency
 Generated clock network latency

Master clock Generated

Clock source definition clock definition

D Q

CLK

Master clock Generated clock Generated clock

Source latency Source latency network latency

Modeling Clock: Uncertainty

… D Q … D Q

A B
CLK

CLK(A)

CLK(B)
Skew

 The greatest difference between the arrival of clock signals at registers in

one clock domain or between domains is uncertainty.
Modeling Clock: Uncertainty (2)

D Q D Q

D Q D Q
CLK
CLK1 CLK2

 The variation in the generation of a clock’s successive

edges with respect to the nominal times represents
simple uncertainty.
 The variation in skew between different clocks’ edges
represents interclock uncertainty.
Modeling Clock: Uncertainty (3)

Uncertainty

Jitter Margin Skew

Clock Jitter

Ideal
Reference

Actual
Waveform

T T+ ∆T1 T+ ∆T2 T+ ∆T3 T+ ∆T4

Clock Uncertainty

Setup uncertainty

CLKB

Effective period Hold uncertainty

Uncertainty= clock skew + clock jitter

set_clock_uncertainty -setup 0.4 [get_clocks CLKB]

set_clock_uncertainty -hold 0.04 [get_clocks CLKB]
Modeling Clock: Transition Time

 The time during which a signal changes from

logic low to logic high (rise time), or from logic
high to logic low (fall time) represents the
transition time.
 The delay at the output and the transition
time of the output signal are affected by the
transition time at the input.
Area Constraints

 Area constraints are given by limiting maximum

area value
 As timing has greater priority in Design Compiler
it is used to set maximum area to zero, thus
optimization achieves the best possible area
with timings met