BACSE103 –Computation Structures(3-0-2-4)
Module -1:
Module1 : Digital Systems and Combinational Circuits (7 Hours)
Introduction to Digital Systems-Number System, Data representation:
Fixed and Floating point, Logic gates, Simplification of Boolean function
using K-map, Design of Combinational circuit: Adder, Carry-ahead adder,
Encoder and Decoder, Multiplexer and Demultiplexer
Dr. I. Mala Serene, SCORE,VIT
Decoder
• Discrete quantities of information in digital systems→ binary
codes
• Is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
• For example if the number of input is n=3 the number of
output lines can be m=23 . It is also known as 1 of 8 because
one output line is selected out of 8 available lines:
2-to-4 Decoder
B’
A’
B
A’
B’
A
3 * 8 decoder
• Three inputs
decoded to 8
outputs
• Each output
represent of the
minterms of the 3-
input variables.
Decoder with Enable Line
• Decoders usually have an enable line,
• If enable=0 , decoder is off. It means all output
lines are zero
• If enable=1, decoder is on and depending on
input, the corresponding output line is 1, all
other lines are 0
• See the truth table in next slide
Truth table for 3-to-8 decoder with
Enable Line
E D2 D1 D0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
-----------------------------------------------------------
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1
1 ……………………………………….
1 ……………………………………..
1
1
1 1 1 1 1 0 0 0 0 0 0 0
Implement a full adder circuit with a decoder
circuit and two OR gates
Example 3: 4-to-16 Decoder
A3 A2 A1 A0 Output
• Problem: Design a 4x16 Decoder 0 0 0 0 D0
0 0 0 1 D1
using 2x4 Decoders A3A2 = 00
0 0 1 0 D2
0 0 1 1 D3
• Solution: 0 1 0 0 D4
0 1 0 1 D5
• Each group combination holds a A3A2 = 01
0 1 1 0 D6
unique value for A3A2
0 1 1 1 D7
• - One Decoder can be 1 0 0 0 D8
therefore used with inputs: A3A2 A3A2 = 10
1 0 0 1 D9
1 0 1 0 D10
• - Four more decoders are
1 0 1 1 D11
needed for representing each 1 1 0 0 D12
individual color combination 1 1 0 1 D13
A3A2 = 11
1 1 1 0 D14
1 1 1 1 D15
Example 3: 4-to-16 Decoder
D0
A0 2x4 D1
Decoder D2
A1 D3
D4
A0 2x4 D5
A1 Decoder D6
D7
A2 2x4
A3 Decoder
D8
A0 2x4 D9
Decoder D10
A1 D11
D12
2x4 D13
A0
Decoder D14
A1 D15
Encoder
• Encoder is a digital circuit that
performs the inverse operation
of a decoder
• Generates a unique binary
code from several input lines.
• Generally encoders produce 2-
bit, 3-bit or 4-bit code. n bit
encoder has 2n input lines
Octal to Binary Encoder
• Encoder can be implemented with OR gates.
• Ouput Z=1(when octal digit→1,3,5 or 7)
• Ouput y=1(when octal digit→2,3,6 or 7)
• Ouput x=1(when octal digit→4,5,6 or 7)
• Boolean function can be expressed as:
Octal to Binary Encoder
Octal to Binary Encoder
Multiplexer
• It is a combinational circuit that selects binary
information from one of the input lines and directs it
to a single output line
• Usually there are 2n input lines and n selection lines
whose bit combinations determine which input line
is selected
• For example for 2-to-1 multiplexer if selection S is
zero then I0 has the path to output and if S is one I1
has the path to output (see the next slide)
2-to-1 multiplexer
Logic symbol for a 1-of-4 data selector/multiplexer.
Three-State Gates
• Three state gates exhibit three states instead
of two states. The three states are:
• high : 1
• Low : 0
• High impedance : In that state the output is
disconnected which is equal to open circuit. In
the other words in that state circuit has no
logic significant.
Three-state buffer
C A Y
----------------------
0 0 z
0 1 z
1 0 0
1 1 1
Three-state buffers can be used to implement
multiplexer
Cascading multiplexers
Using three 2-1 MUX
to make one 4-1 MUX
S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Quadruple 2–to–1-Line Multiplexer
E S Y
(Enable) (Select) (Output)
0 X All 0’s
1 0 A
1 1 B
Notice enable bit
Notice select bit
4 bit inputs
Implementation of 8x1 Mux Using 4x1 Mux
Design a 16−to−1 multiplexer using two 8−to−1 multiplexers having an active LOW
ENABLE input.
S3 S2 S1 S0 Y
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15
16−to−1 multiplexer using two 8−to−1
multiplexers
Summary
• Multiplexers are fundamental digital components
• Can be used for logic
• Useful for datapaths
• Scalable
• Tristate buffers have three types of outputs
• 0, 1, high-impedence (Z)
• Useful for datapaths
Demultiplexer
Application of DeMUX
A 1-line-to-4-line demultiplexer.
Boolean Function Implementation
Problem1: Implementing F(A,B,C)=∑(1,3,5,6)
Boolean Function Implementation
Problem2: Implementing F(A,B,C)=∑(1,2,4,5)
Problem 3
Demultiplexer
Application of DeMUX
A 1-line-to-4-line demultiplexer.
Boolean Function Implementation
Problem1: Implementing F(A,B,C)=∑(1,3,5,6)
Boolean Function Implementation
Problem2: Implementing F(A,B,C)=∑(1,2,4,6)
Problem 3
References
• Digital Logic and Computer Design by Morris Mano
