Topic 1
Introduction to Digital
Systems Design
Dr Chua Sing Yee
Overview
◼ Digital Systems
◼ Combinational Logic
Gates
Logic Representations
Design Process
◼ Sequential Logic
Synchronous Sequential
Asynchronous Sequential
Latches
Flip-flops
◼ Digital System Modules
◼ Implementation Technologies
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Digital Systems
◼ Structure: a collection of interconnected digital modules designed to
perform a particular service or function.
◼ Function: takes a set of discrete information inputs with/without
discrete internal information (system state) and generates a set of
discrete information outputs.
Discrete
Discrete Information Discrete
inputs Processing outputs
System
System state
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Combinational vs Sequential Logic
Combinational Logic Sequential Logic
No state present State present
output = function (input) output = function (input, previous input)
No memory Uses memory i.e. flip-flops, RAM, ROM
Described by truth table Described by state diagram/table
Faster Slower
Easy to design Harder to design
Examples: gates, multiplexers, decoders, Examples: state machines, counters, shift
ALUs registers 4
Combinational Logic
◼ Digital logic circuits without memory.
◼ Interconnected network of standard logic gates
such as AND, OR, NAND, XOR, etc.
◼ In principle static and time does not play a major
role except for practical issues such as glitches.
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Gates
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Combinational Logic: Representations
1. Truth table
2. Boolean/logic equation
3. Logic diagram (schematic)
Unique
Truth table
Not unique Not unique
Boolean/logic Logic diagram
equation (schematic)
Convenient for Close to
manipulation implementation
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Combinational Logic: Design Process
1. Create truth table from specification
2. K-map minimization to obtain logic equation
3. Draw logic diagram
4. Simulate circuit for design verification
5. Circuit analysis and optimization
6. Re-simulate and verify optimized design
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Sequential Logic
◼ Can be classified based on the timing of their signals:
Synchronous sequential logic
◼ state changes at discrete instants of time
Asynchronous sequential logic
◼ state changes at any instant of time
◼ Behaviour is given by state diagram or table
next state = function (present state, input)
output = function (present state) → Moore Machine
output = function (present state, input) → Mealy Machine
◼ When the number of state variables is finite, the sequential
circuit is called a Finite State Machine (FSM)
◼ Latches and flip-flops are the basic building blocks 9
Synchronous vs Asynchronous
Sequential Logic
Synchronous Sequential Logic Asynchronous Sequential Logic
Memory elements are clocked flip- Memory elements are unclocked flip-
flops flops or time delay elements
Change in input can affect memory Change in input can affect memory
element upon activation of clock signal element at any instant of time
(clockless)
Slower Faster as clock is not present
Easier to design More difficult to design, harder to
analyse operations
Examples: edge-triggered D flip-flop, Example: SR latch
registers
More in Synchronous More in Asynchronous
Sequential topic Sequential topic
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Latches
◼ Basic memory elements, not clocked.
◼ Outputs change whenever the inputs change.
◼ Examples:
SR latch
Gated SR latch
Gated D latch (Data latch)
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SR latch
Logic diagram/circuit
Using NOR gates Truth table
No change
Reset
Set
Not allowed
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SR latch
Symbol
State diagram
State table
Next state
equation, Q+
(Or Last Q)
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SR latch
State table
State diagram
or
Excitation input
State table
Q Q+ S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
*Both carry the same meanings
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Gated SR latch
◼ An S-R latch is sensitive to its inputs at all times and glitches to its
inputs can cause the outputs to change.
◼ To avoid this, an extra input G can be added to the latch.
◼ When G=0, no change can occur; when G=1, the behavior is same
as S-R latch.
Control the S & R inputs 15
Gated D latch
◼ Either set or reset → combined gated SR inputs → gated
D latch (Data latch)
Truth Table Gated D Latch
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State Table
Next state equation
State diagram
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Flip-flops
◼ Flip-flop = latch with clock input
◼ Basic memory elements in clocked circuits.
◼ Overcomes problem with latches where glitches or noise may cause
inputs to change and store wrong data → the outputs change
according to the inputs only at the arrival of clock signals.
◼ Examples:
Edge-triggered D flip-flop
Edge-triggered JK flip-flop
T flip-flop
(Toggle)
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Edge-triggered D flip-flop
◼ Two D latches: L1 master, L2 slave
◼ CLK low, master is opened, slave is closed → P = D
◼ CLK high, master is closed, slave is opened → Q = P = D (input at the rising edge)
Positive edge-triggered DFF
D must be stable
within this time
setup time hold time
propagation delay
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* The output Q only change to the input D at the
rising edge (positive edge) OR falling edge
(negative edge) of the clock (CLK)
Truth Table Rising (positive)
edge-triggered DFF State Table
Falling (negative)
edge-triggered DFF Next state equation
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Edge-triggered JK flip-flop
Symbol for JK FF State diagram
State table
Next state equation, Q+
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Edge-triggered JK flip-flop
* Implement
using DFF
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T flip-flop (Toggle flip-flop)
Symbol for TFF
State diagram
State table
Next state equation, Q+
hold
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T flip-flop
* Implement using JK FF
* Implement using DFF
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Flip-flop
◼ Characteristic or next state tables are used in analysis.
◼ Excitation tables are used in design → given the
transition from present state to next state, determine the
flip-flop inputs.
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Flip-flop with additional inputs
1. Enable input
The flip-flop remembers when enable is low and it can be
triggered when the enable is high.
2. Preset and Clear input
For initialization, those inputs will either set or clear the flip-flop
when activated
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Flip-flop with additional inputs
2. Preset and Clear input
* Active high preset and clear
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Flip-flop with additional inputs
2. Preset and Clear input
* Active low preset and clear
active low
asynchronous
inputs
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Digital System Modules
◼ Low level digital modules
Gates - AND, OR, NOR, etc.
Blocks - adder, subtractor, shifter, etc.
◼ High level digital modules
PLDs (Programmable Logic Device)
ASICs (Application Specific Integrated Circuits)
Microprocessors/Microcontrollers
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Implementation Technologies
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Implementation Technologies
◼ PLD (Programmable Logic Device)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
Simple Programmable Logic Device (SPLD)
◼ Refers to PLA or PAL
Complex Programmable Logic Device (CPLD)
◼ Arrangement of multiple SPLDs on single chip
Field Programmable Gate Array (FPGA)
◼ General structure that allows very high logic capacity
◼ ASIC (Application Specific Integrated Circuits)
microchip designed for a special application
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Implementation Technologies
◼ Start with gates (standard logic): AND, OR, NAND, NOR, NOT, etc.
These blocks are implemented with SSI (requires the most
wiring)
◼ Progress to building blocks: Registers, Counters, Shift Registers,
Multiplexors, Selectors, etc.
These blocks are implemented with MSI (requires less wiring)
◼ Progress to PLDs, FPGAs, ASICs, Full Custom VLSI chips
These blocks require the least wiring
◼ FPGA chips are very complicated
Designing them with gates is not very productive and error prone
We need Hardware Description Language (HDL) to specify the
programming of FPGAs
More in HDL topic
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CPLD vs FPGA
CPLD FPGA
Architecture PLA or PAL-like Gate array-like
Basic cell Product term Configurable Logic Block
(CLB) & Look-up Table (LUT)
Equivalent gates 200-12,000 1000-1,000,000
Performance Predictable timing Application dependent
Design entry Equation & schematic Schematic & HDL
Application Combinational based Register based
Examples of Address coding, control Prototyping, hardware
applications logic, etc reconfiguration, digital signal
processing, etc
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ASIC vs FPGA
ASIC FPGA
Design style Custom design, User or field programmable,
application specific reusable
Design flow/cycle Complex Simpler
Time to market Slow Fast
Non-recurring High Low, suitable for prototype
engineering (NRE) designs
cost
Unit cost Low, suitable for high High
volume designs
Performance Faster Slower
Power consumption Low Higher
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