Architecture of 8085 Microprocessor

by Dr. Rashmi Panda

Dept. of Electronics and communication Engineering
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, RANCHI
Intel 8085 Microprocessor
 8 bit microprocessor
 40 pin IC package
 The basic version operates with 3 MHz
 8085AH operates with 5 MHz AND M8085AH with 6MHz
 Requires +5 v power supply
Internal Architecture of 8085
 Registers

General Purpose Registers

 The 8085 has 6 general purpose registers to store 8-bit data during program execution.

 These 6 registers are identified as B, C, D, E, H and L.

 They can be combined as register pairs BC, DE and HL to perform some 16-bit operations.

 These registers are programmable. It can be used to load or transfer data from the registers by

using instructions.
Special Purpose Registers

Accumulator

 The accumulator (A) is an 8-bit register that is part of ALU.

 It is used to store 8-bit data and to perform ALU operations.

 The result of an operation is stored in Accumulator.

 The Accumulator is identified as register A.

 The data on which operations is to be performed is operand. One of the operands must be
stored in Accumulator.
Special Purpose Registers
Program Counter (PC)

 This 16-bit register deals with sequencing the execution of instructions.

 This register is a memory pointer. Memory locations have 16-bit address.

 The microprocessor uses this register to sequence the execution of the instructions.

 The function of the program counter is to point to the memory address from which the next byte is
to be fetched.

 When a byte is being fetched, the program counter is automatically incremented by one to point to

the next memory location.

Special Purpose Registers
Stack Pointer (SP)

 The stack pointer is also a 16-bit register, used as a memory pointer.

 It points to a memory location in R/W memory, called stack.

 The beginning of the stack is defined by loading 16- bit address in the stack pointer. (Holds
the address of the top of the stack)
Special Purpose Registers
Flag register

 The ALU includes five flip-flops, which are set (or) reset after an operation according to data
condition of the result in the accumulator and other registers.

 They are called Zero (Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags.

 Their bit positions in the flag register are shown in Fig. below. The microprocessor also uses
these flags to test data conditions.

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY
 D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY
Sign Flag
Used for indicating the sign of the data in the
accumulator
The sign flag is set if negative (1 – negative)
The sign flag is reset if positive (0 – positive)
Zero Flag
10110011
 Is set if result obtained after an operation is 0
+ 01001101
 Is set following an increment or decrement operation of a register ---------------
Carry Flag 1 00000000

 Is set if there is a carry or borrow from arithmetic operation

1011 0101 1011 0101

+ 0110 1100 - 1100 1100
--------------- ---------------
Carry 1 0010 0001 Borrow 1 1110 1001
Auxillary Carry Flag
 Is set if there is a carry out of bit D3
 Generally used in BCD operations
 Not available for the programmer to change the sequence of a
program with jump instruction

 Parity Flag
 Is set if parity is even (even number of ones in the result)
 Is cleared if parity is odd
Non Programmable Registers

Instruction register and Decoder

 The instruction register and decoder are part of the ALU.

 When an instruction is fetched from the memory, it is loaded in to the instruction
register.
 The decoder decodes the instruction and establishes the sequence of events to
follow.
 The instruction register is not programmable and cannot be accessed by any
instruction.
Non Programmable Registers

Register Array (W&Z)

 There are two additional registers called W and Z, which are included in the
register array along with programmable registers namely B, C, D, E, H, L, SP
and PC.

 These registers are used to hold 8-bit data during the execution of
instructions. However, they are used internally by microprocessor, they are
not available to the programmer.
Non Programmable Registers

Incrementer/Decrementer address latch

 This 16-bit register is used to increment or decrement the contents of
program counter or stack pointer as part of execution of instructions
related to them.
Grouping of Signals of 8085 Microprocessor
 Power supply and frequency signals
 Address bus signals
 Data bus signals
 Control and status signals
 Serial I/O port signals
 Externally initiated signals & external signal acknowledgement
Power Supply and Frequency Signals

 Vcc + 5-volt power supply

 Vss Ground

 X1, X2: Crystal or R/C network or LC network connections to set the frequency of
internal clock generator. The frequency is internally divided by two. Since the basic
operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally.

 CLK (out) – Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor. This signal is used for synchronizing external
devices.
Address bus signals, Data bus signals
AD0-AD7
• These are multiplexed address and data bus.
• It can be used to carry the lower order 8-bit address as well as the data. Generally, these
lines are demultiplexed using the Latch.
• During the opcode fetch operation, in the first clock cycle the lines deliver the lower order
address bus A0-A7. In the subsequent IO/M read or write it is used as data bus D0-D7. CPU can
read or write data through these lines.

A8-A15
• These are address bus used to address the memory location.

 16 address lines
 Most significant bits (A8-A15) – single directional
 Least significant bits (AD0-AD7) – bidirectional
Control and status signals
 Helps the microprocessor unit coordinating and controlling different operations
 Control bus carries the control signals.

 Status_Signals
 IO/M
 S1, S0
 Control
_ _Signals
 RD, WR & ALE
 Control
_
Signals
 RD
 It is a signal to control READ operation.
 When low the selected memory or input-output device is read.
_
 WR
 It is a signal to control WRITE operation.
 When it goes low the data on the data bus is written into the selected memory or I/O location.

 ALE
 It is an Address Latch Enable signal.
 Primarily used to latch the lower order address from multiplexed bus (AD0-AD7).
 It goes high during first T state of every machine cycle enabling the lower 8-bits of the address (A0-A7),
otherwise data bus is activated.

 The 𝑅𝐷 and 𝑊𝑅 signals are sync pulses indicating the availability of data on the data bus.
Status Signals
_
 IO/M
 Differentiate I/O and memory applications
 High – I/O operations
 Low – Memory operations

 S1, S0
 status signals, to indicate the type of machine cycle in progress
Serial I/O port signals
 SID-Serial Input Data

 SOD-Serial Output Data

 These are used to implement serial data transmission

 In serial transmission the data bits are sent over a single line i.e. one bit at a
time.
Externally initiated signals & signal acknowledgement
 DMA Signals: HOLD, HLDA, READY

 Reset Signals: Reset in, Reset Out

 Interrupt control instructions:INTR, RST 7.5, RST 6.5, RST 5.5, TRAP, INTA

 Reset out, INTA and HLDA are acknowledgement signals. Rest are initiated
signals by peripheral devices.

*DMA: Direct Memory Access

DMA Signals
HOLD:
 Indicates that another device is requesting the use of the address and data buses.
 The MPU, upon receiving the hold request, will release the use of the buses as soon as the completion of current bus
transfer. Internal processing can continue.
 The processor can regain the bus only after the HOLD is removed.
 When the HOLD is acknowledged, the Address, Data RD, WR and IO/M’ lines are tri-stated.

HLDA: (Hold Acknowledge)

 Indicates that the MPU has received the HOLD request and that it will relinquish the bus in the next clock cycle HLDA goes
low after the Hold request is removed.
 The MPU takes the bus one half-clock cycle after HLDA goes low.

READY:
 This signal synchronizes the fast MPU and the slow memory, peripherals.
 If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive
 If READY is low, the MPU will wait an integral number of clock cycle for READY to go high before completing the read or write
cycle.
Reset Signals
Reset in
 Sets the program counter to zero (0000H).
 Resets the interrupt enables and HLDA flip-flops.
 Tri-states the data bus, address bus and control bus.
 Affects the content of processors internal registers randomly.
 On Reset, The Program counter sets to 0000h which causes the 8085 to execute; the first instruction from address 0000H.

Reset Out
 This active high signal indicates that the processor; is being reset.
 This signal is synchronized to the processor clock and it can be used to reset other devices connected in the
system.
Interrupt Signals
 Whenever the interrupt signal is enabled or requested the microprocessor shifts the control from main program to process
the incoming request

 After the completion of request, the control goes back to the main program.

 For example, an Input/output device may send an interrupt signal to notify that the data is ready for input. The
microprocessor temporarily stops the execution of main program and transfers control to I/O device. After collecting the
input data, the control is transferred back to main program.

 Interrupt signals present in 8085 are:

 INTR
 RST 7.5
 RST 6.5
 RST 5.5
 TRAP
Interrupt Signals
INTR
 INTR is maskable interrupt
 The processor saves current program counter into stack and branches to another specified memory location.

RST5.5, RST6.5, RST7.5

 These are maskable interrupt.
 Otherwise known as restart interrupts.
 The processor saves current program counter into stack and branches to another specified memory location.

TRAP
 It is a non-maskable interrupt.
 It has the highest priority.

INTA
 It is interrupt acknowledgement used to acknowledge an interrupt

• All maskable interrupts can be enabled or disabled using EI and DI instructions.

• RST5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
• Priority order of interrupts TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
MUX / DEMUX unit
 This unit is used to select a register out of all the available registers.

 This unit behaves as Multiplexer (MUX) when data going from the register to the internal data bus.

 It behaves as Demultiplexer(DEMUX) when data is coming to a register from the internal data bus of the processor.

 The register select will behave as the function of selection lines at the Mux / Demux.
ALU (Arithmetic and Logic Unit)
 Performs arithmetic operations like +, -, *, / and to perform logical operations like AND, OR, NOT etc

 ALU performs these operations on 8-bit data.

 ALU gets its Input from accumulator and temporary register.

 After processing the necessary operations, the result is stored back in accumulator.

 Flag Flip-flops are set or reset according to the result.

8085 PIN Diagram