Unit 1

Introduction to Microcontroller Architecture

Introduction
Block Diagram and Pin Description
of the 8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timer
Interrupt
Serial Communication
Port Structure
 Why do we need to learn
Microprocessors/controllers?
• The microprocessor is the core of computer
systems.
• Nowadays many communication, digital
entertainment, portable devices, are controlled
by them.
• A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
 Different aspects of a
microprocessor/controller

• Computer hardware: It is any physical device used in

or with your machine.

• Software : It is a collection of codes installed onto

your computer's hard drive
 The necessary tools for a
microprocessor/controller
• CPU: Central Processing Unit
• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
 Microprocessors:
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC
16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports.
• for applications in which cost,
• expansive power and space are critical
• versatility • single-purpose
• general-purpose
Comparison of Microprocessor and Microcontroller

Prof. M. N. Kakatkar
Prof. M. N. Kakatkar
 Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.
Harvard Architecture

Prof. M. N. Kakatkar
1. This system architecture was designed and
recommended by Harvard University
2. According to this architecture the processor is
having two different memory spaces
3. They are data memory and program
memory
4. Therefore the distinction between data
memory and program memory is physical
5. It is connected to the microcontroller or
microprocessor through separate sets of
address, data and control buses
Prof. M. N. Kakatkar
 Advantages and Disadvantages
1. Accessed by separate sets of buses, both
program and data can be accessed
simultaneously
2. Two sets of buses are needed and therefore
relatively complex bus structure
• Examples: MCS 8051
PIC Microcontroller

Prof. M. N. Kakatkar
Von – Neumann Architecture

Prof. M. N. Kakatkar
1. This system architecture was designed and
recommended by Von-Neumann at the
Princeton University
2. As per this architecture, the Processor is having
single memory space. The memory may contain
both data as well as program memory in it
3. The distinction between data memory and
program memory is logical
4. Therefore same memory space shares data as
well as program code
5. It is connected to the processor through a single
set of address, data and control buses

Prof. M. N. Kakatkar
 Advantages and Disadvantages
1. Simple construction, less complex bus
structure
2. Accessed by same set of buses, both program
and data cannot be simultaneously accessed
• Example: MC68HC11

Prof. M. N. Kakatkar
 Microcontroller Architecture
Von Neumann Architecture--- CISC
• Uses one memory spaces for program instructions and data
• Limits operating bandwidth
• Execution of data and code occurs in sequential fashion
• Reduced Speed of Operation
• CISC- Complex Instruction Set Computer

Addr
Addr

Input Control CPU ALU Output

Data Data

Addr Data

Memory
(Program and Data)

Ref: T1: Page No 57-58

 Microcontroller Architecture
Harvard Architecture --- RISC
• Uses two separate memory spaces for program instructions and data
• Improved operating bandwidth
• Allows for different bus widths
• Improved Sped of Operation
• RISC- Reduced Set Set Computer

Addr
Addr

Input Control ALU Output

CPU

Data Data

Addr Data Addr Data

Data
Program Memory
Memory
Ref: T1: Page No 57-58
 The 8051
Microcontroller
 8051 Basic Component
• 4K bytes internal ROM
• 128 bytes internal RAM
• Four 8-bit I/O ports (P0 - P3).
• Two 16-bit timers/counters
• One serial interface
CPU RAM ROM
A single chip
I/O Serial Microcontroller
Timer COM
Port
Port
 Block Diagram
External Interrupts

Interrupt 4k 128 bytes Timer 1

Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

P0 P2 P1 P3 TXD RXD
Addr/Data
 Major 8051 featurs
• only 1 On chip oscillator (external crystal)
• 6 interrupt sources (2 external , 3 internal, Reset)
• 64K external code (program) memory(only read)PSEN
• 64K external data memory(can be read and write) by RD,WR
• Code memory is selectable by EA (internal or external)
• We may have External memory as data and code
Features of 8051 Architecture

1. The 8051 is an 8-bit microcontroller

- The CPU can work on only 8 bits of data at a time
- Data larger than 8-bits has to be broken into 8-bit pieces
to be processed by the CPU.

2. 8-bit CPU with registers A, B, R0-R7 .

3. 16-bit program counter(PC) & data pointer(DPTR) .

4. 8-bit stack pointer.

5. Internal ROM- 4K bytes(ROM amount indicates on-chip

program space)
6. Internal RAM-128 bytes

7. Two 16-bit timers

8. One serial port

9. 32 I/O pins arranged as 4, 8-bit ports

10. 6 interrupt sources

11. Oscillator & clock circuit

12. 40-pin DIP chip

 Comparison of the 8051 Family
Members
89XX ROM RAM Timer Int IO pin Other
Source
8951 4k 128 2 6 32 -

8952 8k 256 3 8 32 -

8953 12k 256 3 9 32 WD

8955 20k 256 3 8 32 WD

898252 8k 256 3 9 32 ISP

891051 1k 64 1 3 16 AC

892051 2k 128 2 6 16 AC

WD: Watch Dog Timer

AC: Analog Comparator
ISP: In System Programable
8051 architecture(Block diagram)
Registers

- Register are used to store information temporarily, while the

information could be a byte of data to be processed, or
an address pointing to the data to be fetched

-The vast majority of 8051 register are 8-bit registers

-There is only one data type, 8 bits

The most widely used registers

-A (Accumulator)
- For all arithmetic and logic instructions
- B, R0, R1, R2, R3, R4, R5, R6, R7
- DPTR (data pointer), and PC (program counter)
-The 8 bits of a register are shown from MSB D7 to the LSB D0

- With an 8-bit data type, any data larger than 8 bits must be
broken into 8-bit chunks before it is processed
 Registers

A
B
R0 DPH DPL DPTR
R1
R2 PC PC
R3
R4 16-bit Register
R5
R6
R7

8-bit Registers
PSW(Program Status Word)

CY AC F0 RS1 RS0 OV -- P

Carry flag PSW.7 CY

Auxiliary carry flag PSW.6 AC
Available to the user for general purpose PSW.5 --
Register Bank selector bit 1 PSW.4 RS1
Register Bank selector bit 0 PSW.3 RS0
Overflow flag PSW.2 OV
User define bit PSW.1 --
Parity flag Set/Reset odd/even parity PSW.0 P
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
Program Status Word (PSW) register

Also referred to as the flag register, is an 8 bit register

-Only 6 bits are used

These four are CY (carry), AC (auxiliary carry), P(parity),

and OV (overflow)
-They are called conditional flags, meaning that they
indicate some conditions that resulted after an
instruction was executed

The PSW3 and PSW4 are designed as RS0 and RS1, and are
used to change the bank

The two unused bits are user-definable

 8051
Schematic
Pin out
Pin Diagram of the P1.0 1 40 Vcc
8051, & P1.1 2 39 P0.0(AD0
)P0.1(AD1)
P1.2 3 38
Pin description P1.3 4 37 P0.2(AD2
P1.4 5 36 )P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 8051 33 P0.6(AD6)
RST 9 (8031) 32 P0.7(AD7)
(RXD)P3.0 10 (8751) 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(8951)
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 )P2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 )P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
 IMPORTANT PINS (IO Ports)

• One of the most useful features of the 8051 is that it

contains four I/O ports (P0 - P3)
• Port 0 （pins 32-39）：P0（P0.0～P0.7）
– 8-bit R/W - General Purpose I/O
– Or acts as a multiplexed low byte address and data bus for external memory design

• Port 1 （pins 1-8） ：P1（P1.0～P1.7）

– Only 8-bit R/W - General Purpose I/O

• Port 2 （pins 21-28）：P2（P2.0～P2.7）

– 8-bit R/W - General Purpose I/O
– Or high byte of the address bus for external memory design

• Port 3 （pins 10-17）：P3（P3.0～P3.7）

– General Purpose I/O
– if not using any of the internal peripherals (timers) or external interrupts.
• Each port can be used as input or output (bi-direction)
Port 3 Alternate Functions
Vcc（pin 40）：
Vcc provides supply voltage to the chip.
The voltage source is +5V.

GND（pin 20）：ground

XTAL1 and XTAL2（pins 19,18）：

These 2 pins provide external clock.
 Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST
Machine cycle
Machine cycle
Machine Cycle Freq.=1/12 XTAL

• Find the machine cycle for

(a) XTAL = 11.0592 MHz

(b) XTAL = 16 MHz.

• Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 s

(b) 16 MHz / 12 = 1.333 MHz;

machine cycle = 1 / 1.333 MHz = 0.75 s
RST（pin 9）：reset
– It is an input pin and is active high（normally low）.
The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
Upon applying a high pulse to RST, the microcontroller
will reset and all values in registers will be lost.
Reset values of some 8051 registers
Reset values of some 8051 registers

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000

RAM are all zero.

/EA（pin 31）：external access
-There is no on-chip ROM in 8031 and 8032 .
-The /EA pin is connected to GND to indicate the code is
stored externally.
-/PSEN & ALE are used for external ROM.
-For 8051, /EA pin is connected to Vcc.
-“/” means active low.

/PSEN（pin 29）：program store enable

This is an output pin and is connected to the OE pin of the
ROM.
ALE（pin 30）：address latch enable
– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and
data by connecting to the G pin of the 74LS373 latch.

I/O port pins

– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.
Types of Memory

FFFFh External
8051 Chip
DATA
Internal RAM Memory
(up to 64KB)
SFRs 0000h RAM

FFFFh External
Internal code
Memory CODE
(EEPROM) Memory
(up to 64KB)
0000h ROM
RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H
2FH
Bit-Addressable RAM
20H
1FH 4
Register Bank 3
18H Register
17H Banks
Register Bank 2
10H Each
0FH Register Bank 1 bank has
08H R0-R7
(Stack)
07H Selectabl
00H Register Bank 0 e by
PSW.2,3
-Register bank 0 is the default when 8051 is
powered up
Bit Addressable RAM memory
There are 128 bytes of RAM in the 8051
-Assigned addresses 00 to 7FH

The 128 bytes are divided into three different groups as

follows:

1) A total of 32 bytes from locations 00 to 1F hex are set

aside for register banks and the stack.

2) A total of 16 bytes from locations 20H to 2FH are set aside

for bit-addressable read/write memory.

3) A total of 80 bytes from locations 30H to 7FH are used for

read and write storage, called scratch pad.
Stack in the 8051

The register used to access the stack is called SP (stack

pointer) register.

The stack pointer in the 8051 is only 8 bits wide, which

means that it can take value 00 to FFH. When 8051
powered up, the SP register contains value 07.
Example:
MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4

0BH 0BH 0BH 0BH

0AH 0AH 0AH 0AH F3

09H 09H 09H 12 09H 12

08H 08H 25 08H 25 08H 25

Start SP=08H SP=09H SP=08H

SP=07H
8051 Programming Model
SFR-I/0 port bit addresses
 The 8051
Assembly Language Overview
• Data transfer instructions
• Addressing modes
• Data processing (arithmetic and logic)
• Program flow instructions
 Data Transfer Instructions
• MOV dest, source dest  source
• Stack instructions
PUSH byte ;increment stack pointer,
;move byte on stack
POP byte ;move from stack to byte,
;decrement stack pointer

• Exchange instructions
XCH a, byte ;exchange accumulator and byte
XCHD a, byte ;exchange low nibbles of
;accumulator and byte
 Exchange Instructions

two way data transfer

XCH a, 30h ; a  M[30]
XCH a, R0 ; a  R0
XCH a, @R0 ; a  M[R0]
XCHD a, R0 ; exchange “digit”

a[7..4] a[3..0] R0[7..4] R0[3..0]

Only 4 bits exchanged

 Addressing Modes
Immediate Mode – specify data by its value

mov A, #0 ;put 0 in the accumulator

;A = 00000000

mov R4, #11h ;put 11hex in the R4

register
;R4 = 00010001

mov B, #11 ;put 11 decimal in b register

;B = 00001011

mov DPTR,#7521h ;put 7521 hex in DPTR

;DPTR = 0111010100100001
 Addressing Modes
Register Addressing – either source or
destination is one of CPU register
MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV DPTR,#25F5H
MOV R5,DPL
MOV R,DPH

Note that MOV R4,R7 is incorrect

 Addressing Modes
Direct Mode – specify data by its 8-bit address
Usually for 30h-7Fh of RAM
Mov a, 70h ; copy contents of RAM at 70h to a
Mov R0,40h ; copy contents of RAM at 70h to a
Mov 56h,a ; put contents of a at 56h to a
Mov 0D0h,a ; put contents of a into PSW
 Addressing Modes
Register Indirect – the address of the source or destination is
specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0 ; use register bank 0
mov r0, #0x3C
mov @r0, #3 ; memory at 3C gets #3
; Only R0 &R1
Uses DPTR register for 16-bit addresses:
mov dptr, #0x9000 ; dptr  9000h
movx a, @dptr ; a  M[9000]

Note that 9000 is an address in external memory

 Addressing Modes

Register Indexed Mode – source or destination

address is the sum of the base address and
the accumulator(Index)

• Base address can be DPTR or PC

mov dptr, #4000h
mov a, #5
movc a, @a + dptr ;a  M[4005]
 Addressing Modes

Register Indexed Mode continue

• Base address can be DPTR or PC

ORG 1000h
1000 mov a, #5
1002 movc a, @a + PC ;a  M[1008]
PC
1003 Nop

• Table Lookup
• MOVC only can read internal code memory
 SFRs Address

All SFRs such as

(ACC, B, PCON, TMOD, PSW, P0~P3, …)
are accessible by name and direct address
But
both of them
Must be coded as direct address
 Stacks
pop
push

stack pointer

stack

Go do the stack exercise…..

 Stack
• Stack-oriented data transfer
– Only one operand (direct addressing)
– SP is other operand – register indirect - implied
• Direct addressing mode must be used in Push and Pop

mov sp, #0x40 ; Initialize SP

push 0x55 ; SP  SP+1, M[SP]  M[55]
; M[41]  M[55]
pop b ; b  M[55]

Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore,
to push/pop the accumulator, must use acc, not a
 Stack (push,pop)
• Therefore
Push a ;is invalid
Push r0 ;is invalid
Push r1 ;is invalid
push acc ;is correct
Push psw ;is correct
Push b ;is correct
Push 13h
Push 0
Push 1
Pop 7
Pop 8
Push 0e0h ;acc
Pop 0f0h ;b
 Bit-Oriented Data Transfer
• transfers between individual bits.
• Carry flag (C) (bit 7 in the PSW) is used as a single-bit
accumulator
• RAM bits in addresses 20-2F are bit addressable
mov C, P0.0

mov C, 67h
mov C, 2ch.7
 SFRs that are Bit Addressable

SFRs with addresses

ending in 0 or 8 are bit-
addressable.
(80, 88, 90, 98, etc)

Notice that all 4 parallel

I/O ports are bit
addressable.
Data Processing Instructions

Arithmetic Instructions
Logic Instructions
 Arithmetic Instructions

• Add
• Subtract
• Increment
• Decrement
• Multiply
• Divide
• Decimal adjust
 Arithmetic Instructions

Mnemonic Description
ADD A, byte add A to byte, put result in A
ADDC A, byte add with carry
SUBB A, byte subtract with borrow
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
MUL AB multiply accumulator by b register
DIV AB divide accumulator by b register
DA A decimal adjust the accumulator
 ADD Instructions
add a, byte ; a  a + byte
addc a, byte ; a  a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.
Instructions that Affect PSW bits
 ADD Examples
mov a, #3Fh • What is the value of the C,
add a, #D3h AC, OV flags after the
second instruction is
executed?
0011 1111
1101 0011
0001 0010

C = 1
AC = 1
OV = 0
 Subtract

SUBB A, byte subtract with borrow

Example:
SUBB A, #0x4F ;A  A – 4F – C

Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.

Example:
Clr c
SUBB A, #0x4F ;A  A – 4F
 Increment and Decrement
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte

• The increment and decrement instructions do NOT affect the C flag.

• Notice we can only INCREMENT the data pointer, not decrement.
 Multiply
When multiplying two 8-bit numbers, the size of the maximum
product is 16-bits

FF x FF = FE01
(255 x 255 = 65025)

MUL AB ; BA  A * B

Note : B gets the High byte

A gets the Low byte
 Division

• Integer Division
DIV AB ; divide A by B

A  Quotient(A/B)
B  Remainder(A/B)

OV - used to indicate a divide by zero condition.

C – set to zero
 Decimal Adjust

DA a ; decimal adjust a

Used to facilitate BCD addition.

Adds “6” to either high or low nibble after an addition
to create a valid BCD number.

Example:
mov a, #23h
mov b, #29h
add a, b ; a  23h + 29h = 4Ch (wanted 52)
DA a ; a  a + 6 = 52
 Logic Instructions

 Bitwise logic operations

 (AND, OR, XOR, NOT)
 Clear
 Rotate
 Swap

Logic instructions do NOT affect the flags in PSW

 Bitwise Logic
Examples:
ANL  AND 00001111
ORL  OR ANL 10101100
00001100
XRL  XOR
CPL  Complement 00001111
ORL 10101100
10101111

00001111
XRL 10101100
10100011

CPL 10101100
01010011
 Uses of Logic Instructions

• Force individual bits low, without affecting other bits.

anl PSW, #0xE7 ;PSW AND 11100111

• Force individual bits high.

orl PSW, #0x18 ;PSW OR 00011000

• Complement individual bits

xrl P1, #0x40 ;P1 XRL 01000000
 Other Logic Instructions

CLR - clear
RL – rotate left
RLC – rotate left through Carry
RR – rotate right
RRC – rotate right through
Carry
SWAP – swap accumulator nibbles
 CLR ( Set all bits to 0)

CLR A
CLR byte (direct mode)
CLR Ri (register mode)
CLR @Ri (register indirect mode)
 Rotate
• Rotate instructions operate only on a

RL a
Mov a,#0xF0 ; a 11110000
RR a ; a 11100001

RR a
Mov a,#0xF0 ; a 11110000
RR a ; a 01111000
 Rotate through Carry
C
RRC a

mov a, #0A9h ; a  A9
add a, #14h ; a  BD (10111101), C0
rrc a ; a  01011110, C1
C
RLC a

mov a, #3ch ; a  3ch(00111100)

setb c ; c  1
rlc a ; a  01111001, C1
Rotate and Multiplication/Division

• Note that a shift left is the same as multiplying

by 2, shift right is divide by 2

mov a, #3 ; A 00000011 (3)

clr C ; C 0
rlc a ; A 00000110 (6)
rlc a ; A 00001100 (12)
rrc a ; A 00000110 (6)
 Swap

SWAP a

mov a, #72h ; a  27h

swap a ; a  27h
 Bit Logic Operations
• Some logic operations can be used with single bit operands

ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit

• “bit” can be any of the bit-addressable RAM locations or SFRs.

 Program Flow Control

• Unconditional jumps (“go to”)

• Conditional jumps

• Call and return

 Unconditional Jumps

• SJMP <rel addr> ; Short jump,

relative address is 8-bit 2’s complement number,
so jump can be up to 127 locations forward, or 128
locations back.

• LJMP <address 16> ; Long jump

• AJMP <address 11> ; Absolute jump to

anywhere within 2K block of program memory

• JMP @A + DPTR ; Long

indexed jump
 Infinite Loops

Start: mov C, p3.7

mov p1.6, C
sjmp Start

Microcontroller application programs are almost always infinite loops!

 Conditional Jump

• These instructions cause a jump to occur only if a condition

is true. Otherwise, program execution continues with the
next instruction.

loop: mov a, P1
jz loop ; if a=0, goto loop,
; else goto next instruction
mov b, a

• There is no zero flag (z)

• Content of A checked for zero on time
 Conditional jumps
Mnemonic Description
JZ <rel addr> Jump if a = 0
JNZ <rel addr> Jump if a != 0
JC <rel addr> Jump if C = 1
JNC <rel addr> Jump if C != 1
JB <bit>, <rel addr> Jump if bit = 1
JNB <bit>,<rel addr> Jump if bit != 1
JBC <bir>, <rel addr> Jump if bit =1, &clear
bit
CJNE A, direct, <rel addr> Compare A and memory,
jump if not equal
Example: Conditional Jumps
if (a = 0) is true
send a 0 to LED
else
send a 1 to LED

jz led_off
Setb P1.6
sjmp skipover
led_off: clr P1.6
mov A, P0
skipover:
 More Conditional Jumps

Mnemonic Description
CJNE A, #data <rel addr> Compare A and data, jump
if not equal
CJNE Rn, #data <rel addr> Compare Rn and data,
jump if not equal
CJNE @Rn, #data <rel addr> Compare Rn and memory,
jump if not equal
DJNZ Rn, <rel addr> Decrement Rn and then
jump if not zero

DJNZ direct, <rel addr> Decrement memory and

then jump if not zero
 Iterative Loops

For A = 0 to 4 do For A = 4 to 0 do
{…} {…}

mov R0, #4
clr a loop: ...
loop: ... ...
... djnz R0, loop

inc a
cjne a, #4, loop
 Iterative Loops(examples)
mov a,#50h mov a,#25h
mov b,#00h mov r0,#10h
cjne a,#50h,next mov r2,#5
mov b,#01h Again: mov @ro,a
next: nop inc r0
end djnz r2,again
end
mov a,#0aah
mov b,#10h mov a,#0h
Back1:mov r6,#50 mov r4,#12h
Back2:cpl a Back: add a,#05
djnz r6,back2 djnz r4,back
djnz b,back1 mov r5,a
end end
 Call and Return

• Call is similar to a jump, but

– Call pushes PC on stack before branching

acall <address ll> ; stack  PC

; PC  address 11 bit

lcall <address 16> ; stack  PC

; PC  address 16 bit
 Return

• Return is also similar to a jump, but

– Return instruction pops PC from stack to get
address to jump to

ret ; PC  stack
 Subroutines
call to the subroutine
Main: ...
acall sublabel
...
...
sublabel: ...
...
the subroutine
ret
 Why Subroutines?

• Subroutines allow us to have "structured"

assembly language programs.
• This is useful for breaking a large design into
manageable parts.
• It saves code space when subroutines can be
called many times in the same program.
 Initializing Stack Pointer

• SP is initialized to 07 after reset.(Same address as R7)

• With each push operation 1st , SP is increased

• When using subroutines, the stack will be used to store the PC, so it is very
important to initialize the stack pointer. Location 2Fh is often used.

mov SP, #2Fh

 example of delay subroutine

mov a,#0aah Delay2:

Back1:mov p0,a mov r6,#0ffh
lcall delay1 back1: mov r7,#0ffh ;1cycle
cpl a Here: djnz r7,here ;2cycle
sjmp back1 djnz r6,back1;2cycle
Delay1:mov r0,#0ffh;1cycle ret ;2cycle
Here: djnz r0,here ;2cycle end
ret ;2cycle
end Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
Delay=1+255*2+2=513 cycle
 8051
Interrupts
Interrupts Programming

• An interrupt is an external or internal event that

interrupts the microcontroller to inform it that a device
needs its service.
Interrupts vs. Polling
• A single microcontroller can serve several devices.
• There are two ways to do that:
– interrupts
– polling.
• The program which is associated with the interrupt is
called the interrupt service routine (ISR) or interrupt
handler.
Interrupt :
Steps in executing an interrupt

• Finish current instruction and saves the PC on stack.

• Jumps to a fixed location in memory depend on type of

interrupt

• Starts to execute the interrupt service routine until RETI

(return from interrupt)

• Upon executing the RETI the microcontroller returns to the

place where it was interrupted. Get (pop) PC from stack
Interrupt Sources

• Original 8051 has 6 sources of interrupts

– Reset
– Timer 0 overflow
– Timer 1 overflow
– External Interrupt 0
– External Interrupt 1
– Serial Port events (buffer full, buffer empty, etc)

• Enhanced version has 22 sources

– More timers, programmable counter array, ADC,
more external interrupts, another serial port (UART)
Interrupt Vectors

Each interrupt has a specific place in code memory where

program execution (interrupt service routine) begins.

External Interrupt 0: 0003h

Timer 0 overflow: 000Bh
External Interrupt 1: 0013h
Timer 1 overflow: 001Bh Note: that there
are only 8
Serial : 0023h
memory
Timer 2 overflow(8052+) 002bh locations
between vectors.
Interrupt Enable (IE) register
All interrupt are disabled after reset
We can enable and disable them by IE
Interrupt Priorities
• What if two interrupt sources interrupt at the same time?
• The interrupt with the highest PRIORITY gets serviced
first.
• All interrupts have a power on default priority order.
1. External interrupt 0 (INT0)
2. Timer interrupt0 (TF0)
3. External interrupt 1 (INT1)
4. Timer interrupt1 (TF1)
5. Serial communication (RI+TI)
• Priority can also be set to “high” or “low” by IP reg.
Interrupt Priorities (IP) Register

--- --- PT2 PS PT1 PX1 PT0 PX0

IP.7: reserved
IP.6: reserved
IP.5: timer 2 interrupt priority bit(8052 only)
IP.4: serial port interrupt priority bit
IP.3: timer 1 interrupt priority bit
IP.2: external interrupt 1 priority bit
IP.1: timer 0 interrupt priority bit
IP.0: external interrupt 0 priority bit
Interrupt inside an interrupt
--- --- PT2 PS PT1 PX1 PT0 PX0

 A high-priority interrupt can interrupt a low-priority

interrupy
 All interrupt are latched internally
 Low-priority interrupt wait until 8051 has finished
servicing the high-priority interrupt
 8051
timer/counter
 TIMERS/COUNTERS

Real time applications

1. Delay Generation
2. Pulse counting
3. Frequency measurement
4. Pulse width measurement
5. Baud rate generation
Timers /Counters Programming

• The 8051 has 2 timers/counters: timer/counter 0 and

timer/counter 1. They can be used as
1. The timer is used as a time delay generator.
– The clock source is the internal crystal frequency of
the 8051.
2. An event counter.
– External input from input pin to count the number of
events on registers.
– These clock pulses could represent the number of
people passing through an entrance, or the number of
wheel rotations, or any other event that can be
converted to pulses.
 TIMER

-A timer count machine cycles & provide a reference

time delay.
-Machine cycle of 8051 consist if 12 oscillator
periods.
• Set the initial value of registers. Start the timer and
then the 8051 counts up.
•When the registers equal to 0 and the 8051 sets a
bit to denote time out *(Overflow)
Timer

• A timer count machine cycles & provide a reference

time delay. Machine cycle consists of 12 clocks.
• Set the initial value of registers. Start the timer and
then the 8051 timer counts up.
• Input from internal system clock (for timer).
• When the registers equals to 0
,8051 sets a bit to denote 8051
time out (Overflow)
P2 P1 to
Set LCD
Timer 0 TH0
TL0
 COUNTERS

-A counter of 8051 is incremented in response to a

transition from ‘1’ to ‘0’ at its corresponding external
pin(either T0/T1)

-Thus counter output will be a count or a number

representing the occurrence of such ‘1’ to ‘0’ transitions at
the external pin.

-
Counter
• A counter of 8051 is incremented in response to a
transition from ‘1’ to ‘0’ at its corresponding
external pin(either T0/T1).
• Thus counter output will show the number of events
representing of such ‘1’ to ‘0’ transitions .
– External input from T0 input pin (P3.4) for
Counter 0
– External input from T1 input pin (P3.5) for
Counter 1
TH0 P1 to
LCD
TL0
a switch T0 P3.4

8051
Registers Used in Timer/Counter

• TH0, TL0, TH1, TL1

• TMOD (Timer mode register)
• TCON (Timer control register)
• Since 8052 has 3 timers/counters, the formats of these
control registers are different.
– T2CON (Timer 2 control register), TH2 and TL2 used for
8052 only.
 Timer Registers

TH0 TL0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 0

TH1 TL1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Timer 1
 TMOD Register
• Timer mode register: TMOD
MOV TMOD,#21H
– An 8-bit register
– Set the usage mode for two timers
• Set lower 4 bits for Timer 0 (Set to 0000 if not
used)
• Set upper 4 bits for Timer 1 (Set to 0000 if not
used)
– Not bit-addressable
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
TMOD Register
GATE Gating control when set. Timer/counter is enabled only
while the INTx pin is high and the TRx control bit is
set. When cleared, the timer is enabled whenever the
TRx control bit is set.
C/T Timer or counter selected cleared for timer operation
(input from internal system clock). Set for counter
operation (input from Tx input pin).
M1 Mode bit 1
M0 Mode bit 0
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
Timer modes
TCON Register
• Timer control register: TCON
– Upper nibble for timer/counter, lower nibble for
interrupts
• TR (run control bit)
– TR0 for Timer/counter 0; TR1 for Timer/counter 1.
– TR is set by programmer to turn timer/counter
on/off.
• TR=0: off (stop)
• TR=1: on (start)
(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
 TCON Register

• TF (timer flag, control flag)

– TF0 for timer/counter 0; TF1 for timer/counter 1.
– TF is like a carry. Originally, TF=0. When TH-TL roll over
to 0000 from FFFFH, the TF is set to 1.
• TF=0 : not reach
• TF=1: reach
• If we enable interrupt, TF=1 will trigger ISR.

(MSB) (LSB)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 Timer0 for Interrupt
Steps of Mode 1

1. Choose mode 1 timer 0

– MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
– MOV TH0,#FFH
– MOV TL0,#FCH
3. You had better to clear the flag to monitor: TF0=0.
– CLR TF0
4. Start the timer.
– SETB TR0
 Steps of Mode 1

5. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set
TF0=1.
TH0-TL0= FFFEH, FFFFH, 0000H (Now TF0=1)
6. Keep monitoring the timer flag (TF) to see if it is raised.
AGAIN: JNB TF0, AGAIN
7. Clear TR0 to stop the process.
CLR TR0
8. Clear the TF flag for the next round.
CLR TF0
Mode 1 Programming

XTAL
oscillator ÷ 12
C/T = 0
Timer
overflow
flag
TH TL TF

TR
TF goes high when FFFF 0
 Timer Delay Calculation for XTAL = 11.0592 MHz

(a) in hex
• (FFFF – YYXX + 1) × 1.085 s
• where YYXX are TH, TL initial values respectively.
• Notice that values YYXX are in hex.

(b) in decimal
• Convert YYXX values of the TH, TL register to decimal
to get a NNNNN decimal number
• then (65536 – NNNNN) × 1.085 s
Counter

• These timers can also be used as counters counting events

happening outside the 8051.
• When the timer is used as a counter, it is a pulse outside of
the 8051 that increments the TH, TL.
• When C/T=1, the counter counts up as pulses are fed from
– T0: timer 0 input (Pin 14, P3.4)
– T1: timer 1 input (Pin 15, P3.5)
Block diagram
Serial Communication
 Basics of serial communication
Parallel: expensive - short distance – fast
 Serial :cheaper– long distance, slow
 e.g. different cities by modem- Internet
Basics of serial communication
Start and stop bits
When there is no transfer the signal is high
Transmission begins with a start (low) bit
LSB first
Finally 1 stop bit (high)
Data transfer rate (baud rate) is stated in bps
bps: bit per second
 RS 232 standard
 A network protocol is an established/ agreed set of
rules that determine how data is transmitted between
different devices in the same network, regardless of
any differences in their internal structure .
 Most widely used serial I/O interfacing standard.
 This standard set long before the TTL logic family.
 The input and output voltage levels are not TTL
compatible.
 RS232 Standard

Standard for serial comm (COM port)

1: -3V to -25V;
0: +3V to +25V
Reason: for long distance wired line
Input-output voltage are not TTL
compatible
So, we need MAX232/233 for voltage
converter. Commonly known as line drivers
 RS232 Pins
Connectors:
Minimally, 3 wires: RxD, TxD, GND
Could have 9-pin or 25-pin

DB-25 DB-9
25-Pin Connector 9-Pin Connector
DTE and DCE
 Null Modem Connection
Null modem is a communication method to
connect two DTEs (computer, terminal, printer
etc.) directly using a RS-232 serial cable.
With a null modem connection the transmit and
receive lines are crosslinked.
Depending on the purpose, sometimes also one
or more handshake lines are crosslinked.

10-143
 PIC18 Connection to RS232

Line driver

(a) Inside MAX232 (b) its Connection to the PIC18

Baud Rate
Baud Rate
Communication between 8051 to PC
 Connect TXD to RXD and RXD to TXD from pc to 8051
 Use max232 to transform signal from TTL level to RS232 level
 The baud rate of the 8051 must matched to baud rate of the pc
 PC standard baud rate
 2400-4800-9600-19200-38400
 Serial mode 1 is used
 Timer 1 is used
 The 8051 UART divides the machine cycle frequency by 32
 Machine cycle is 1/12 XTAL frequency
 We use timer1 in mode 2 (auto reload)
 See example 10-1
RxD and TxD pins in the 8051

• TxD pin 11 of the 8051 (P3.1)

• RxD pin 10 of the 8051 (P3.0)

SBUF register

MOV SBUF,#’D’ ;load SBUF=44H, ASCII for ‘D’

MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
Serial control (SCON) Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

SM0 (SCON.7) : mode specifier

SM1 (SCON.6) : mode specifier
SM2 (SCON.5) : used for multi processor communication
REN (SCON.4) : receive enable (by software enable/disable)
TB8 (SCON.3) : transmit bit8
RB8 (SCON.2) : receive bit 8
TI (SCON.1) : transmit interrupt flag set by HW clear by SW
RI (SCON.0) : receive interrupt flag set by HW clear by SW
 Mode of operation

SM0 SM1 MODE operation transmit rate

0 0 0 shift register fixed (xtal/12)
0 1 1 8 bit UART variable (timer1)
1 0 2 9 bit UART fixed (xtal/32 or xtal/64)
1 1 3 9 bit UART variable (timer1)
Power control register
Power control

• A standard for applications where power consumption is

critical
• two power reducing modes
– Idle
– Power down
 Idle mode
• An instruction that sets PCON.0 causes Idle mode
– The internal CPU clock is gated off
– Interrupt, Timer, and Serial Port functions act normally.
– All of registers , ports and internal RAM maintain their data
during Idle
• Any interrupt
– will cause PCON.0 to be cleared by HW (terminate Idle
mode)
– then execute ISR
– with RETI return and execute next instruction after Idle
instruction.
• RST signal clears the IDL bit directly
Power-Down Mode

• An instruction that sets PCON.1 causes power down mode

• Last instruction executed before going into the power down
mode
• The on-chip oscillator is stopped.
• All functions are stopped, the contents of the on-chip RAM
and Special Function Registers are maintained.
• The ALE and PSEN output are held low
• The reset that terminates Power Down
 Difference in Idle and Power Down mode

• In Power Down mode, the oscillator clock

provided to the system is OFF i.e. CPU and
peripherals clock remains inactive in this
mode.
• In Idle Mode, only the clock provided to the
CPU gets deactivated, whereas the peripherals
clock will remain active in this mode.
Port Structure
 I/O Port Programming

Port 1（pins 1-8）

• Port 1 is denoted by P1.

– P1.0 ~ P1.7
• We use P1 as examples to show the operations on ports.
– P1 as an output port (i.e., write CPU data to the
external pin)
– P1 as an input port (i.e., read pin data into CPU bus)
Hardware Structure of I/O Pin( A pin of port 1)

Read latch Vcc

B2
Internal
Pull-Up
Internal CPU D Q P1.X
bus P1.X pin

Write to latch Clk Q M1

B1
Read pin
 Hardware Structure of I/O Pin

• Each pin of I/O ports

– Internally connected to CPU bus
– A D latch store the value of this pin
• Write to latch＝1：write data into the D latch
– 2 Tri-state buffer：
• B1: controlled by “Read pin”
– Read pin＝1：really read the data present at the pin
• B2: controlled by “Read latch”
– Read latch＝1：read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close
Port 1 as Output（Write to a Port）

• Send data to Port 1：

MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK

– Let P1 toggle.
– You can write to P1 directly.
 Writing “1” to Output Pin P1.X

Read latch Vcc

B2
Internal 2. output pin
Pull-Up is Vcc
1. write a 1 to the pin
1 P1.X
Internal CPU D Q
bus P1.X pin
0 output 1
Write to latch Clk Q M1

B1
Read pin
 Writing “0” to Output Pin P1.X

Read latch Vcc

B2
Internal 2. output pin
Pull-Up is ground
1. write a 0 to the pin
0 P1.X
Internal CPU D Q
bus P1.X pin
1 output 0
Write to latch Clk Q M1

B1
Read pin
Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1

B2 external
1. write a 1 to the pin Internal
MOV P1,#0FFH pin=High
Pull-Up
1 1 P1.X
Internal CPU D Q
bus P1.X pin
0 M1
Write to latch Clk Q

B1
Read pin
3. Read pin=1 Read
latch=0
 Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1

B2
1. write a 1 to the pin Internal external
MOV P1,#0FFH Pull-Up pin=Low
1 0 P1.X
Internal CPU D Q
bus P1.X pin
0 M1
Write to latch Clk Q

B1
Read pin
3. Read pin=1 Read
latch=0
Other Pins

• P1, P2, and P3 have internal pull-up resisters.

– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not connects
to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X.
• However, for a programmer, it is the same to program P0,
P1, P2 and P3.
• All the ports upon RESET are configured as output.
Port 0（pins 32-39）

• P0 is an open drain.
– Open drain is a term used for MOS chips in the same
way that open collector is used for TTL chips.
• When P0 is used for simple data I/O we must connect it to
external pull-up resistors.
– Each pin of P0 must be connected externally to a 10K
ohm pull-up resistor.
– With external pull-up resistors connected upon reset,
port 0 is configured as an output port.
Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
8051 P0.1

Port
P0.2
8951 P0.3
P0.4 0
P0.5
P0.6
P0.7
Port 3 Alternate Functions

P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17