Pin configuration of 8085

8085 is an 8-bit microprocessor as it operates on 8 bits. The size of the address bus in
8085 is 16 bits. Thus, can address 64 KB memory. An 8085 microprocessor is
an IC with 40 pins and operates with +5V power supply.
Pin configuration of 8085

The signals of this 40 pin IC is grouped into 7

categories

1.Power supply and clock signals

2.Data bus
3.Address bus
4.Serial I/O ports
5.Control and status signals
6.Interrupts and externally generated signals
7.Direct memory access
 Power supply and clock signals:

•VCC – Pin number 40 denotes VCC, and an external power

supply of + 5 V is provided at this pin.

•VSS – Its pin number is 20. This pin shows the grounded
connection of the microprocessor.

•X1 and X2 – These are represented by pin number 1 and 2

respectively in the pin configuration. These 2 pins are
connected with a crystal or LC network to maintain the
internal frequency of the clock generator.

•CLK (OUT) – It is the 37th pin of the 8085 IC and acts as

the system clock that keeps the record of time duration
required by each operation to get completed.
 Address Bus

The address bus has 16 lines i.e.; it can carry 16 bits at a

time. However, out of 16, 8 are multiplexed with the data
bus and the leftover 8 are separately shown by pin number
21 to 28 in the pin configuration.

These are used to carry the address of data and instruction

from the processor to the memory location and is
unidirectional in nature. These are denoted by A8 to A15 that
represents the 8 MSB of the memory location or input-output
address.

 Divide into 2 part: A15 – A8 (upper)

 AD7 – AD0 (lower).
 A15 – A8 : Unidirectional, known as ‘high order address’.
 AD7 – AD0 : bidirectional and dual purpose (address and data placed once at a time).
 AD7 – AD0 also known as ‘low order address’.
 To execute an instruction, at early stage AD7 – AD0 uses as address bus and alternately as
data bus for the next cycle.
 The method to change from address bus to data bus known as ‘bus multiplexing’.
 Data Bus with multiplexed address bus

The size of the data bus of the 8085 microprocessor is 8

bits. However, to reduce the number of bus lines these
8-bit data bus lines are multiplexed with the 8-bit
address bus.

These are shown by pin number 12 to 19. The address

bus is denoted by A whereas the data bus is denoted by
D. The pin configuration denotes the lower order
multiplexed address and data bus bits from AD0 to AD7.
 Serial I/O ports

It has basically 2 pins.

•SID – SID denotes serial input data pin and its

pin is numbered as 5. With this pin, data is
serially fed to the processor directly through the
input devices.

•SOD – SOD denotes serial output data pin and

its pin number is 4, in the pin configuration of
8085. Once the data is processed in the
microprocessor then this pin represents bit by
bit results at the output devices.
 Control and status signals :
•ALE – ALE is an acronym for address latch enable and is pin number 30 in the
configuration. We know that 8 lower order bits of the 16-bit address bus are
multiplexed with the 8-bit data bus.
This pin gets enabled at the time when the address is present at the multiplexed
address and data bus. Otherwise, it gets disabled showing the absence of an address
on the bus.
•RD – This pin is numbered 32 in the configuration and a low signal in this pin
shows the read operation either from I/O devices or from the memory unit. Thereby
indicating that the data bus is now in a state or position to accept the data from the
memory or I/O devices.
•WR – It is the 31st pin in the pin diagram and a low signal in this pin represents
the write operation at the memory or I/O devices. This indicates that the data
present in the data bus is to be written into the desired memory address or I/O
device by the processor.
•IO/M – It is pin number 34 and indicates the selection of a memory address or
input-output device. This shows whether the read/write operation is to be carried
out at the memory location or at the I/O device. The low signal at this pin shows
that operation is performing over memory location. As against, a high signal at this
pin represents the operation at I/O device.
 Control and status signals :

•S0 and S1 – The pins S0 and S1 represent the status signal at pin number
29 and 33 respectively. These signals show the type of recent operation
of the microprocessor. The table below represents the status of the data
bus under different conditions:
 Control & Status signals
•ALE (Address Latch Enable) signal :

ALE used to de-multiplex address/data bus

Active high signal - generated to show the start of 8085 operation.
When transition 1-to-0: indicate that lines AD7-AD0
(AD7-AD0 = A7-A0) act as address lines.
 Direct Memory Access (DMA)
•HOLD – This signal is generated at pin number 39. This pin generates a signal
to notify the processor that more than one request is present to access the data and
address bus. When this signal gets enabled, the CPU frees the bus after
completion of the recent operation. Once the hold signal gets disabled, the
processor can access the bus again.

•HLDA -This signal is generated at pin number 38. This signal is enabled at the
time when the processor gets HOLD signal and it releases HLDA i.e., hold
acknowledge signal. In order to show that the multiple requests are kept on hold
and will be considered once the bus gets free after the recent operation.
After the disabling of hold request, the HLDA signal becomes low.

•READY -This is the 35th numbered pin in the pin diagram that maintains
synchronization between the processor and peripherals, memory. It is clear that a
microprocessor has a much faster response than peripherals and memory. So, this
pin is enabled when the processor as well as the peripherals and memory both
become ready to begin the next operation. In the case when the READY pin is
disabled, then the microprocessor is in the WAIT state.
 Interrupts and Externally generated signals

Interrupts: Interrupts are the signals that are generated to break the sequence of an
ongoing operation. When an interrupt signal is generated then CPU immediately
stops its recent task under operation and switches to some other program known as
interrupt service routine (ISR) (short program or subroutine that instructs the
microprocessor on how to handle the interrupt).

Maskable interrupts: The interrupts whose request can be either accepted or

rejected by the processor are called maskable interrupts. In 8085 INTR, RST5.5,
RST6.5, RST7.5 and are easily manageable external interrupts.

Non-maskable interrupt: The interrupts whose request has to be definitely

accepted (or cannot be rejected by the processor are called non-maskable interrupts.
Whenever a request is made by non-maskable interrupt, the processor has to
definitely accept that request and service that interrupt by suspending its current
program and executing an ISR. TRAP is a non-maskable interrupt and holds the
topmost priority among all interrupts in the 8085 microprocessor

Hardware, software, internal, external interrupt

 Interrupts and Externally generated signals

TRAP : It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as ISR
and sends the data to backup memory. This interrupt transfers the control to the location
0024H.

RST7.5: It is a maskable interrupt, having the second highest priority among all
interrupts. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 003CH address.

RST 6.5: It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address.

RST 5.5 : It is a maskable interrupt. When this interrupt is executed, the processor saves
the content of the PC register into the stack and branches to 002CH address.
 Interrupts and Externally generated signals

INTR : It is a maskable interrupt, having the lowest priority among all

interrupts. It can be disabled by resetting the microprocessor. When INTR
signal goes high, the following events can occur − The microprocessor checks
the status of INTR signal during the execution of each instruction. When the
INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal. When instructions are
received, then the microprocessor saves the address of the next instruction on
stack and executes the received instruction.

Microprocessor 8085 has 8 software interrupts, RST 0 to RST 7. When

executed they call adress 0 ( RST 0 ) to 56 ( RST 7 ), There are also 3 hardware
interrupts. RST 5.5 to RST 7.5 which forces the CPU to call halfway over the
corresponding software interrupt. So RST 7.5 forces the cpu to call adress 60. (
56 + 4 )
 Limitations of 8085
• The low order address bus is multiplexed with the data bus. The buses
need to be de-multiplexed.
• Appropriate control signals need to be generated to interface memory
and I/O with the 8085.
Generating Control Signals
De-multiplexing Address/Data Lines
De-multiplexed Address & Data bus with Control Signals
Internal Architecture of 8085
 Timing Diagram
Timing Diagram is a graphical representation which represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle: The time required to execute an instruction .

Machine Cycle: The time required to access the memory or input/output devices .

T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation
carried out in one system clock period is called as T-state.
 Timing diagrams
The 8085 microprocessor has 7 basic machine cycle. They are
1. Op-code Fetch cycle(4T or 6T). 4. I/O read cycle(3T)
2. Memory read cycle (3T) 5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle
3. Memory write cycle(3T)
7. Bus idle cycle
 Timing diagrams
Following Buses and Control Signals must be shown in a Timing Diagram:
-Higher Order Address Bus, Lower Address/Data bus, ALE, RD, WR, IO/M
Opcode fetch cycle(4T or 6T) T1 State: During the T1 state, the contents of the program counter are
placed on the 16 bit address bus. The higher order 8 bits are transferred
to address bus (A8-A15) and lower order 8 bits are transferred to
multiplexed A/D (AD0-AD7) bus.
ALE (address latch enable) signal goes high. As soon as ALE goes
high, the memory latches the AD0-AD7 bus. At the middle of the T state
the ALE goes low
T2 State: During the beginning of this state, the RD’ signal goes
low to enable memory. It is during this state, the Opcode is placed
is placed on D0-D7 of the Adress/Data multiplexed bus.
T3 State:
In the previous state the Opcode is placed in D0-D7 of the
A/D bus. In this state of the cycle, the Opcode of the A/D bus
is transferred to the instruction register of the
microprocessor. Now the RD’ goes high after this action and
thus disables the memory from A/D bus.t
 Memory read cycle (3T)
These machine cycles have 3 T-states.
T1 state: The higher order address bus (A8-A15) and
lower order address and data multiplexed (AD0-
AD7) bus. ALE goes high so that the memory
latches the (AD0-AD7) so that complete 16-bit
address are available.

The mp identifies the memory read machine cycle

from the status signals IO/M’=0, S1=1, S0=0. This
condition indicates the memory read cycle.

T2 state: Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. RD’ goes LOW
T3 State: The data which was loaded on the previous state is transferred to the microprocessor. In the middle
of the T3 state RD’ goes high and disables the memory read operation. The data which was obtained from the
memory is then decoded.
Memory write cycle (3T)
These machine cycles have 3 T-states.
T1 state:
The higher order address bus (A8-A15) and lower order
address and data multiplexed (AD0-AD7) bus. ALE goes
high so that the memory latches the (AD0-AD7) so that
complete 16-bit address are available. The mp identifies the
memory read machine cycle from the status signals IO/M’=0,
S1=0, S0=1. This condition indicates the memory write cycle.
T2 state:
Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. WR’ goes LOW

T3 State:
In the middle of the T3 state WR’ goes high and disables the
memory write operation. The data which was obtained from the
memory is then decoded.
I/O read cycle(3T)
I/O write cycle(3T)
STA instruction
ex: STA 526A (store Accumulator contents in memory)
It require 4 m/c cycles 13 T states
1.opcode fetch(4T)
2.memory read(3T)
3.memory read(3T)
4.Memory write(3T)
 Timing diagram for IN C0H
• Fetching the Opcode DBH from the memory 4125H.
• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to the accumulator.
• Let the content of port is 5EH.

It require 3 m/c cycles ,10 T states

opcode fetch(4T)
memory read(3T)
I/O read(3T)
 Timing diagram for MVI B, 43h
• Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
• Read (move) the data 43H from memory 2001H. (memory read)
 Introduction to 8086
The 8086 (also called iAPX 86) is a 16-bit microprocessor chip designed by
Intel between early 1976 and June 8, 1978, when it was released. On the other
hand Intel core i3 June 17, 2009 (announced) January 04, 2010 (launch)
Introduction to 8086
Internal Architecture of 8086
Pin diagram of 8086
 General Purpose Registers
AX (Accumulator)
This is accumulator register. It gets used in arithmetic, logic and data transfer instructions. In
manipulation and division, one of the numbers involved must be in AX or AL

BX (Base Register)
This is base register. BX register is an address register. It usually contain a data pointer used for
based, based indexed or register indirect addressing.

CX (Count register)
This is Count register. This serves as a loop counter. Program loop constructions are facilitated
by it. Count register can also be used as a counter in string manipulation and shift/rotate
instruction.

DX (Data Register)
This is data register. Data register can be used as a port number in I/O operations. It is also used
in multiplication and division.

SP (Stack Pointer)
This is stack pointer register pointing to program stack. It is used in conjunction with SS for
accessing the stack segment.
 General Purpose Registers
BP (Base Pointer)
This is base pointer register pointing to data in stack segment. Unlike SP, we can use
BP to access data in the other segments.

SI (Source Index)
This is source index register which is used to point to memory locations in the data
segment addressed by DS. Thus when we increment the contents of SI, we can easily
access consecutive memory locations.

DI (Destination Index)
This is destination index register performs the same function as SI. There is a class of
instructions called string operations, that use DI to access the memory locations
addressed by ES.

ALU (Arithmetic & Logic Unit)

This unit can perform various arithmetic and logical operation, if required, based on
the instruction to be executed. It can perform arithmetical operations, such as add,
subtract, increment, decrements, convert byte/word and compare etc and logical
operations, such as AND, OR, exclusive OR, shift/rotate and test etc.
 Status Flag Registers:

1. Overflow Flag (OF): Overflow Flag is set to 1 when there is a signed overflow. For
example, when you add bytes 100 + 50 (result is not in range -128…127).

2. Sign Flag (SF): Sign Flag is set to 1 when result is negative. When result is positive it
is set to 0. This flag takes the value of the most significant bit.

3. Zero Flag (ZF): Zero Flag (ZF) is set to 1 when result is zero. For non-zero result this
flag is set to 0.

4. Auxiliary Flag (AF): Auxiliary Flag is set to 1 when there is an unsigned overflow for
low nibble (4 bits).

5. Parity Flag (PF): Parity Flag is set to 1 when there is even number of one bits in
result, and to 0 when there is odd number of one bits.

6. Carry Flag (CF); Carry Flag is set to 1 when there is an unsigned overflow. For
example when you add bytes 255 + 1 (result is not in range 0…255). When there is no
overflow this flag is set to 0.
 Language
>>>High level languages are written in a form that is close to our human language,
enabling to programmer to just focus on the problem being solved. Such as C++, Java,
Pascal, Python, Visual Basic.

Advantages: Easier to modify as it uses English like statements, Easier/faster to write

code as it uses English like statements
Easier to debug during development due to English like statements, Portable code – not
designed to run on just one type of machine

>>>Low level languages are used to write programs that relate to the specific
architecture and hardware of a particular type of computer. They are closer to the native
language of a computer (binary), making them harder for programmers to understand.
Such as Assembly Language, Machine Code

>>>Assembly Language: It is easy distinguishable from a high level language as it

contains few recognizable human words but plenty of mnemonic code.

>>>Machine Code: Programmers rarely write in machine code (binary) as it is difficult

to understand.
 Problems
Write an assembly language Objective to convert the given temperature in Celsius
scale to Fahrenheit scale for 8086 microprocessor.

mov [2000H], 10
mov cl, [2000H]
mov al,9
imul cl
mov cl,5
idiv cl
add al,32
mov [2001H], al

Exercise
Write an assembly language to convert the given temperature in Fahrenheit scale to
Celsius scale for 8086 microprocessor. Data will be taken from the memory (last four
digit of your ID) and result have to available at the memory corresponds to last four
digit of you H.S.C roll number.
 Interrupt: An interrupt is used to cause a temporary halt in the execution of program
and responds to the interrupt service routine (short program or subroutine that instructs
the microprocessor on how to handle the interrupt).

Hardware Interrupt / External Signal: caused by any peripheral device by sending a

signal through a specified pin to the microprocessor.

Software interrupts: The software interrupts are program instructions. These instructions
are inserted at desired locations in a program. While running a program, if software interrupt
instruction is encountered then the processor initiates an interrupt. The 8086 processor
has 256 types of software interrupts. The software interrupt instruction is INT n, where n is
the type number in the range 0 to 255 ie. 00 to FFh.
 Solve them
• Let DS = 0300h; SI = 3126h and CX = 4A3Ch. What will be the physical address of the
memory location? MOV [SI], CX Justify your answer with an ALP. [CAUTION: DS, CS may not
receive immediate data so you should transfer from any other general purpose register]

• Assume DS = 3000h; BX = 1234h, ALPHA = 0012h, SI = 1233h. Determine the

addressing mode and calculate and verify the physical addressing of the memory location
for the following instructions: MOV [BX] + ALPHA, AH MOV [SI] + ALPHA, AH.
[CAUTION: here APHA is just offset value]

• Assume: DS = 3000h, BX = 1000h, SI = 1234h and ALPHA = 0012h. Find the physical
address for the following instruction: MOV AL, [BX] [SI] + ALPHA Verify your result
with an ALP. [CAUTION: DS, CS may not receive immediate data so you should transfer from any other general purpose register]
 Interfacing of 8086
Interfacing: Interface is the path for communication between two components. It is an
integrated circuit which helps in performing basic functions of the CPU. Interfacing is
classified into two types, memory interfacing and I/O interfacing.
Memory Interfacing: Microprocessor needs to access the memory in order to read the
instruction codes as well as the stored data in the memory. So memory and microprocessor
need some signals to read from the memory and write in registers. The interfacing which
match the memory signal requirements and the signals of the microprocessor is known as
memory interfacing of microprocessor.
Input Output (I/O) interfacing: I/O interfaces are the mediums in which data are sent
from internal logic to external sources and from which data are received from external
sources. The main purpose of the I/O interfaces is to transmit and receive data; however,
the portion designated as an I/O interface may contain additional resources, such as
voltage translators, registers, impedances, and buffers.
 8086 Interfacing Pins:

Following is the list of 8085 pins used for interfacing with other
devices –
AD15 - AD0, ALE, RD, WR, READY, RESET, MN/MX
AD0-AD15: These are 16 address/data bus. AD0-AD7 carries low
order byte data and AD8AD15 carries higher order byte data. During
the first clock cycle, it carries 16-bit address and after that it carries
16-bit data.
WR: It stands for write signal and is available at pin 29. It is used to
write the data into the memory or the output device depending on the
status of M/IO signal. When 0 data bus contain valid data.
RD: When 0, data bus driven memory or I/O devices.
RESET: It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

MN/MAX: It stands for Minimum/Maximum and is available at pin 33. It indicates what
mode the processor is to operate in; when it is high, it works in the minimum mode and vice-
versa.
 8086 Interfacing Pins:
ALE: It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines.

Ready: It is available at pin 22. It is an acknowledgement signal from I/O devices that data
is transferred. It is an active high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait state.

74HC373 D latch: The 74HC373; 74HCT373 is an octal D-type transparent latch

with 3-state outputs. The device features latch enable (LE) and output enable (OE)
inputs. ... In this condition the latches are transparent, a latch output will change each time
its corresponding D-input changes.
 8255A
8255A -Programmable Peripheral Interface: The 8255A is a general purpose
programmable I/O device designed to transfer the data from I/O to interrupt I/O under certain
conditions as required. It can be used with almost any microprocessor.
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
U4
34 4
D0 PA0
33 3
Operational modes of 8255: There are two 32
D1 PA1
2
D2 PA2
31 1
basic operational modes of 8255 as 30
D3
D4
PA3
PA4
40

 Bit Set/Reset mode (BSR mode), 29

28
D5
D6
PA5
PA6
39
38

 Input/Output mode (I/O mode).

27 37
D7 PA7
5 18
RD PB0
36 19
WR PB1
9 20
A0 PB2
8 21
A1 PB3
35 22
RESET PB4
23
PB5
6 24
CS PB6
25
PB7
14
PC0
15
PC1
16
PC2
17
PC3
13
PC4
12
PC5
11
PC6
10
PC7

8255A
Bit Set/Reset (BSR) mode
The Bit Set/Reset (BSR) mode is available on port C only. Each line of port C (PC7 -
PC0) can be set or reset by writing a suitable value to the control word register. BSR
mode and I/O mode are independent and selection of BSR mode does not affect the
operation of other ports in I/O mode.
•D7 bit is always 0 for BSR mode.
•Bits D6, D5 and D4 are don't care bits.
•Bits D3, D2 and D1 are used to select the pin of Port C.
•Bit D0 is used to set/reset the selected pin of Port C
Selection of port C pin is determined
as follows:
D3 D2 D1 Bit/pin of port C
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
 Input/Output mode

This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O
modes:

Mode 0 - Simple I/O

Mode 1 - Strobed I/O
Mode 2 - Strobed Bi-directional I/O

Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals.
Port A, port B provide simple I/O operation. The two halves of port C can be either used
together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the
two halves of port C are independent, they may be used such that one-half is initialized as
an input port while the other half is initialized as an output port.

Mode 1 - Strobed Input/output mode

When we wish to use port A or port B for handshake (strobed) input or output operation,
we initialise that port in mode 1 (port A and port B can be initialised to operate in
different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some
of the pins of port C function as handshake lines.
Mode 2 - Strobed Bidirectional Input/Output mode

Only port A can be initialized in this mode. Port A can be used for bidirectional handshake
data transfer. This means that data can be input or output on the same eight lines (PA0 -
PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C
(PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0 or as
handshaking for port B if group B is initialized in mode 1
Exercise:
1. Design a circuit using 8086 microprocessor and 8255A to blink the LED as
follows:
-light up all red LED connected in PORTA of 8255A when all other LED goes off
-light up all green LED connected in PORTB of 8255A when all other LED goes off
-light up all yellow LED connected in PORTC of 8255A when all other LED goes off
2. Design a circuit using 8086 microprocessor and 8255A to blink the LED as
follows:
-light up first LED connected in PORTA of 8255A when all other LED goes off
-light up next LED connected in PORTA of 8255A when all other LED goes off
-so on sequentially