A Constant gm Current Reference Generator with

Purely Off-Chip Resistor

Mohsen Shahghasemi, Kofi M. Odame
Thayer School of Engineering, Dartmouth College
Hanover, New Hampshire, United States of America
Email: {mohsen.shahghasemi.th, kofi.m.odame}@dartmouth.edu

Abstract—Most analog circuits need a current reference gener-

VDD VDD
ator to provide a stable biasing point for the transistors. Given the
limited voltage headroom in advanced node technologies, there
Rbig 3
would be notable restrictions on the tolerance of the reference M3 M4 M3 M4
current deviation. Use of off-chip reference generators adds
to the size of the system while the on-chip reference current Cp3
1 1
L1 L2
generators are still partially dependent on the on-chip resistor 2 2
values which is prone to technology variations. We proposed
an on-chip reference generator with a fully off-chip resistor M1 M2 M1 M2
M : 1 M : 1
which has less sensitivity to the process variations. Monte-
Carlo simulation results shows that the proposed has 31% r Iref Iref
more precision compared to the conventional on-chip reference
generator. Measurement results in 0.18 μm CMOS shows that
the chip produces a stable reference current that is defined based R-r C R C
on an off-chip resistor.
Index Terms—Bias Generation, Reference Circuit, Constant
Current Source, Constant gm , Bandgap Reference (a) (b)
I. I NTRODUCTION
Fig. 1: Constant gm reference current generators: (a) conven-
Constant transconductance (gm ) reference current genera-
tional, split R implementation (b) the proposed structure.
tors are basic circuit building blocks, used to provide process-
independent biases for operational amplifiers, voltage con-
trolled oscillators, and sensor interfaces [1]–[3]. Generally,
constant gm reference current generators produce a transcon-  2
ductance that is inversely-proportional to some resistor value 1 1 2
Iref = 2 1− √ (1)
[4]. To produce a precise current reference, the resistance is R M μ n ox W/L
C
typically implemented as a high-precision off-chip resistor,  
in series with a smaller on-chip resistor [5]. Unfortunately, 2 1
gm1 = 1− √ (2)
process variation of the on-chip resistor might necessitate post- R M
silicon trimming, which is costly and undesirable for mass where W , L, μn and Cox are respectively the width, length,
production. electron mobility, and oxide capacitance of M2 . As Eq. 2
In this paper, we propose a new constant gm reference shows, gm1 is dependent only on the resistance, R, and
current generator that does not require any carefully-controlled transistor sizing ratios. It would be robust to process variation,
on-chip resistor. This obviates the need for expensive post- save for the on-chip r being part of the total resistance. But
silicon trimming. Our novel design produces a constant r is necessary to keep this circuit stable, as we show with the
transconductance that depends solely on an off-chip, high- following analysis.
precision resistor. The loop L1 in Fig. 1 (a) has one dominant zero and one
II. C ONVENTIONAL gm REFERENCE dominant pole:
Figure 1 (a) shows the conventional split resistor (split R) 1 1 + gm1 R
implementation of a constant gm reference current generator. ωz1 = , ωp1 = . ωz1 (3)
(R − r)C 1 + gm1 r
Both branches carry the same current and transistors M3,4
are of the same size while M1 is M times larger than M2 . where C represents the parasitic off-chip capacitor. The loop
The voltage across the resistor R (the series combination of gain (Av (s)) is calculated as
resistors r and R-r) is the difference between the gate-source
voltages of M2 and M1 and will produce the bias current (I ref ). (1 − s/ωz1 ) M
The bias current and the transconductance are calculated as Av (s) = A0 , A0 = √ . (4)
(1 − s/ωp1 ) 3 M −2
 The positive feedback of the loop is not a concern for M <
4 because the DC gain is lower than unity. However, at high (1 − s/ωz1 ) M
frequencies, the loop gain is Av (s) = A0 , A0 = √ (7)
(1 − s/ωp1 )(1 − s/ωp2 ) 3 M −2
1 + gm1 R M in which
Av (|s| >> ωp1 ) = . √ (5)
1 + gm1 r 3 M − 2 1 1
ωz1 = , ωp1 = (1 + gm1 R)ωz1 , ωp2 = . (8)
RC Rbig Cp3
which is higher than unity if r = 0 (note that M = 2 and 3 are
the only options), meaning that the loop is unstable without The Cp3 in Eq. 8 stands for the parasitic capacitor at node
use of the on-chip portion. As depicted in Fig. 2 (a), this 3 and is mainly produced by gate-source capacitance of M4b .
happens because ωz1 has a lower frequency compared to ωp1 High values of Rbig lead to ωp2 smaller than ωz1 and provides
and hence gives rise to the gain and pushes it beyond unity a stable system with the Bode plot shown in Fig. 2 (c). Rbig
while the loop phase is close to zero. The loop has a positive can be implemented by use of one small size MOSFET and
gain so a loop phase equal to zero will cause instability. To does not add considerable amount of area. The value of R in
ensure that the circuit is stable, we need a non-zero value of Eq. 1 and Eq. 2 now can be highly precise which leads to a
r, specifically more accurate I ref and gm1 .

R√ IV. I MPLEMENTATION AND COMPARISON

r> M. (6)
2 Figure 3 shows the implementation of the proposed design
which is composed of four sections. The core bias circuit
This helps because the on-chip portion of the resistor gives
has the structure of Fig. 1 (b) with the addition of cascode
us the leverage to move the pole to a lower frequency while
transistors (M2a,b and M3a,b ) to decrease the channel length
the zero frequency remains the same. As shown in Fig. 2 (b)
modulation on the mirroring transistors (M1a,b and M4a,b ). M
this can prevent the instability by keeping the high frequency
is chosen to be 3 which means that M1a is 3 times larger than
loop gain below unity.
M1b ; this is achieved by choosing a multiplier of 3 for M1a in
order to obtain acceptable matching. R is chosen to be 5.7 kΩ
III. P ROPOSED CONSTANT gm REFERENCE GENERATOR
which provides 40.6 μA reference current. The other section
The proposed structure shown in Fig. 1 (b) uses completely is the start-up circuit which will be addressed later.
off-chip resistor and has the same transistor sizing as Fig. 1 Two sections in Fig. 3 implement Minch structure [6] for
(a). It has an additional pole due to Rbig and the parasitic providing biasing voltages (V b2 and V b3 ) for the cascode
capacitor on node 3. Knowing that the poles at nodes 1 and transistors M2a,b and M3a,b . At the Vb2 bias generation, M7a,b
2 are at high frequencies due to the low resistance of these and M8a,b mirror the current of the core bias circuit. M5a
nodes, the loop gain is now calculated as has the same size as the M1b while the M6a is a big size
device biased very close to sub-threshold. Consequently, the
voltage at node A is equal to V eff,M1b (= V GS,M5a - V GS,M6a
≈ VGS,M5a - V th,M6a ). MM6b and MM2a,b are of the same size
Loop Gain (dB) and carry the same current, hence their V GS is equal. The b2
node voltage could be calculated as
ωz1
(a) ωp1 ω (rad/s)
Vb2 = Veff,M1b + VGS,M2b . (9)

Loop Gain (dB)

Applying this voltage to the gate of M2a,b provides enough
voltage for M1a,b to stay in saturation. The same situation
ωz1 ωp1
(b) ω (rad/s) happens in the Minch Vb3 bias generation section by choosing
M11b as a big size near sub-threshold driven device which sets
the node B voltage to V DD - V eff,M4b .
Loop Gain (dB) The circuit has two states, one with I ref equal to the value
ωz1 ωp1 defined by equation 1 and the other with zero current. To make
(c) ωp2 ω (rad/s)
sure we do not end up with the latter, we use the start-up circuit
Pole that changes the state to the desired one and then turns off to
Zero
have a minimal effect on the main circuit. Looking at the start-
up section in Fig. 3, if node b1 voltage is zero (undesirable
state), Ms1 and Ms2 act as an inverter that turns on Ms3 and
Fig. 2: Bode plot sketch of the loop gain: (a) non-compensated Ms4 ; these then turn on M3a,b and M4a,b and flow current
(b) conventional, split R implementation (c) the proposed into the branches and increase the b1 and b2 node voltages to
structure. the the desirable state. The next step is to turn off the start-up
circuit. Ms2 is a small size device acting as a resistor; once
 VDD

b4 Mres 3
M4a M4b b4 M8a b4 M8b M12b
B

b3 b3 b3
M3a M3b M7a M7b M11a M11b

b3
b2
b2 b2 b2
b3 M2a M2b M6a M6b M10a M10b
Ms2

b1 A
C Ms3 Ms4 M1a M1b M5a b1 M9a b1 M9b
M : 1
Iref
b1 Ms1
R C

Start-up circuit Core bias circuit Vb2 generation Vb3 generation

Fig. 3: The transistor-level implementation of the proposed structure

0
the circuit is back to its normal operation, b1 node voltage
Amplitude (dB)
goes high, Ms1 turns on and sets the node C voltage to zero
-20
and turns off Ms3 and Ms4 to prevent them from affecting the
circuit normal operation. -40 Non Compensated
Split R
Proposed off-chip resistor
Mres (in Fig. 3) implements the Rbig in Fig. 1 (b) and has -60
a resistance of 2.7 MΩ; the parasitic capacitance at node 3 is 10 4 10 5 10 6 10 7

equal to 842 fF which yields a pole frequency of 491 krad/s

0
(78 kHz). This is lower than the zero frequency of 3.5 Mrad/s
(557 kHz) considering an off-chip parasitic capacitor (C) of
Phase( o)

-100
50 pF. To have a fair comparison, a split structure has been
implemented with all device sizing similar to Fig. 3. The only -200 Non Compensated
Split R
difference is removal of the Mres and addition of 30% of the Proposed off-chip resistor
resistance on-chip (r = 1.7 kΩ, R-r = 4 kΩ). These values will -300
10 4 10 5 10 6 10 7
not satisfy Eq. 6 but the loop has a below unity value because Frequency (Hz)
of the body effect of M1a which decreases the gm2 . The split
Fig. 4: Bode plot of the amplitude and phase of the loop gain
also has been simulated with r = 0 to implement a non-
for all three structures.
compensated loop. Figure 4 shows the simulation results for
the loop gain and phase considering 50 pF parasitic off-chip
capacitor for all three cases. The gain for the non-compensated
loop exceeds unity at frequencies higher than 300 kHz while V. M EASUREMENT RESULTS
it always stay below unity for the two other cases.
Both the split R and the proposed structure were fabricated
In order to characterize the mismatch and process variations on the same chip in a 0.18 μm CMOS technology, each
sensitivity, Monte-Carlo simulations has been performed on occupying an area of 0.13 × 0.24 mm2 . Figure 6 (a) shows the
the conventional split R and the proposed design. Figure layout implementation of the proposed structure. The layout
5 (a) and 5 (b) show the results for 200 iterations. The for the conventional, split R structure has the same size with
proposed structure has lower dispersion compared to the split little differences.
R which leads to 31% reduction in the standard deviation. The die micrograph is shown in Fig. 6 (b). The target
This improvement is the result of removing the on-chip part reference current is 40.6 μA and measurement results of the
of the resistor which results in higher precision. The deviation sample chip show 42.1 μA for the split-R structure and 51.2
in the proposed design is caused by the mismatch between μA for the proposed structure. The source of this discrepancy
transistors as well as the process variations on the MOSFET is the physical distance between the proposed circuit and
process transconductance (depicted on Eq. 1 and Eq. 2). ground. Figure 6 (b) shows the distance between the proposed
 30
Occurrence = 39.888 ( A)
(a) 0.24 mm
20 = 1.449 ( A)

10

0.13 mm
(a)
0
36 37 38 39 40 41 42 43 44
I ref ( A)

3.1 mm
30
Occurrence

= 40.635 ( A)
20 (b) = 1.1041 ( A)

M1a Source
10 The Proposed

(b) The proposed

0 0.13 mm

36 37 38 39 40 41 42 43 44 0.24 mm

I ref ( A)

3.1 mm
Fig. 5: Monte-Carlo simulation results: (a) split R implemen-
M1a Source
tation (b) the proposed structure. Split R Split R
0.13 mm
0.24 mm

GND

circuit and ground is considerably higher than for the conven-

tional one. Hence, the trace connecting proposed design to the
ground produces a non-zero voltage due to its resistive voltage
drop. In other words, the voltage of the ground connected to
Fig. 6: The implementation (a) layout of the proposed ref-
the bottom of R (Fig. 3) is still zero (because of the short
erence current generator in 0.18 μm technology (b) the die
distance) while all other grounds are connected to a biased
micrograph of the fabricated chip.
ground with the voltage of some few millivolts. The voltage
across R is now calculated as

VII. F UTURE WORK

VR = VGND,1b + VGS,1b − VGS,1a − VGND,R (10)
Off-chip resistors with different temperature coefficients can
provide a temperature-independent current or transconduc-
in which V GND,1b defines the voltage of the ground connected
tance. Also, the proposed can be used for bandgap voltage
to the source of M1b and V GND,R defines the voltage of
or current references that are intended to be proportional to
the ground connected to the bottom of R. Consequently, the
absolute temperature (PTAT) or complementary to absolute
voltage across R is approximated to
temperature (CTAT) or temperature independent by use of
purely off-chip resistors with any desired thermal coefficient.
VR = VGS,1b − VGS,1a + VGND,1b . (11)
VIII. ACKNOWLEDGMENTS
This V R is higher than the designated voltage and increases This work was supported in part by the U.S. National
the reference current produced by the proposed circuit. The Science Foundation, under Grant No. 1418497, U.S. DoD
conventional design is placed close to the chip ground and CDMRP Grant No s. W81XWH-15-1-0572 and W81XWH-
does not suffer this problem as much as the proposed does. 15-1-0571.
This can be solved in a careful design which places the bias R EFERENCES
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