Subject: Microprocessor and Microcontroller,

Subject code: TIU-UEC-T210, Batch: BCS2A (2nd year) (4th sem)

1. Which of the following microprocessor has 16 bit address bus and 8-bit data
bus
A. 4004
B. 8088
C. 8085
D. 8086

2. An 8-bit microprocessor has an

A. 8-bit data bus
B. 8-bit address bus
C. 8-bit control bus
D. 8 interrupt line

3. If a microprocessor is capable of addressing 64K bytes of memory, its

address-bus width is
A. 16 bits
B. 20 bits
C. 8 bits
D. None of these

4. A microprocessor performs as a
A. CPU
B. Memory
C. Output device
D. Input device

5. In a Microprocessor based system

A. Address bus and data bus both are unidirectional
B. Address bus and data bus both are bidirectional
C. Address bus is unidirectional and data bus is bidirectional
D. Address bus is bidirectional and data bus is unidirectional

6. Which of the following is not a part of the processor

A. Register unit
B. Arithmetic and Logic (ALU) unit
C. Control unit (CU)
D. System bus

7. The number of flag bits in flag register (F) of the 8085 microprocessor is
A. 5
B. 6
C. 4
D. 3

8. Clock frequency and power supply of 8085 microprocessor are

A. 3 MHz and +5 volt
 B. 2 MHz and +7 volt
C. 4 MHz and +10 volt
D. 5 MHz and -5 volt

9. Which of the following is a general purpose register in 8085

A. Flag register (F)
B. Register C
C. Instruction decoder
D. Program Counter (PC)

10. Which of the following is a special purpose register in 8085

A. Register B
B. Register A
C. Register D
D. Register H

11. Which of the following is a valid register pair

A. B-D
B. B-C
C. D-H
D. B-L

12. In 8085
A. Program counter (PC) and Stack pointer (SP) both are 16 bit register as well
as memory pointer
B. Program counter (PC) and Stack pointer (SP) both are 16 bit register but
they are not memory pointer
C. Program counter (PC) and Stack pointer (SP) both are not 16 bit register but
they are memory pointer
D. Program counter (PC) and Stack pointer (SP) are neither 16 bit register nor
memory pointer

13. In 8085, result of arithmetic and logic (ALU) operation is always stored in
A. ALU
B. CU
C. Register A
D. Register B

14. The program counter (PC) in a microprocessor

A. Keeps the address of the next instruction to be fetched
B. Counts the number of instructions being executed on the microprocessor
C. Counts the number of programs being executed on the microprocessor
D. Counts the number of interrupts handled by the microprocessor

15. MOV A,C is

A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

16. LXI H, 2050H is

 A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

17. SUB B is
A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

18. LDA 2050H is

A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

19. MVI A, 3FH is

A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

20. ADI 3FH is

A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

21. INR A is
A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

22. ANA B is
A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

23. ORA C is
A. One Byte Instruction
B. Two Byte Instruction
C. Three Byte Instruction
D. Four Byte Instruction

24. Opcode of instruction MOV A,C is

A. 01111001
B. 01111000
C. 01001111
 D. 01000111

25. Opcode of instruction ADD D is

A. 10000000
B. 10000010
C. 11000000
D. 01000111

26. Opcode of instruction LXI H, 2000H is

A. 00100001
B. 10001110
C. 11111111
D. 11100000
ANSWER: A

27. Opcode of instruction MVI A, 3FH is

A. 01111000
B. 00111110
C. 01111111
D. 00000000

28. Opcode of instruction ADI 3FH is

A. 00100001
B. 11000110
C. 10001110
D. 11111111

29. Opcode of instruction SUB B is

A. 10000000
B. 10000010
C. 11000000
D. 10010000

30. Let the contents of register A (ACC) and register B are CBH and E9H
respectively. After execution of instruction MOV A,B contents of register A (ACC)
and register B are
A. CBH and E9H
B. CBH and CBH
C. E9H and E9H
D. E9H and CBH

31. Let the contents of register A (ACC) and register B are CBH and E9H
respectively. After execution of instruction ADD B contents of register A (ACC) and
register B are
A. CBH and E9H
B. CBH and CBH
C. CBH and 4BH
D. B4H and E9H

32. Let the contents of register A (ACC) and register B are CBH and E9H
respectively. After execution of instruction SUB B contents of register A (ACC) and
register B are
 A. B4H and E9H
B. E9H and E2H
C. CBH and 4BH
D. E2H and E9H

33. Let the content of register A (ACC) is CBH. After execution of instruction
INR A content of the register A is
A. CBH
B. BCH
C. CCH
D. BBH

34. Let the content of register A (ACC) is E9H. After execution of instruction
DCR A content of the register A is
A. E9H
B. 9EH
C. EEH
D. E8H

35. Let the contents of register A (ACC) and register B are 93H and B7H
respectively. After execution of instruction ANA B contents of register A (ACC) and
register B are
A. 93H and B7H
B. 93H and 93H
C. B7H and B7H
D. B7H and 93H

36. Let the contents of register A (ACC) and register B are 93H and B7H
respectively. After execution of instruction ORA B contents of register A (ACC) and
register B are
A. 93H and B7H
B. 93H and 93H
C. B7H and B7H
D. B7H and 93H

37. Let the contents of register A (ACC) and register B are 97H and 65H
respectively. After execution of instruction XRA B contents of register A (ACC) and
register B are
A. 97H and 65H
B. 97H and 97H
C. F2H and 65H
D. 65H and F2H

38. Let the contents of register A (ACC) and register B are 97H and 65H
respectively. After execution of instruction CMP B contents of register A (ACC) and
register B are
A. 97H and 65H
B. 97H and 97H
C. 65H and 65H
D. 65H and 97H

39. Let the content of register A (ACC) is 15H. After execution of instruction
CMA content of the register A is
A. 15H
B. 51H
C. EAH
D. AEH

40. Let the contents of register A (ACC) and register B are CBH and E9H
respectively. After execution of instruction ADD B status of Flag register (F) is
A. S=1, Z=0, CY=1, AC=1, P=1
B. S=0, Z=0, CY=1, AC=1, P=1
C. S=0, Z=0, CY=0, AC=1, P=1
D. S=1, Z=1, CY=0, AC=0, P=1

41. Let the contents of register A (ACC) and register B are CBH and E9H
respectively. After execution of instruction SUB B status of Flag register (F) is
A. S=0, Z=0, CY=1, AC=1, P=1
B. S=0, Z=0, CY=0, AC=1, P=1
C. S=1, Z=1, CY=0, AC=0, P=1
D. S=1, Z=0, CY=1, AC=1, P=1

42. Let the content of register A (ACC) is CBH. After execution of instruction
INR A status of Flag register (F) is
A. S=0, Z=0, AC=0, P=1
B. S=0, Z=0, AC=1, P=1
C. S=1, Z=0, AC=0, P=1
D. S=1, Z=1, AC=0, P=1

43. Let the content of register A (ACC) is E9H. After execution of instruction
DCR A status of Flag register (F) is
A. S=0, Z=0, AC=0, P=1
B. S=0, Z=0, AC=1, P=1
C. S=1, Z=0, AC=0, P=1
D. S=1, Z=0, AC=1, P=1

44. Let the contents of register A (ACC) and register B are 15H and 93H
respectively. After execution of instruction ANA B status of Flag register (F) is
A. S=0, Z=0, CY=0, AC=0, P=1
B. S=0, Z=0, CY=1, AC=1, P=1
C. S=0, Z=0, CY=0, AC=1, P=1
D. S=1, Z=1, CY=0, AC=0, P=1

45. Let the contents of register A (ACC) and register B are 15H and 93H
respectively. After execution of instruction ORA B status of Flag register (F) is
A. S=1, Z=0, CY=0, AC=0, P=0
B. S=0, Z=0, CY=1, AC=1, P=1
C. S=0, Z=0, CY=0, AC=1, P=1
D. S=1, Z=1, CY=0, AC=0, P=1

46. Let the contents of register A (ACC) and register B are 15H and 93H
respectively. After execution of instruction XRA B status of Flag register (F) is
A. S=1, Z=0, CY=0, AC=0, P=0
B. S=0, Z=0, CY=1, AC=1, P=1
 C. S=0, Z=0, CY=0, AC=1, P=1
D. S=1, Z=1, CY=0, AC=0, P=1

47. Let the contents of register A (ACC) and register B are 15H and 93H
respectively. After execution of instruction CMP B status of Flag register (F) is
A. S=0, Z=0, CY=0, AC=1, P=1
B. S=0, Z=0, CY=0, AC=1, P=0
C. S=1, Z=1, CY=0, AC=0, P=1
D. S=1, Z=0, CY=1, AC=1, P=1