CSE-3105: Microprocessor, Microcontroller & Embedded Systems

EEE-3213: Microprocessor, Microcontroller & Embedded Systems

Department of Computer Science & Engineering

Pundra University of Science & Technology
8086 microprocessor

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8086 microprocessor-Features
The 8086, announced in 1978, was the first 16-bit
microprocessor introduced by Intel Corporation
8086 is a 16-bit processor
 It’s ALU, internal registers works with 16 bit binary word
8086 has a 16-bit data bus
 It can read or write data to a memory either 16bits or 8 bit at a
time
8086 has a 20-bit address bus
 It can address up to 220 = 1MB memory location
In addition, it can address up to 64K of byte-wide
input/output ports

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8086 microprocessor-Features
It is manufactured using high-performance metal-oxide
semiconductor (HMOS) technology
The circuitry on its chip is equivalent to approximately
29,000 transistors
Frequency range of 8086 is 6-10 MHz
It has multiplexed address and data bus AD0 - AD15 and A16
– A19
It has 14 registers each one with 16-bit.
It requires +5V power supply
A 40 pin dual in line package

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Pins and Signals

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Pins and Signals

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Pins and Signals

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Pins and Signals

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Pins and Signals

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Pins and Signals

This is a single
microprocessor configuration .

This is a multi
microprocessor configuration .

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Pins and Signals

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Pins and Signals

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Pins and Signals

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Pins and Signals

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Pins and Signals

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 Simplified Functional Block Diagram of 8086 MP
Various conditions of the
Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
Instruction address of the
Flag decoding unit instructions to be
Register fetched from the
memory and send
through address
bus to the
Timing and
PC/ IP memory
control unit

Control Bus Address Bus

Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
control unit 16
microproces sor
Internal Architecture of 8086 MP

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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18
Internal Architecture of 8086 MP
8086 has two blocks
 BIU (Bus Interface Unit)
• BIU fetches instructions, reads data from memory and I/O ports,
writes data to memory and I/ O ports.
• The BIU handles all transfers of data and addresses on the buses for
the execution unit
 EU (Execution Unit)
• EU executes instructions that have already been fetched by the BIU.
• BIU and EU functions separately
• The execution unit tells the BIU
– To fetch the instruction
– Decode the instruction
– Executes instruction

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Internal Architecture of 8086 MP
BIU contains
 Instruction queue
 Adder
 Segment registrés
 Instruction pointer

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Internal Architecture of 8086 MP
 Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

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8086 Architecture - BIU
Instruction queue
 The BIU stores prefetched bytes in a first-in-first-out register set
called a queue
 When the EU is ready for its next instruction, it simply reads the
instruction byte for the instruction from the queue in the BIU
 A group of First-In-First-Out (FIFO) in which up to 6 bytes of
instruction code are pre fetched from the memory ahead of time.
 This is done in order to speed up the execution by overlapping
instruction fetch with execution.
 This mechanism is known as pipelining.

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Instruction Queue and Pipelining
 Pipelining is a computer organization technique in which successive
steps of an instruction sequence are executed in parallel, so that another
instruction can be begun before the previous one is finished.

 To speed up program execution, the BIU fetches six instruction bytes a

head of time from the memory.

 Feature of fetching the next instruction while the current (first) instruction is
executing is called pipelining as shown in figure.

 From figure is seen that the required time for fetching and execution 3
instructions without pipelining is mare than with pipelining.
8086 Architecture - BIU
Segment register
 The four segment register
• The code segment (CS)
• The stack segment (SS)
• The extra segment (ES)
• The data segment (DS)

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8086 Architecture - BIU
• The code segment (CS)
– 16 bit
– It holds the upper 16 bits of the starting or base address for the current
code segment
– IP contains the distance or offset from this address to the next instruction
byte to be fetched.
– BIU computes the 20-bit physical address by logically shifting the contents
of CS 4-bits to the left and then adding the 16-bit contents of IP.
• The stack segment (SS)
– 16-bit
– It is used to hold the upper 16 bits of the starting address for the program
stack
– Points to the current stack.
– The 20-bit physical stack address is calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for stack instructions such as PUSH and
POP.
– In based addressing mode, the 20-bit physical stack address is calculated
from the Stack segment (SS) and the Base Pointer (BP).
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8086 Architecture - BIU
• The extra segment (ES)
– 16-bit
– Points to the extra segment in which data (in excess of 64K
pointed to by the DS) is stored.
– String instructions use the ES and DI to determine the 20-bit
physical address for the destination.
• The data segment (DS)
– 16-bit
– Points to the current data segment; operands for most instructions
are fetched from this segment.
– The 16-bit contents of the Source Index (SI) or Destination Index
(DI) or a 16-bit displacement are used as offset for computing the
20-bit physical address.

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8086 Architecture - BIU
Instruction pointer
 16-bit
 Always points to the next instruction to be executed within the
currently executing code segment.
 So, this register contains the 16-bit offset address pointing to the
next instruction code within the 64Kb of the code segment area.
 Its content is automatically incremented as the execution of the
next instruction takes place.

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8086 Architecture - EU
EU contains
 Control circuitry
 Instruction décoder
 ALU (Arithmétique Logic unit)
 Flag register
 General purpose register

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8086 Architecture - EU
EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 30
DX can be used as DH and DL
8086 Architecture - EU
Control circuitry
 It directs internal operations
Instruction decoder
 It translates instructions fetched from memory into a series of
actions which the EU carries out
ALU (Arithmetic Logic Unit)
 The EU has 16 bit arithmetic logic unit which can add, subtract,
AND, OR, XOR, increment, decrement, complement

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8086 Architecture-Flag Registers
Flag register
 A flag is a flip-flop which indicates some condition
 A 16-bit flag register in the EU contains nine active flags
 Six of the nine flag are used to indicate some condition
 The six conditional flags are
• The carry flag (CF)
• The parity flag (PF)
• The auxiliary flag (AF)
• The zero flag (ZF)
• The sign flag (SF)
• The overflow flag (OF)

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8086 Architecture-Flag Registers
The three remaining flags in the flag register are used to
control certain operations of the processor
The three control flags are
 The trap flag (TF)
 The interrupt flag (IF)
 The direction flag (DF)

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Functions of Flag Registers
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 34
8086 Architecture - EU
General purpose register
 The EU has four 16-bit general purpose register, AX, BX, CX,
and DX.
 The AX is also called the accumulator

Accumulator Register (AX)

Consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX.

AL in this case contains the low order byte of the word, and AH contains the
high-order byte.

The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit

data to or from an I/O port.

Multiplication and Division instructions also use the AX or AL.

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General Purpose Registers
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX.

BL in this case contains the low-order byte of the word, and BH contains the high-
order byte.

This is the only general purpose register whose contents can be used for
addressing the 8086 memory.

All memory references utilizing this register content for addressing use DS as the
default segment register.

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General Purpose Registers
Counter Register (CX)

Consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX.

When combined, CL register contains the low order byte of the word, and CH
contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a

counter.

Example:

The instruction LOOP START automatically decrements CX by 1 without

affecting flags and will check if [CX] = 0.

If it is zero, 8086 executes the next instruction; otherwise the 8086 branches
to the label START.

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General Purpose Registers
Data Register (DX)

Consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX.

When combined, DL register contains the low order byte of the word, and DH
contains the high-order byte.

Use to hold the high 16-bit result (data) in the case of multiplication and
division

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8086 Architecture - EU
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during execution of instructions that

involve the stack segment in the external memory.

SP contents are automatically updated (incremented/ decremented) due to

execution of a POP or PUSH instruction.

BP contains an offset address in the current SS, which is used by instructions

utilizing the based addressing mode.

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8086 Architecture - EU
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.

Instructions that process data strings use the SI and DI registers together with
DS and ES respectively in order to distinguish between the source and destination
addresses.

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Registers and Special Functions- At a Glance
Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 41
Summery of 8086 MP Registers
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 6 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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Addressing Modes of 8086 MP
8086 Microprocessor
Addressing Modes

Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing
memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes
10. Indirect I/O port Addressing for I/O ports
11. Relative Addressing Group IV : Relative Addressing mode
12. Implied Addressing Group V : Implied Addressing m4o4de
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX] to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing

7. Based Index Addressing When BP holds the base value of EA, BP and SS is
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
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(AH)  (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

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8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data

1. Register Addressing Employed in string operations to operate on string

data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = ( D I)5 2+ 1
8086 Microprocessor Group III : Addressing
Addressing Modes modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register. 53
8086 Microprocessor Group IV : Relative
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA
12. Implied Addressing If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
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8086 Microprocessor Group IV : Implied
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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 8086 Microprocessor
Types of Memory

Processor Memory
 Registers inside a microcomputer
 Store data and results temporarily
 No speed disparity
 Cost 


 Primary or Main Memory


 Storage area which can be directly
Memory accessed by microprocessor
 Store programs and data prior to
Store
execution
Programs
 Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
 ROM, EPROM, Static RAM, DRAM

Secondary Memory
 Storage media comprising of slow
devices such as magnetic tapes and
disks
 Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 56
8086 Microprocessor Memory Segmentation

 In memory, data is stored as bytes. Each byte has a specific address.

 Intel 8086 has 20 lines address bus. With 20 address lines, the memory
that can be addressed is 2^20 bytes. 2^20= 1,048,576 bytes (1 MB).

 8086 can access memory with address ranging from 00000 H to

FFFFF H.

 Each of these segments are addressed by an address stored in

corresponding segment register.

 These registers are 16-bit in size. Each register stores the base address
(starting address) of the corresponding segment.

 Because the segment registers cannot store 20 bits, they only store the
upper 16 bits. 58
8086 Microprocessor Advantages of Memory Segmentation

 Segmentation is used to increase the execution speed of computer

system so that processor can able to fetch and execute the data from
memory easily and fastly.

 Allows the memory capacity to be 1 Mbyte although the actual

addresses to be handled are of 16-bit size

 Allows the placing of code data and stack portions of the same
program in different parts (segments) of memory, for data and code
protection.

 Permits a program and/ or its data to be put into different areas of

memory each time program is executed, ie, provision for relocation
may be done.

59
8086 Microprocessor Memory Segmentation

60
8086 Microprocessor Physical Address Calculation

How is a 20-bit address obtained if there are only 16-bit

registers?

 The 20-bit address of a byte is called its Physical Address.

 But, it is specified as a Logical Address.
 Logical address is in the form of:
Base Address : Offset
 Offset is the displacement of the memory location from the
starting location of the segment.

61
8086 Microprocessor Physical Address Calculation

62
8086 Microprocessor Physical Address Calculation

How is a 20-bit address obtained if there are only 16-bit registers?

 To calculate the effective address of the memory, BIU uses the

following formula:
Effective Address = Starting Address of Segment * 10H + Offset
 To find the starting address of the segment, BIU takes the contents of
a segment register, shifts it one hexadecimal place to the left (same as
multiplying by 10H).
 Then add the required offset to form the 20- bit address

63
8086 Microprocessor
Physical Address Calculation-Example

The value of Data Segment Register (DS) is 2222 H.

To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of
the address.
After appending, the starting address of the Data Segment becomes 22220H.
If the data at any location has a logical address specified as:
2222 H : 0016 H
Then, the number 0016 H is the offset.

2222: 0016  2222  22220 H (2222 x 10 = 22220)

0016  0016 H (Offset)
+ -------
22236 H (The absolute address)

65
8086 Microprocessor
Physical Address Calculation-Example

66
 Physical Address Calculation- More Examples

Example:
If CS=2500 h & IP=95F3 h, what is the physical address?
Solution:
Physical Address Calculation- More Examples
Example:
If CS=24F6h & IP=634Ah, show the;
1- The logical address
2- The offset address
3- The physical address
4- The lower range of the segment
5- The upper range of the segment

Solution:
1- The logical address is the CS: IP content which is: 24F6:634A
2- The offset address is the content of the IP register which is: 634A
3- The physical address:
 Physical Address Calculation- More Examples
4- The lower range of the segment:

5- The upper range of the segment:

Physical Address Calculation- More Examples
Physical Address Calculation- More Examples
Interrupts
of
8086 MP

72
 Interrupt
 An interrupt is a signal from a device attached to a computer, or from
a program within the computer, that tells the OS (operating system) to stop
and decide what to do next. When an interrupt is generated,
computer processor follows to change from one task to another while
ensuring that the tasks do not conflict.
 An interrupt is used to cause a temporary halt in the execution of program.
 The meaning of ‘interrupts’ is to break the sequence of operation.
 While the Microprocessor is executing a program, an ‘interrupt’ breaks the
normal sequence of execution of instructions, diverts its execution to some
other program called Interrupt Service Routine (ISR).
 After executing ISR, IRET (Interrupt Return) returns the control back again
to the main program. Interrupt processing is an alternative to polling.
 Examples
• When your phone rings during a lecture, what will
happen?
• When you are studying then your cell phone rings – what
will you do?
• When you finish talking on the phone then you will
continue with your study
• Now your phone rings again and someone also knocking
at your door then what will you do?
• When being interrupted, you will perform some pre-
defined action
• Interrupt has priority – some interrupt is more important
than the others. For example, asking your phone is more
important than opening the door

74
 Basic Interrupt Terminology
• Interrupt pins: Set of pins used in hardware interrupts
• Interrupt Service Routine (ISR) or Interrupt handler: code used
for handling a specific interrupt
• Interrupt priority: In systems with more than one interrupt inputs,
some interrupts have a higher priority than other
– They are serviced first if multiple interrupts are triggered
simultaneously
• Interrupt vector: Code loaded on the bus by the interrupting device
that contains the Address (segment and offset) of specific interrupt
service routine
• Interrupt Masking: Ignoring (disabling) an interrupt
• Non-Maskable Interrupt: Interrupt that cannot be ignored (power-
down)
75
 The Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices with low data-
transfer rates, like a keyboard or a mouse, in which case polling the
device wastes valuable processing time
• The peripheral interrupts the normal application execution,
requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
• After the processor services the peripheral, the execution of the
interrupted program continues.

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

76
 Use of Interrupt
How to get key typed in the keyboard or a keypad?

Polling
The CPU executes a program that check for the available of data
If a key is pressed then read the data, otherwise keep waiting
or looping!!!

Interrupt
The CPU executes other program, as soon as a key is pressed, the
Keyboard generates an interrupt. The CPU will response to the
interrupt – read the data. After that returns to the original program.
So by proper use of interrupt, the CPU can serve many devices at the
“same time”

77
How to get key typed in the keyboard or a keypad?

interrupt

Doing
Something else

No key pressed

Do key pressed action

Polling
78
 Use of Interrupt
How to control a robot that has sensors to detect obstacles
and makes a turn?
• Polling
– Move forward in a pre-defined unit
– Check sensor reading
– Do nothing if no obstacle or turn if obstacle detected
– Loop back and move forward again
• Controlling a robot by interrupt
– Keeping moving until interrupted by the sensor
– Interrupt received then do pre-defined operation
– After finishing the interrupt service return to
normal operation ie keep moving forward again 79
 Polling Vs Interrupt-Control of a Robot

Move forward
Move forward

Check sensor

interrupt
Stop or turn 80
Interrupt Processing Flow Chart
Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC

81
Steps Involved in Processing an Interrupt Instruction by the Processor
Executes the Interrupt instructions

Jumps to the Interrupt Vector Table

Takes the CS and IP in the Vector Table

Pushes the existing CS and IP on the Stack

Loads the new CS and IP

Jumps to the Interrupt Service Routine

Executes the Interrupt Service Routine

Comes back and continues the Main Program

 Processing of an Interrupt by the 8086

Main Program Push flags register Interrupt Service

Clear IF and TF Routine (ISR)
Push CS and IP
Load CS and IP
Interrupt program
Interrupt :
:
:
Pop IP and CS :
Pop flags register :
:
IRET
 Sources of Interrupts
Three types of interrupts sources are there:
1. An external signal applied to NMI or INTR input pin( hardware interrupt)
2. Execution of Interrupt instruction( software interrupt)
3. Interrupt raised due to some error condition produced in 8086 instruction
execution process. (Divide by zero, overflow errors etc)
 Introduction to 8086 Interrupts
• 8086 can implement 256 different types of interrupts
• The interrupts are divided into 5 groups
• Five groups: external hardware interrupt, software
interrupts, internal interrupts, nonmaskable interrupt, and
reset
• The interrupt routines for external hardware, software,
and nonmaskable interrupts can be defined by user (you
can write your own ISR)

85
 Interrupt Priority
• When more than one interrupt occur then priorities of the
interrupts are compared in order to determine which
interrupt to serve first
• Hardware, software, and internal interrupts are serviced on
a priority basis
• Priority hierarchy groups: internal interrupt, nonmaskable
interrupt, software interrupt, and external hardware
interrupt
• Internal interrupt group has the highest priority
• External hardware interrupt group has the lowest priority
• Within a group, different interrupts have different priority
levels represented by the type number (or interrupt
number)
90
 Interrupt Priority
Interrupt type Priority level
Internal Highest
Non-maskable Very high
software High
External Low

91
 Hardware Interrupts – Interrupt Pins and Timing
• x86 Interrupt Pins
– INTR: Interrupt Request. Activated by a peripheral device to
interrupt the processor.
• Level triggered. Activated with a logic 1.
– /INTA: Interrupt Acknowledge. Activated by the processor to
inform the interrupting device the the interrupt request (INTR) is
accepted.
• Level triggered. Activated with a logic 0.
– NMI: Non-Maskable Interrupt. Used for major system faults such
as parity errors and power failures.
• Edge triggered. Activated with a positive edge (0 to 1) transition.
• Must remain at logic 1, until it is accepted by the processor.
• Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock
cycles.
• No need for interrupt acknowledgement.
 Interrupt Vectors & Interrupt Vector Table
• An interrupt vector is the memory location of an interrupt handler, which
prioritizes interrupts and saves them in a queue if more than one interrupt
is waiting to be handled.
• An "interrupt vector table" (IVT) is a data structure that associates a list
of interrupt handlers with a list of interrupt requests in a table of interrupt
vectors.
• The processor uses the interrupt vector to determine the address of the ISR
of the interrupting device. The interrupt vector is a pointer to the Interrupt
Vector Table.
• In the 8088/8086 processor
– The Interrupt Vector Table occupies the address range from 00000H to
003FFH.
– Each entry in the Interrupt Vector Table is 4 bytes long. The first two
represent the offset address and the last two the segment address of the
ISR.
– The first 5 vectors are reserved by Intel to be used by the processor. The
vectors 5 to 255 are free to be used by the user.
 Circuits for Generating Interrupt Vectors

Interrupt Vector: FFH

Interrupt Vector: any

94
 Interrupt Vector - Example
• Draw a circuit diagram to show how a device with interrupt vector
4CH can be connected on an 8086 microprocessor system.
• Answer:
– The peripheral device activates the INTR line
– The processor responds by activating the INTA signal
– The NAND gate enables the 74LS244 octal buffer
– The number 4CH appears on the data bus
– The processor reads the data bus to get the interrupt vector

95
 Issues in Implementing Interrupts
1. Is there a minimum pulse width required for the INTR signal?
The microprocessor checks INTR, one clock period before the last T-states of an instruction
cycle. In the 8085, the Call instructions require 18 T-states; therefore, the INTR pulse should
be high at least for 17.5 T-states. In a system with 3 MHz clock frequency (such as the SDK-
85 system), the input pulse to INTR should be at leas 5.8 µs long.

2. How long can the INTR pulse stay high?

The INTR pulse can remain high until the interrupt flip-flop is set by the EI instruction in the
service routine. If it remains high after the execution of the EI instruction, the processor will
be interrupted again, as if it were a new interrupt. In Figure 12.3, the manual push button will
keep the INTR high for more than 20 ms; however, the service routine has a delay of 1
second, and the EI instruction is executed at the end of the service routine.

3. Can the microprocessor be interrupted again before the completion of

the first interrupt service routine?
The answer to this question is determined by the programmer. After the first interrupt, the
interrupt process is automatically disabled. In the Illustrative program in section 12.12, the
service routine enables the interrupt at the end of the service routine; in this case, the
microprocessor cannot be interrupted before the completion of this routine. If the instruction
EI is written at the beginning of the routine, the microprocessor can be interrupted again
during the service routine
 DMA
• Direct Memory Access
– The DMA is a process of communication or data transfer controlled by an
external peripheral.
– IO device can transfer data from (to) memory directly.
– When µP controlled data transfer is too slow, the DMA is generally is used.
For example, Data transfer between a floppy disk and R/W memory of the
system.
– The 8085 µP has two pins for DMA communication: HOLD (hold) and
HLDA (Hold Acknowledge)
• HOLD
– an input high signal to this pin initiated DMA. µP releases bus in the
following machine cycle. gets back the control when HOLD is low.
• HLDA
– HOLD Ackn. After releasing the bus µP sends a high signal at this pin to
inform the IO device.
 DMA Block Diagram
• Usually a DMA controller sends the DMA request to MP. The processor
completes the current machine cycle; floats all the bus lines, and sends a
acknowledge signal to HLDA. DMA controller takes the control of the buses
and transfer data directly to memory from the external source by-passing µP.
After data transfer DMA controller sends a low signal at HOLD pin to
terminate the request for DMA. MP gets back its control over the buses.

Address
DMA
contr
Memory IO oller
MPU
control

Data Bus

HOLD
HLDA
Series of Intel and Pentium Microprocessors

• Intel 8088
• Intel 80188
• Intel 80288
• Intel 80388
• Intel 80488
• Intel Pentium
• Intel Pentium Pro
• Intel Pentium II
• Intel Pentium II Xeon
• Intel Pentium III
• Intel Pentium IV
• Intel Dual Core
• Intel Core 2 Duo

99
Series of Intel and Pentium Microprocessors

• Intel 8088
– Introduced in 1979
– It was also 16-bit MP
– It could execute 2.5 million instructions per second
– It could access 1 MB of memory
– It had 22,000 instructions
– It had Multiply and Divide instructions

100
Series of Intel and Pentium Microprocessors

• Intel 80188
– Introduced in 1982
– They were 16-bit MPs
– They had additional components like
• Interrupt Controller
• Clock Generator
• Local Bus Controller
• Counters

101
Series of Intel and Pentium Microprocessors

• Intel 80288
– Introduced in 1982
– It was also 16-bit MP
– It could address 16 MB of memory
– It could execute 4 million instructions per second
– Its clock speed was 8 MHz

102
Series of Intel and Pentium Microprocessors

• Intel 80388
– Introduced in 1986
– It was first 32-bit MP
– It could address 4 GB of memory
– Different versions of 80386 is
• 80386 SX
• 80386 SL / 80386 SLC
• 80386 EX

103
Series of Intel and Pentium Microprocessors

• Intel 80488
– Introduced in 1989
– It was also 32-bit MP
– It had 1.2 million transistors
– Cache memory was introduced

104
Series of Intel and Pentium Microprocessors

• Intel Pentium
– Introduced in March 22,1993
– It was also 32-bit MP
– It was originally named 80586
– It could execute 110 million instructions per sec
– Cache memory
• 8 KB for instructions
• 8 KB for data

105
Series of Intel and Pentium Microprocessors

• Intel Pentium Pro

– Introduced in 1995
– It was also 32-bit MP
– It had 21 million transistors
– Cache memory
• 8 KB for instructions
• 8 KB for data
– It had L2 cache of 256 KB
• L2 cache memory, also called the secondary cache,
resides on a separate chip from the microprocessor chip

106
Series of Intel and Pentium Microprocessors

• Intel Pentium II
– Introduced in 1997
– It was also 32-bit MP
– It could execute 333 million instructions per second
– MMX (Multi-Media-eXtension) technology was
supported
– L2 cache & processor were on one circuit
• Level 3 cache is now the name for the extra cache built into
motherboards between the microprocessor and the main
memory

107
Series of Intel and Pentium Microprocessors

• Intel Pentium II Xeon

– Introduced in 1998
– It was also 32-bit MP
– It was designed for servers
– L1 cache of 32 KB & L2 cache of 512 KB, 1MB
or 2 MB

108
Series of Intel and Pentium Microprocessors

• Intel Pentium III

– Introduced in 1999
– It was also 32-bit MP
– Its clock speed was 1GHz

109
 Series of Intel and Pentium Microprocessors

• Intel Pentium IV
– Introduced in 2000
– It was also 32-bit MP
– L1 cache was of 32 KB & L2 cache of 256 KB
– It had 42 million transistors
– All internal connections were made from
aluminum to copper

110
Series of Intel and Pentium Microprocessors

• Intel Dual Core

– Introduced in 2006
– It was 32-bit
– It had two cores
– It supported SMT technology
– SMT: Simultaneously Multi-Threading
• E.g.: Adobe Photoshop supported SMT

111
Series of Intel and Pentium Microprocessors

• Intel Core 2 Duo

– Introduced in 2006
– It was 32-bit
– Max. CPU clock rate is 1.06 GHz to 3.5 GHz

112
8086 Microprocessor
8085 and 8086 Comparison

113
8086 Microprocessor
8086 and 8088 comparison

8086 8088

Similar EU and Instruction set ; dissimilar BIU

16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 – AD15 demultiplexing AD0 – AD7

20-bit address bus 8-bit address bus

Two banks of memory each of 512 Single memory bank

kb

6-bit instruction queue 4-bit instruction queue

Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz

In MIN mode, pin 28 is assigned the In MIN mode, pin 28 is assigned the
signal M / 𝐈𝐎 signal IO / 𝐌̅

To access higher byte, 𝐁𝐇𝐄 signal is No such signal required, since the
used data width is only 1-byte
114
8086 Microprocessor
Multiprocessor System and Co-processor

Multiprocessor A microprocessor system comprising of two or more

processors
system
Distributed processing: Entire task is divided in to
subtasks

Intel 8087 Co-processor works in parallel with a 8086

in the maximum mode

Advantages Better system throughput by having more than one

processor

Each processor have a local bus to access local

memory or I/O devices so that a greater degree of
parallel processing can be achieved

System structure is more flexible.

One can easily add or remove modules to change the
system configuration without affecting the other
modules in the system

115
 Microcontrollers
• An embedded microcontroller is a chip which is
a computer processor with all it’s support
functions (clocking and reset), memory, and i/O
built into the device.

Power Control
distribution store
Reset
control

Clock and
timing RAM

Microcontroller block diagram

 Types of Microcontrollers
• Embedded
– All the hardware required to run the application is provided
on the chip. typically: power, reset, clock, memory and IO.
• External memory
– some microcontrollers allow the connection of external
memory.
 Processor Architecture
• Harvard and Princeton
– US govt asked for computer to be used with naval shell distance
for varying elevations and environmental conditions.
– Princeton provided ‘Von Neumann’ architecture where common
memory space are used for storing program and data. Memory
unit is responsible for arbitrary access to memory space
between reading instructions and passing data back and forth
with processor and its internal registers.
• Advantages: simple memory interfacing and management.

– Harvard proposes a design that used separate memory banks for

program storage, the processor stack, and variable RAM.
• Advantage: execute instruction in fewer cycles than Von Neumann.
Princeton Architecture Block Diagram

instruction decode
program ROM

Data

Add memory
Variable RAM interface unit Processor and built-
Ctrl in registers

Stack RAM
Harvard Architecture Block Diagram

Data

Add instruction
decode
Ctrl

PC Stack
program ROM Variable RAM

Data
Processor and
Add
built-in
registers Ctrl
 CISC & RISC
• CISC versus RISC
– RISC stands for “Reduced Instruction Set
Computers”. Instructions are as bare a minimum as
possible to allow users to design their own operations.
– CISC stands for “Complex Instruction Set
Computers”. Large number of instructions, each
carrying out a different permutation of the same
operation.
 Microcontroller Memory Types
• Control store
– program memory or firmware. this memory space is the
maximum size of the application that can be loaded into
the microcontroller and that the application also
includes all the low-level code and device interface
necessary to execute an application.
– nonvolatile
– 8051 has 5 different types of control store : none, mask
ROM, PROM, EPROM and EEPROM/Flash
 Microcontroller Memory Types
• Variable area (RAM)
– 4 types variable data storage: bits, registers, variable
RAM, PC stack.
– in 8051 they are implemented as SRAM.
– program counter stack
– part of the RAM.
– LIFO memory.
– must be initialized by the starting address of the
stack area.
 Microcontroller Features
• Clock/Oscillator
• IO pins
• interrupts
Basic features

• timers
• Peripherals
• ADC inputs
• DAC outputs
• PWM outputs
 Comparing µC with µP
• General-purpose
microprocessors contains
o No RAM
 Have the advantage of versatility on the amount of
o No ROM RAM, ROM, and I/O ports
o No I/O ports
• Microcontroller has
o CPU (microprocessor)
o RAM
o ROM
o I/O ports
 The fixed amount of on-chip ROM, RAM, and
o Timer number of I/O ports and less computing power;
o ADC and other peripherals suitable for very specific purpose with much less
cost.
 Applications

 Home
 Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, TVs, cable TV tuner, VCR,
camcorder, remote controls, video games, cellular phones, musical
instruments, sewing machines, lighting control, paging, camera, pinball
machines, toys, exercise equipment.
 Office
 Telephones, security systems, fax machines, microwave, copier, laser
printer, color printer, paging.
 Auto
 Navigation system, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate control,
cellular phone, keyless entry.
 Examples of 8-bit µC

– Motorola’s 6811
– Intel’s 8051
– Zilog’s Z8
The 8051 family has the largest number of
– Microchip’s PIC diversified (multiple source) suppliers:
o Intel (original)
o Atmel
o Philips/Signetics
o AMD
o Infineon (formerly Siemens)
o Matra
o Dallas Semiconductor/Maxim
8051 µC
8051 µC Pin Diagram
Pin Description Summery
 8051 µC features
• Intel introduced 8051, referred as MCS-51, in 1981
• The 8051 is an 8-bit processor
• The CPU can work on only 8 bits of data at a time
• 1 to 16 MHz clock
• The 8051 has
• 128 bytes of RAM
• 4K bytes of on-chip ROM
• Two timers
• One serial port
• Four I/O ports, each 8 bits wide
• 2 external and 3 internal interrupt sources
 8051 µC features
• 8051 instruction cycle consists of 12 clock cycles.
• Application should be run using slower clock speed to reduce power
consumption.
• Dallas version of 8051 is 87C51 has EPROM as control store and CMOS
device:
• 24Mhz
• 12 cycle per instruction
• 4Kbyte of Control store
• 128 bytes of RAM
• 32 I/O lines
• Two 8/16-bit times
• Multiple internal and external interrupts sources
• Programmable serial ports
• Interface upto 128Kbytes of external memory
 8051 µC Block Diagram
Frequency
Reference Counters

Oscillator 4K Prog 128 B 2 16-bit

timers/
Memory RAM counter

8051
CPU

64K bus I/O Serial port/

Internal expansion ports UART
interrupt control

External Ports/IO/ Tx Rx
Control
Interrupt ADD/Data
bus
UART  Universal Asynchronous Receiver and Transmitter also known as serial port. It is a full
duplex port which able to transmit & receive data simultaneously at different data rates.
MPU Based System-Example
MCU Based System-Example