UEC3361 Digital System Design

Unit 2: Lecture-4
Adders
Dr. C. VINOTH KUMAR
Associate Professor, ECE Dept.
 Lecture Schedule
Lecture 1 Logic Minimization using Karnaugh’s Map: 3 Variables and
4 Variables
Lecture 2 Logic Minimization using Karnaugh’s Map: 5 Variables
Lecture 3 Logic Minimization using Quine Mc-Cluskey Method
Lecture 4 Arithmetic operations: Half adder, Full Adder, Ripple Carry
Adder, Carry Lookahead Adder
Lecture 5 Arithmetic operations: Half Subtractor, Full Subtractor and
Adder/Subtractor
Lecture 6 Arithmetic Operations: Binary Multipliers
Lecture 7 Selection Logic: Magnitude Comparator
Lecture 8 Selection Logic: Multiplexer and Demultiplexer.
Lecture 9 Selection Logic: Decoder, Encoder and Priority Encoder
 Session Objectives
• To design and implement half adder and full
adder circuits.
• To design and implement Ripple Carry
Adder, Lookahead Adder
• To model Half Adder & Full Adder using
VHDL.
• To model Ripple Carry Adder, Lookahead
Adder using VHDL.
 Session Outcomes
• At the end of this session, participants will be
able to
• Design, Implementation and VHDL Modeling of
half adder, full adder, Ripple Carry Adder and
Lookahead Adder.
 Logic Circuits
• Logic Circuits
– Combinational or Sequential
• Combinational Logic Circuits
“A combinational logic circuit consists of logic
gates whose outputs at any time are determined
from only the present combination of inputs”
– It performs an operation that can be specified
logically by a set of Boolean functions.
– Examples: Adder circuits, Code converters, etc.

'n' inputs Combinational 'm' outputs

. .
.
.
Circuit .
.
 Logic Circuits
• Sequential Logic Circuits
“A sequential logic circuit consists of logic gates
whose outputs depend not only on present values of
inputs, but also on past inputs”
– Sequential logic circuits employ storage elements
in addition to logic gates to store the state of the
past inputs.
– The circuit behaviour must be specified by a time
sequence of inputs and internal states.
– Examples: Registers, Counters, etc
Inputs Combinational
Circuit Outputs
Memory
Elements
Feedback path
 Logic Circuits
• Logic Circuit Design
– Input: Specifications – word description
– Output: Optimized logic diagram
• Design Procedure
1. From the given specifications,
a) Identify the number of inputs & outputs and Assign
arbitrary (letter) symbols to the inputs & outputs
b) Draw the block diagram.
2. Derive a truth table that defines the relationship
between the inputs and outputs.
In a truth table, if we have ‘n’ inputs then there will be
2n possible input combinations
3. Obtain simplified Boolean expression for each
output as a function of the input variable.
4. Implement with logic diagram.
 Logic Circuits
• Design Constraints
– In designing a combinational circuit certain
constraints are to be considered.
• Minimum no. of gates must be used.
• Minimum no. of inputs must be given to the gates.
• Circuit should have minimum no. of interconnections.
• The propagation time of the signals through the gate
should be minimum.
 Adders
• Binary adders
– A combinational circuit that performs the
arithmetic operations of addition with binary
numbers.
– Half Adder
– Full Adder
– Ripple Carry Adder
– Carry Lookahead Adder
 Half Adder
• Half adder
– This circuit needs two binary inputs and two
binary outputs. (No carry from the previous stage
is considered)
– Step 1: Derive block diagram
• The input variables designate the augend and addend
bits
• The output variables produce the sum and carry.
• Assign symbols A and B to the two inputs and Sum
Carry to the outputs.
 Half Adder
• Half adder
– Step: 2 Derive the truth table

– Step: 3 Obtain minimized Boolean equation

Sum  AB  AB  A  B
 Half Adder
• Half adder
– Step: 3 Obtain minimized Boolean equation

Carry  AB

– Step-4: Draw the logic diagram

 Full Adder
• Full Adder
– The difference between a half-adder and a full-
adder is that the full-adder has three inputs and
two outputs, whereas half adder has only two
inputs and two outputs.
– Step 1: Derive the block diagram
• Addition of n-bit binary numbers requires the use of a
full adder, and the process of addition proceeds on a bit-
by-bit basis, right to left, beginning with the least
significant bit.
• After the least significant bit, addition at each position
adds not only the respective bits of the words, but must
also consider a possible carry bit from addition at the
previous position.
 Full Adder
• Full Adder
– Step 1: Derive the block diagram
• A full adder is a combinational circuit that forms the
arithmetic sum of three bits.
• It consists of three inputs and two outputs.
– Two of the input variables, denoted by xi and yi ,
represent the two significant bits to be added.
– The third input ci , represents the carry from the
previous lower significant position.
• Two outputs are necessary because the arithmetic sum
of three binary digits ranges in value from 0 to 3, and
binary representation of 2 or 3 needs two bits.
– The two outputs are designated by the symbols ‘s’ for
sum and ‘ci+1’ for carry.
 Full Adder
• Full Adder
– Step 1: Derive the block diagram

xi s

yi Full Adder
ci+1
ci
 Full Adder
• Design Example – Full Adder
– Step 2: Derivation of truth table that defines the
relationship between the inputs and outputs

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0

1 0 0 0 1
1 0 1 1 0
1 1 0 1 0

1 1 1 1 1
 Full Adder
• Design Example – Full Adder
– 3: Obtaining simplified Boolean expression for
each output as a function of the input variable
xiyi xiyi
ci ci
 Full Adder
• Design Example – Full Adder
– 4: Implementation with logic diagram
xi
si
yi

ci

ci+1
 Full Adder
• Design Example – Full Adder
– 4: Implementation with logic diagram

si
 Full Adder
• Using two half adders
– The half adder adds two input bits and generates a carry
and sum, which are the two outputs of a half adder.
– Full adder takes in an additional carry in bit.
– With the addition of an OR gate to combine their carry
outputs, two half adders can be combined to make a full
adder.
– Steps
• Connect first half adder to inputs xi and yi. Outputs are s1
and c1.
• connect s1 and ci to the second half adder. Its sum output
is the final sum si.
• OR the two carry bits to generate the final carry out ci+1.
 Full Adder
• Using two half adders

xi
yi si

ci+1

ci
Full Adder (using Half Adders)
 Binary Adder
• A binary adder is a digital circuit that produces the
arithmetic sum of two binary numbers.
• It can be constructed with full adders connected in
cascade, with the output carry from each full adder
connected to the input carry of the next full adder in
the chain.
• The input carry to the least significant position is
fixed at 0.
• Addition of n-bit numbers requires a chain of n full
adders or a chain of one-half adder and n–1 full
adders.
4-bit Binary Ripple Carry Adder
• Four full-adder (FA) circuits are connected to
provide a four-bit binary ripple carry adder.
4-bit Binary Ripple Carry Adder
• Four full-adder (FA) circuits are connected to
provide a four-bit binary ripple carry adder.
– The augend bits of A and the addend bits of B are
designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bit.
– The carries are connected in a chain through the full adders.
– The input carry to the adder is C0, and it ripples through
the full adders to the output carry C4.
– The S outputs generate the required sum bits.
4-bit Binary Ripple Carry Adder
• Consider the two binary numbers A = 1011 and B =
0011.
• Their sum S = 1110 is formed with the four-bit
adder as follows
8-bit Binary Ripple Carry Adder
• Eight full-adder (FA) circuits are connected to
provide a 8-bit binary ripple carry adder.
 Carry Lookahead Adder
• Carry propagation
– The addition of two binary numbers in parallel
implies that all the bits of the augend and addend
are available for computation at the same time.
– As in any combinational circuit, the signal must
propagate through the gates before the correct
output sum is available in the output terminals.
– The total propagation time is equal to the
propagation delay of a typical gate, times the
number of gate levels in the circuit.
– The longest propagation delay time in an adder is
the time it takes the carry to propagate through
the full adders.
 Carry Lookahead Adder
• Carry Propagation
– Since each bit of the sum output depends on the
value of the input carry, the value of Si at any
given stage in the adder will be in its steady-state
final value only after the input carry to that stage
has been propagated.
 Carry Lookahead Adder
• Carry Propagation
– Let us consider the output S3.
• Inputs A3 and B3 are available as soon as input
signals are applied to the adder. But, the input
carry C3 does not settle to its final value until
C2 is available from the previous stage.
• Similarly, C2 has to wait for C1 and so on down
to C0.
• Thus, only after the carry propagates and
ripples through all stages will the last output S3
and carry C4 settle to their final correct value.
• The number of gate levels for the carry
propagation can be found from the circuit
of the full adder.
 Propagate & Generate Logic
• Let us redraw the full adder circuit with
generate (G) and propagate (P) signals.
 Propagate & Generate Logic
• Truth Table for Full Adder A, B, C – Inputs

K – Kill
K  AB

P – Propagate
P  A B

G – Generate
G  A B

Sum (S)
Carry Out (C) – Outputs
 Propagate & Generate Logic
• Let us redraw the full adder circuit with
generate (G) and propagate (P) signals.
 Propagate & Generate Logic
• The input and output variables use the subscript i
to denote a typical stage of the adder.
• The signals at Pi and Gi settle to their steady-state
values after they propagate through their respective
gates.
• These two signals are common to all half adders and
depend on only the input augend and addend bits.
• The signal from the input carry Ci to the output
carry Ci+1 propagates through an AND gate and an
OR gate, which constitute two gate levels.
– If there are four full adders in the adder, the output carry
C4 would have 2*4 = 8 gate levels from C0 to C4.
– For an n -bit adder, there are 2 n gate levels for the carry
to propagate from input to output.
4-bit Carry Look Ahead Adder
• Four Carry Look Ahead Adder
4-bit Carry Look Ahead Adder
• Four Carry Look Ahead Adder
4-bit Carry Look Ahead Adder
• Four Bit Carry Look Ahead Adder
4-bit Carry Look Ahead Adder
• Four Bit Carry Look Ahead Adder
4-bit Carry Look Ahead Adder
• Four Bit Carry Look Ahead Adder
 Review Questions
1. What are combinational logic circuits?
2. What are sequential logic circuits?
3. What is half adder?
4. What is full adder?
5. Design and implement half adder using logic gates.
6. Design and implement full adder using logic gates.
7. What is binary parallel adder?
8. What is ripple carry adder?
9. Design and implement 4-bit binary parallel adder.
10.Design and implement 8-bit binary parallel adder.
11.Why carry look ahead adder is required?
12.What are propagate, generate and kill logic?
 Review Questions
13.Construct 4-bit carry look ahead adder.
14.State the merits and demerits of carry look ahead
adder.
15.Write VHDL Source Code and test bench for half
adder.
16.Write VHDL Source Code and test bench for full
adder.
17.Write VHDL Source Code and test bench for 4-bit
ripple carry adder.
18.Write VHDL Source Code and test bench for 4-bit
carry look-ahead adder.
 Session Summary
• In this lecture, we have discussed about
• Design, Implementation and VHDL Modeling of
half adder, full adder, Ripple Carry Adder and
Lookahead Adder.
Text Books & Reference Books
• Test Book
1. M. Morris Mano and Michael D. Ciletti, Digital Design Pearson, Sixth
Edition, 2018.
• Reference Books
1. Salivahanan S and Arivazhagan S, Digital Circuits and Design,
Oxford University Press, Fifth Edition, 2017.
2. John F. Wakerly, Digital Design Principles and Practices, Prentice
Hall, Fourth Edition, 2012.
3. Charles H. Roth and Larry L. Kenney Fundamentals of Logic
Design, Cengage learning, Seventh Edition, 2018.
4. Donald D. Givone, Digital Principles and Design, Tata McGraw Hill,
2003.
5. Samir Palnitkar, Verilog HDL A guide to digital design and synthesis,
Pearson, 2nd edition, 2003.
Thank You