Device & Technology Impact on

Low Power

Dr. Rudra S. Dhar

Dept. of ECE

National Institute of Technology Mizoram

Rudra S. Dhar 1
Overview
1. Dynamic Dissipation in CMOS

2. Transistor scaling

3. Impact of technology Scaling,

4. Technology & Device innovation

Rudra S. Dhar 2
Dynamic Dissipation in CMOS

Power dissipation in CMOS circuits

Dynamic power dissipation (dominant)
Short-circuit power dissipation
Leakage power dissipation
Dynamic power dissipation

: effective (switched) capacitance

: clock frequency
: switching activity
: supply voltage
: physical capacitance
Rudra S. Dhar 3
 Dynamic CMOS

In static circuits at every point in time (except when

switching) the output is connected to either GND or VDD via
a low resistance path.
fan-in of N requires 2N devices

Dynamic circuits rely on the temporary storage of signal

values on the capacitance of high impedance nodes.
requires only N + 2 transistors
takes a sequence of precharge and conditional evaluation phases to realize logic
functions

Rudra S. Dhar 4
Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
should be smaller in area than static complementary CMOS
Full swing outputs (VOL = GND and VOH = VDD)
Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)
Faster switching speeds
reduced load capacitance due to lower number of transistors per gate (Cint)
so a reduced logical effort
reduced load capacitance due to smaller fan-out (Cext)
no Isc, so all the current provided by PDN goes into discharging CL
Ignoring the influence of precharge time on the switching speed of the gate,
tpLH = 0 but the presence of the evaluation transistor slows down the tpHL

Rudra S. Dhar 6
Properties of Dynamic Gates, con’t
Power dissipation should be better
consumes only dynamic power – no short circuit power consumption since the
pull-up path is not on when evaluating
lower CL- both Cint (since there are fewer transistors connected to the drain
output) and Cext (since there the output load is one per connected gate, not
two)
by construction can have at most one transition per cycle – no glitching
But power dissipation can be significantly higher due to
higher transition probabilities
extra load on CLK
PDN starts to work as soon as the input signals exceed
VTn, so set VM, VIH and VIL all equal to VTn
low noise margin (NML)
Needs a precharge clock

Rudra S. Dhar 7
Power Consumption of Dynamic
Gate
CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

Rudra S. Dhar 8
Dynamic Power Consumption is Data
Dependent Dynamic 2-input NOR Gate
Assume signal probabilities
A B Out
PA=1 = 1/2
0 0 1 PB=1 = 1/2
0 1 0

1 0 0
Then transition probability
P01 = Pout=0 x Pout=1
1 1 0

Switching activity can be higher in dynamic gates!

P01 = Pout=0

Rudra S. Dhar 9
A Solution to Charge Leakage
 Keeper compensates for the charge lost due to the pull-
down leakage paths.
Keeper

CLK Mp Mkp

!Out
A
CL
B

CLK Me

Same approach as level restorer for pass

transistor logic
Rudra S. Dhar 10
 Transistor Sizing

• Once a CMOS gate circuit has bbeen generated, the

only significant step remaining in the design is to
decide on W/L ratios for all devices.
• These ratios usually are selected to provide the gate
with current-driving capability in both directions equal
to that of the basic inverter.
• (W/L)=n and (W/L)p=P, where n is usually 1.5 to 2 and,
for a matched design, p=(μn/μp)n.

Rudra S. Dhar
 Transisor Sizing..

• We should find the input combinations that result in the

lowest output current and then choose sizes that will
make this current equal to that of the basic inverter.
• We consider the parallel and series connection of
MOSFETs and find the equivalent W/L ratios.

Rudra S. Dhar 1
2
 Technology scaling

• Scaling consequences:
– Device area
– Transistor density
– Gate capacitance
– Drain current
– Gate delay
– Power
– Power density
– Interconnects

Rudra S. Dhar 13
 Moore’s Law
Recall that Moore’s Law has been driving CMOS

Corollary: clock speeds have improved

Moore’s Law today

Rudra S. Dhar 1
4
 Scaling
• The only constant in VLSI is constant change
• Feature size shrinks by 30% every 2-3 years
• Transistors become cheaper
• Transistors become faster and lower power
• Wires do not improve
• (and may get worse)

• Scale factor S or K
• Typically
• Technology nodes

S 2

Rudra S. Dhar 1
5
 Dennard Scaling

• Proposed by Dennard in 1974

• Also known as constant field scaling

• Electric fields remain the same as features scale

• Scaling assumptions
• All dimensions (x, y, z => W, L, tox)

• Voltage (VDD)

• Doping levels

Rudra S. Dhar 1
6
Constant Electric Field Scaling

Device Parameter Scaling

Length, L 1/K
Width, W 1/K
Gate oxide thickness, tox 1/K
Supply voltage, VDD 1/K
Threshold voltages, Vtn, Vtp 1/K
Substrate doping, NA K

Rudra S. Dhar 17
Constant Electric Field Scaling(Cont.)
Device Characteristic Scaling
β W / (L tox) K
Current, Ids β (VDD – Vt ) 2 1/K
Resistance, R VDD / Ids 1
Gate capacitance, C W L / tox 1/K
Gate delay, τ RC 1/K
Clock frequency, f 1/ τ K

Dynamic power per gate, P CV 2 f 1/K 2

Chip area, A 1/K 2
Power density P/A 1
Current density Ids /A K

Rudra S. Dhar 18
VLSI Chip Level Scaling Scenario
• A scaling factor (K ) reduces device
dimensions as 1/K.

• Successive generations of technology have

used a scaling K = √2, doubling the number of
transistors per unit area. This produced 0.25μ,
0.18μ, 0.13μ, 90nm and 65nm technologies,
continuing on to 45nm, 32nm and 22nm.

• A 5% gate shrink (S = 1.05) is commonly

applied to boost speed as the process matures.

19
 Technology scaling..

• How is scaling achieved?

– All the device dimensions (lateral and vertical)
are reduced by 1/K
– Concentration densities are increased by K
– Device voltages reduced by 1/K (not in all
scaling methods)
– Typically 1/K = 0.7 (30% reduction in the
dimensions)

Rudra S. Dhar 20
Scaling consequence
• Interconnects scaling:
– Higher densities are only possible if the interconnects
also scale.
– Reduced width increased resistance
– Denser interconnects higher capacitance
– To account for increased parasitics and integration
complexity more interconnection layers are added:
• thinner and tighter layers local interconnections
• thicker and sparser layers global interconnections
and power

Rudra S. Dhar 21
Effects of Scaling Down

• 1-16% short-circuit power at 0.7 micron

• 4-37% at 0.35 micron

• 12-60% at 0.17 micron

Rudra S. Dhar 22
 Butwhatif wewantmorespeed?
 We saw that t pd  Cg VDD Ion

 We can aggressively increase the speed by keeping the

voltage constant.
» Long channel devices:

I  K V2  S t  S 1 1 S  1 S 2
on n GT pd

 This led to the Fixed Voltage Scaling Model which was used
until the 1990s (VDD=5V)

𝑉𝐺𝑇 = 𝑉𝑔𝑠 − 𝑉𝑇

Rudra S. Dhar 23
 FixedVoltageScaling –ShortChannel
 What happens under velocity saturated devices?
Ion  KnVDSat VGT V DSat   S  S 1 1  1
Dominated
by Vdd

 So the on current doesn’t increase leading to less effective

speed increase.
t R C  1 S 1  1 S
pd on g

 The power density still increases quadratically!

PD  fCV 2 A  S  S 1 1 S 2  S 2
DD

24
 Technology Scaling Models
 Fixed Voltage Scaling
» Supply voltages have to be similar for all devices (one battery)
» Only device dimensions are scaled.
» 1970s-1990s
 Full “Denard” Scaling (Constant Electrical Field)
» Scale both device dimensions and voltage by the same factor, S.
» Electrical fields stay constant, eliminates breakdown and
many secondary effects.
» 1990s-2005

 General Scaling –
» Scale device dimensions by S and voltage by U.
» Now!

Rudra S. Dhar 25
 HowaboutLeakagePower?
 The off current is exponentially dependent on the threshold
VT
voltage. n
Ioff  e T

 In the case of Full Scaling, the

leakage current increases
exponentially as VT is decreased!

 Since the 90nm node, static

power is one of the major
problems in ICs.

Rudra S. Dhar 26
 Observations

Capacitance per micron is remaining constant

About 0.2 fF/mm
Roughly 1/5 of gate capacitance

Local wires are getting faster

Not quite tracking transistor improvement
But not a major problem

Global wires are getting slower

No longer possible to cross chip in one cycle

Rudra S. Dhar 27
 WireScaling
 We could try to scale interconnect at the same rate
(S) as device dimensions.
» This makes sense for local interconnect that connects
smaller devices/gates.
» But global interconnections, such as clock signals, buses,
etc. won’t scale in length.

 Length of global interconnect is proportional to die

size or system complexity.
» Die Size has increased by 6% per year (X2 @10 years)
» Devices have scaled, but complexity has grown!

Rudra S. Dhar 28
Nature of Interconnect

Rudra S. Dhar 29
 Local Wire Scaling
 Looking at local interconnect:
» W, H, t, L all scale at 1/S
» C=LW/t1/S
» R=L/WH S So the delay of
local interconnect
» RC=1 stays constant.

 Reminder – Full (Dennard) Scaling of transistors:

» Ron=VDD/Ion α 1
» tpd=RonCg α 1/S
 So the delay of local interconnect still increases
relative to transistors!
Rudra S. Dhar 30
 Local Wire Scaling –Full Scaling
 What about fringe cap?

Rudra S. Dhar 31
Local Wire Scaling - ConstantThickness
 Thickness wasn’t scaled!

Rudra S. Dhar 32
 Local Wire Scaling–Interwire Capacitance
 Without scaling height, coupling gets much worse.

Rudra S. Dhar 33
 Global Wire Scaling
 Looking at global interconnect:
» W, H, t scale at 1/S
» L doesn’t scale!
» C=LW/t1 Long wire delay
» R=L/WH S2 increases
quadratically!!!
» RC=S !!!
2

 And if chip size grows, L actually increases!

Rudra S. Dhar 34
 Global Wire Scaling –ConstantThickness
 Leave thickness constant for global wires

Rudra S. Dhar 35
 WireScaling
 So whereas device speed increases with scaling:
» Local interconnect speed stays constant.
» Global interconnect delays increase quadratically.
 Therefore:
» Interconnect delay is often the limiting factor for speed.
 What can we do?
» Keep the wire thickness (H) fixed.
» This would provide 1/S for local wire delays and S for
constant length global wires.
» But fringing capacitance increases, so this is optimistic.

Rudra S. Dhar 36
 WireScaling
 What is done today?
» Low resistance metals.
» Low-K insulation.
» Low metals (M1, M2) are used for local
interconnect, so they are thin and dense.
» Higher metals are used for global routing, so they
are thicker, wider and spaced farther apart.

Rudra S. Dhar 37
Technology Strategy Roadmap

Rudra S. Dhar 38
 Reference Listing
1. Digital integrated circuits: a design perspective, Jan M. Rabaey,
Anantha P. Chandrakasan,Borivoje Nikolic, 2nd Edition, Pearson
Education, 2003..
2. Practical Low Power Digital VLSI Design, Gary K. Yeap, Springer
London, Limited, 1998.
3. Low power design methodologies, Jan M. Rabaey, Massoud
Pedram, 2nd Ed, Kluwer Academic Publishers, 1996.
4. Additional journal & conference papers/proceedings/ppts available
online.

Rudra S. Dhar 39
The End

Rudra S. Dhar 40