Microprocessor and Microcontroller
Module 4:
Intel 8086 microprocessor- Intel 8086 hardware, Pin description, External memory addressing, Bus
cycles, Interrupt processing - Addressing Modes, Instruction Set, Assembler Directives.
8086 Microprocessor
Slide 1: Title
8086 Microprocessor: Overview, Architecture, Registers, Modes, Addressing, Interrupts, Memory,
Assembly, ALPs, Questions
Slide 2: 8086 Overview
16-bit microprocessor
20-bit address bus → 1 MB memory access
Up to 64K I/O ports
14 internal 16-bit registers
Multiplexed bus: AD0–AD15, A16–A19
Single phase clock (33% duty cycle)
Two modes: Minimum / Maximum
Key improvements over 8085:
o Pipelining (6-byte prefetch queue)
o Instruction queue
o Segmentation
Power: +5V, 40-pin DIP
Slide 3: Internal Architecture (1/2)
Two blocks: BIU and EU
Bus Interface Unit (BIU):
o 16-bit data bus, 20-bit address bus
o Functions: instruction fetch, queue, operand fetch, address generation, bus control
o Instruction queue: up to 6 bytes (FIFO)
o Forms physical address = segment + offset
Execution Unit (EU):
o Decodes & executes instructions
o Uses ALU, control circuitry, decoders, flags
o Fetches instructions from queue, executes, updates flags
o Handles jumps/branches by flushing queue
Slide 4: Register Organization (1/3)
Four groups of registers:
1. Instruction Pointer (IP)
2. Data registers (AX, BX, CX, DX)
3. Pointer & Index registers (SP, BP, SI, DI)
4. Segment registers (CS, DS, SS, ES)
Segment Registers:
CS: Code Segment → instruction fetch (auto-updated on far jumps/calls)
SS: Stack Segment → stack pointer & base pointer
DS: Data Segment → general register data access
ES: Extra Segment → string operations (DI)
Slide 5: Register Organization (2/3)
General Registers (16-bit):
AX: Accumulator (AL + AH) – arithmetic, I/O, string ops
BX: Base Register (BL + BH) – data pointer
CX: Count Register (CL + CH) – loop, shift/rotate, string counter
DX: Data Register (DL + DH) – port addressing, high word in multiply/divide
Slide 6: Register Organization (3/3)
Pointer & Index Registers:
SP: Stack Pointer → program stack
BP: Base Pointer → data in stack segment
SI: Source Index → string source address
DI: Destination Index → string destination
Flag Register (16-bit, 9 active flags):
OF: Overflow
DF: Direction
IF: Interrupt enables
TF: Single step
SF: Sign
ZF: Zero
AF: Auxiliary carry
PF: Parity
CF: Carry
Slide 7: Modes of Operation
Minimum Mode:
MN/MX# = 1
Single microprocessor configuration
Maximum Mode:
MN/MX# = 0
Multiprocessor configuration
Slide 8: Addressing Modes
Implied
Register
Immediate
Direct (memory direct)
Register Indirect (via SI, DI, BX, BP)
Based (displacement + BX/BP)
Indexed (displacement + SI/DI)
Based Indexed (BX/BP + SI/DI)
Based Indexed + Displacement
Slide 9: Interrupts (1/2)
Execution Sequence:
1. Save FLAGS to stack
2. Disable interrupts
3. Fetch interrupt type
4. Jump to ISR (vector table)
5. Return via IRET
Types:
INTR → maskable, enabled via STI/CLI
NMI → non-maskable, type 2 (0008h), higher priority
Slide 10: Interrupts (2/2)
Software Interrupts:
INT → breakpoint (Type 3)
INT n → any of 256 interrupts
INTO → overflow
Single step (TF = 1, Type 1)
Processor Exceptions:
Type 0: Divide error
Type 6: Unused opcode
Type 7: Escape opcode
Slide 11: Memory
Unified program, data, stack memory space
16-bit pointers → 64KB limit, extended with segmentation
Physical address = (segment × 16) + offset
Memory types:
o Program memory (jumps, calls, far/short)
o Data memory (256KB max via 4 segments)
o Stack memory (anywhere, best at even addresses)
Reserved:
o 0000h–02FFh: Interrupt vectors
o FFFF0h: Reset start
Slide 12: 8086 Instruction Types
Data Flow: MOV, PUSH, POP, IN, OUT, etc.
Arithmetic: ADD, SUB, MUL, DIV, CMP, etc.
Bit Manipulation: SHL, ROR, AND, OR, XOR, etc.
Control Transfer: JMP, CALL, RET, LOOP, JCXZ, etc.
String Instructions: MOVS, CMPS, SCAS, LODS, STOS
Interrupts: INT, INTO, IRET
Processor Control: STC, STD, STI
Miscellaneous: NOP, WAIT
Slide 13: Memory Segmentation & Models
Segmentation:
64KB segments: Code, Data, Stack, Extra
Program uses .DATA, .STACK, .CODE
Memory Models:
Small: 1 code, 1 data
Medium: multiple code, 1 data
Compact: 1 code, multiple data
Large: multiple code & data (no array > 64KB)
Huge: multiple code & data (arrays > 64KB allowed)
Slide 14: Most Asked Assembly Programs (ALPs)
Examples:
Add/Sub/Mul/Div of n numbers (16/32-bit)
GCD & LCM
Sorting & searching (max/min)
Shift & rotate ops
Check positive/negative
Count 0s & 1s
Palindrome (bit/nibble)
Packed ↔ Unpacked BCD conversion
BCD ↔ ASCII conversion
Block data transfer
String reverse, compare, length
Fibonacci series
Matrix transpose (3×3)
Odd/Even separation
Square/cube of number
Traffic light controller
Slide 15: Question Bank (Sample)
What is pipelining & segmentation?
Which pins determine mode of operation?
Explain EU & BIU with diagram
Describe 8086 registers and flags
How is 20-bit address generated?
Explain timing diagrams in min/max mode
Types of interrupts, their priority
Procedures vs. Macros
Assembler vs. Linker
Instruction formats & addressing modes
